Bug Summary

File:dev/pci/drm/i915/display/intel_dsi_vbt.c
Warning:line 625, column 27
Value stored to 'i915' during its initialization is never read

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name intel_dsi_vbt.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Shobhit Kumar <shobhit.kumar@intel.com>
24 *
25 */
26
27#include <linux/gpio/consumer.h>
28#ifdef notyet
29#include <linux/gpio/machine.h>
30#include <linux/mfd/intel_soc_pmic.h>
31#include <linux/pinctrl/consumer.h>
32#include <linux/pinctrl/machine.h>
33#endif
34#include <linux/slab.h>
35#include <linux/string_helpers.h>
36
37#include <asm/unaligned.h>
38
39#include <drm/drm_crtc.h>
40#include <drm/drm_edid.h>
41
42#include <video/mipi_display.h>
43
44#include "i915_drv.h"
45#include "i915_reg.h"
46#include "intel_de.h"
47#include "intel_display_types.h"
48#include "intel_dsi.h"
49#include "intel_dsi_vbt.h"
50#include "intel_gmbus_regs.h"
51#include "vlv_dsi.h"
52#include "vlv_dsi_regs.h"
53#include "vlv_sideband.h"
54
55#define MIPI_TRANSFER_MODE_SHIFT0 0
56#define MIPI_VIRTUAL_CHANNEL_SHIFT1 1
57#define MIPI_PORT_SHIFT3 3
58
59/* base offsets for gpio pads */
60#define VLV_GPIO_NC_0_HV_DDI0_HPD0x4130 0x4130
61#define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA0x4120 0x4120
62#define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL0x4110 0x4110
63#define VLV_GPIO_NC_3_PANEL0_VDDEN0x4140 0x4140
64#define VLV_GPIO_NC_4_PANEL0_BKLTEN0x4150 0x4150
65#define VLV_GPIO_NC_5_PANEL0_BKLTCTL0x4160 0x4160
66#define VLV_GPIO_NC_6_HV_DDI1_HPD0x4180 0x4180
67#define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA0x4190 0x4190
68#define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL0x4170 0x4170
69#define VLV_GPIO_NC_9_PANEL1_VDDEN0x4100 0x4100
70#define VLV_GPIO_NC_10_PANEL1_BKLTEN0x40E0 0x40E0
71#define VLV_GPIO_NC_11_PANEL1_BKLTCTL0x40F0 0x40F0
72
73#define VLV_GPIO_PCONF0(base_offset)(base_offset) (base_offset)
74#define VLV_GPIO_PAD_VAL(base_offset)((base_offset) + 8) ((base_offset) + 8)
75
76struct gpio_map {
77 u16 base_offset;
78 bool_Bool init;
79};
80
81static struct gpio_map vlv_gpio_table[] = {
82 { VLV_GPIO_NC_0_HV_DDI0_HPD0x4130 },
83 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA0x4120 },
84 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL0x4110 },
85 { VLV_GPIO_NC_3_PANEL0_VDDEN0x4140 },
86 { VLV_GPIO_NC_4_PANEL0_BKLTEN0x4150 },
87 { VLV_GPIO_NC_5_PANEL0_BKLTCTL0x4160 },
88 { VLV_GPIO_NC_6_HV_DDI1_HPD0x4180 },
89 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA0x4190 },
90 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL0x4170 },
91 { VLV_GPIO_NC_9_PANEL1_VDDEN0x4100 },
92 { VLV_GPIO_NC_10_PANEL1_BKLTEN0x40E0 },
93 { VLV_GPIO_NC_11_PANEL1_BKLTCTL0x40F0 },
94};
95
96struct i2c_adapter_lookup {
97 u16 slave_addr;
98 struct intel_dsi *intel_dsi;
99#ifdef notyet
100 acpi_handle dev_handle;
101#endif
102};
103
104#define CHV_GPIO_IDX_START_N0 0
105#define CHV_GPIO_IDX_START_E73 73
106#define CHV_GPIO_IDX_START_SW100 100
107#define CHV_GPIO_IDX_START_SE198 198
108
109#define CHV_VBT_MAX_PINS_PER_FMLY15 15
110
111#define CHV_GPIO_PAD_CFG0(f, i)(0x4400 + (f) * 0x400 + (i) * 8) (0x4400 + (f) * 0x400 + (i) * 8)
112#define CHV_GPIO_GPIOEN(1 << 15) (1 << 15)
113#define CHV_GPIO_GPIOCFG_GPIO(0 << 8) (0 << 8)
114#define CHV_GPIO_GPIOCFG_GPO(1 << 8) (1 << 8)
115#define CHV_GPIO_GPIOCFG_GPI(2 << 8) (2 << 8)
116#define CHV_GPIO_GPIOCFG_HIZ(3 << 8) (3 << 8)
117#define CHV_GPIO_GPIOTXSTATE(state)((!!(state)) << 1) ((!!(state)) << 1)
118
119#define CHV_GPIO_PAD_CFG1(f, i)(0x4400 + (f) * 0x400 + (i) * 8 + 4) (0x4400 + (f) * 0x400 + (i) * 8 + 4)
120#define CHV_GPIO_CFGLOCK(1 << 31) (1 << 31)
121
122/* ICL DSI Display GPIO Pins */
123#define ICL_GPIO_DDSP_HPD_A0 0
124#define ICL_GPIO_L_VDDEN_11 1
125#define ICL_GPIO_L_BKLTEN_12 2
126#define ICL_GPIO_DDPA_CTRLCLK_13 3
127#define ICL_GPIO_DDPA_CTRLDATA_14 4
128#define ICL_GPIO_DDSP_HPD_B5 5
129#define ICL_GPIO_L_VDDEN_26 6
130#define ICL_GPIO_L_BKLTEN_27 7
131#define ICL_GPIO_DDPA_CTRLCLK_28 8
132#define ICL_GPIO_DDPA_CTRLDATA_29 9
133
134static enum port intel_dsi_seq_port_to_port(struct intel_dsi *intel_dsi,
135 u8 seq_port)
136{
137 /*
138 * If single link DSI is being used on any port, the VBT sequence block
139 * send packet apparently always has 0 for the port. Just use the port
140 * we have configured, and ignore the sequence block port.
141 */
142 if (hweight8(intel_dsi->ports) == 1)
143 return ffs(intel_dsi->ports) - 1;
144
145 if (seq_port) {
146 if (intel_dsi->ports & BIT(PORT_B)(1UL << (PORT_B)))
147 return PORT_B;
148 else if (intel_dsi->ports & BIT(PORT_C)(1UL << (PORT_C)))
149 return PORT_C;
150 }
151
152 return PORT_A;
153}
154
155static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
156 const u8 *data)
157{
158 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(intel_dsi->base.base.dev);
159 struct mipi_dsi_device *dsi_device;
160 u8 type, flags, seq_port;
161 u16 len;
162 enum port port;
163
164 drm_dbg_kms(&dev_priv->drm, "\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "\n");
165
166 flags = *data++;
167 type = *data++;
168
169 len = *((u16 *) data);
170 data += 2;
171
172 seq_port = (flags >> MIPI_PORT_SHIFT3) & 3;
173
174 port = intel_dsi_seq_port_to_port(intel_dsi, seq_port);
175
176 if (drm_WARN_ON(&dev_priv->drm, !intel_dsi->dsi_hosts[port])({ int __ret = !!((!intel_dsi->dsi_hosts[port])); if (__ret
) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->
drm))->dev), "", "drm_WARN_ON(" "!intel_dsi->dsi_hosts[port]"
")"); __builtin_expect(!!(__ret), 0); }))
177 goto out;
178
179 dsi_device = intel_dsi->dsi_hosts[port]->device;
180 if (!dsi_device) {
181 drm_dbg_kms(&dev_priv->drm, "no dsi device for port %c\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "no dsi device for port %c\n"
, ((port) + 'A'))
182 port_name(port))__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "no dsi device for port %c\n"
, ((port) + 'A'));
183 goto out;
184 }
185
186 if ((flags >> MIPI_TRANSFER_MODE_SHIFT0) & 1)
187 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM(1 << 0);
188 else
189 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM(1 << 0);
190
191 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT1) & 3;
192
193 switch (type) {
194 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM0x03:
195 mipi_dsi_generic_write(dsi_device, NULL((void *)0), 0);
196 break;
197 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM0x13:
198 mipi_dsi_generic_write(dsi_device, data, 1);
199 break;
200 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM0x23:
201 mipi_dsi_generic_write(dsi_device, data, 2);
202 break;
203 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM0x04:
204 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM0x14:
205 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM0x24:
206 drm_dbg(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_DRIVER, "Generic Read not yet implemented or used\n"
)
207 "Generic Read not yet implemented or used\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_DRIVER, "Generic Read not yet implemented or used\n"
);
208 break;
209 case MIPI_DSI_GENERIC_LONG_WRITE0x29:
210 mipi_dsi_generic_write(dsi_device, data, len);
211 break;
212 case MIPI_DSI_DCS_SHORT_WRITE0x05:
213 mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
214 break;
215 case MIPI_DSI_DCS_SHORT_WRITE_PARAM0x15:
216 mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
217 break;
218 case MIPI_DSI_DCS_READ0x06:
219 drm_dbg(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_DRIVER, "DCS Read not yet implemented or used\n"
)
220 "DCS Read not yet implemented or used\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_DRIVER, "DCS Read not yet implemented or used\n"
);
221 break;
222 case MIPI_DSI_DCS_LONG_WRITE0x39:
223 mipi_dsi_dcs_write_buffer(dsi_device, data, len);
224 break;
225 }
226
227 if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) < 11)
228 vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
229
230out:
231 data += len;
232
233 return data;
234}
235
236static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
237{
238 struct drm_i915_privateinteldrm_softc *i915 = to_i915(intel_dsi->base.base.dev);
239 u32 delay = *((const u32 *) data);
240
241 drm_dbg_kms(&i915->drm, "\n")__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "\n");
242
243 usleep_range(delay, delay + 10);
244 data += 4;
245
246 return data;
247}
248
249static void vlv_exec_gpio(struct intel_connector *connector,
250 u8 gpio_source, u8 gpio_index, bool_Bool value)
251{
252 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(connector->base.dev);
253 struct gpio_map *map;
254 u16 pconf0, padval;
255 u32 tmp;
256 u8 port;
257
258 if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)(sizeof((vlv_gpio_table)) / sizeof((vlv_gpio_table)[0]))) {
259 drm_dbg_kms(&dev_priv->drm, "unknown gpio index %u\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "unknown gpio index %u\n"
, gpio_index)
260 gpio_index)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "unknown gpio index %u\n"
, gpio_index);
261 return;
262 }
263
264 map = &vlv_gpio_table[gpio_index];
265
266 if (connector->panel.vbt.dsi.seq_version >= 3) {
267 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
268 port = IOSF_PORT_GPIO_NC0x13;
269 } else {
270 if (gpio_source == 0) {
271 port = IOSF_PORT_GPIO_NC0x13;
272 } else if (gpio_source == 1) {
273 drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "SC gpio not supported\n"
);
274 return;
275 } else {
276 drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "unknown gpio source %u\n"
, gpio_source)
277 "unknown gpio source %u\n", gpio_source)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "unknown gpio source %u\n"
, gpio_source);
278 return;
279 }
280 }
281
282 pconf0 = VLV_GPIO_PCONF0(map->base_offset)(map->base_offset);
283 padval = VLV_GPIO_PAD_VAL(map->base_offset)((map->base_offset) + 8);
284
285 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)(1UL << (VLV_IOSF_SB_GPIO)));
286 if (!map->init) {
287 /* FIXME: remove constant below */
288 vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00);
289 map->init = true1;
290 }
291
292 tmp = 0x4 | value;
293 vlv_iosf_sb_write(dev_priv, port, padval, tmp);
294 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)(1UL << (VLV_IOSF_SB_GPIO)));
295}
296
297static void chv_exec_gpio(struct intel_connector *connector,
298 u8 gpio_source, u8 gpio_index, bool_Bool value)
299{
300 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(connector->base.dev);
301 u16 cfg0, cfg1;
302 u16 family_num;
303 u8 port;
304
305 if (connector->panel.vbt.dsi.seq_version >= 3) {
306 if (gpio_index >= CHV_GPIO_IDX_START_SE198) {
307 /* XXX: it's unclear whether 255->57 is part of SE. */
308 gpio_index -= CHV_GPIO_IDX_START_SE198;
309 port = CHV_IOSF_PORT_GPIO_SE0x48;
310 } else if (gpio_index >= CHV_GPIO_IDX_START_SW100) {
311 gpio_index -= CHV_GPIO_IDX_START_SW100;
312 port = CHV_IOSF_PORT_GPIO_SW0xb2;
313 } else if (gpio_index >= CHV_GPIO_IDX_START_E73) {
314 gpio_index -= CHV_GPIO_IDX_START_E73;
315 port = CHV_IOSF_PORT_GPIO_E0xa8;
316 } else {
317 port = CHV_IOSF_PORT_GPIO_N0x13;
318 }
319 } else {
320 /* XXX: The spec is unclear about CHV GPIO on seq v2 */
321 if (gpio_source != 0) {
322 drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "unknown gpio source %u\n"
, gpio_source)
323 "unknown gpio source %u\n", gpio_source)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "unknown gpio source %u\n"
, gpio_source);
324 return;
325 }
326
327 if (gpio_index >= CHV_GPIO_IDX_START_E73) {
328 drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "invalid gpio index %u for GPIO N\n"
, gpio_index)
329 "invalid gpio index %u for GPIO N\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "invalid gpio index %u for GPIO N\n"
, gpio_index)
330 gpio_index)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "invalid gpio index %u for GPIO N\n"
, gpio_index);
331 return;
332 }
333
334 port = CHV_IOSF_PORT_GPIO_N0x13;
335 }
336
337 family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY15;
338 gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY15;
339
340 cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index)(0x4400 + (family_num) * 0x400 + (gpio_index) * 8);
341 cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index)(0x4400 + (family_num) * 0x400 + (gpio_index) * 8 + 4);
342
343 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)(1UL << (VLV_IOSF_SB_GPIO)));
344 vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
345 vlv_iosf_sb_write(dev_priv, port, cfg0,
346 CHV_GPIO_GPIOEN(1 << 15) | CHV_GPIO_GPIOCFG_GPO(1 << 8) |
347 CHV_GPIO_GPIOTXSTATE(value)((!!(value)) << 1));
348 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)(1UL << (VLV_IOSF_SB_GPIO)));
349}
350
351static void bxt_exec_gpio(struct intel_connector *connector,
352 u8 gpio_source, u8 gpio_index, bool_Bool value)
353{
354 STUB()do { printf("%s: stub\n", __func__); } while(0);
355#ifdef __linux__
356 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(connector->base.dev);
357 /* XXX: this table is a quick ugly hack. */
358 static struct gpio_desc *bxt_gpio_table[U8_MAX0xff + 1];
359 struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
360
361 if (!gpio_desc) {
362 gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev,
363 NULL((void *)0), gpio_index,
364 value ? GPIOD_OUT_LOW :
365 GPIOD_OUT_HIGH0x0002);
366
367 if (IS_ERR_OR_NULL(gpio_desc)) {
368 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "GPIO index %u request failed (%ld)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , gpio_index
, PTR_ERR(gpio_desc))
369 "GPIO index %u request failed (%ld)\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "GPIO index %u request failed (%ld)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , gpio_index
, PTR_ERR(gpio_desc))
370 gpio_index, PTR_ERR(gpio_desc))printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "GPIO index %u request failed (%ld)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , gpio_index
, PTR_ERR(gpio_desc));
371 return;
372 }
373
374 bxt_gpio_table[gpio_index] = gpio_desc;
375 }
376
377 gpiod_set_value(gpio_desc, value);
378#endif
379}
380
381static void icl_exec_gpio(struct intel_connector *connector,
382 u8 gpio_source, u8 gpio_index, bool_Bool value)
383{
384 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(connector->base.dev);
385
386 drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Skipping ICL GPIO element execution\n"
);
387}
388
389enum {
390 MIPI_RESET_1 = 0,
391 MIPI_AVDD_EN_1,
392 MIPI_BKLT_EN_1,
393 MIPI_AVEE_EN_1,
394 MIPI_VIO_EN_1,
395 MIPI_RESET_2,
396 MIPI_AVDD_EN_2,
397 MIPI_BKLT_EN_2,
398 MIPI_AVEE_EN_2,
399 MIPI_VIO_EN_2,
400};
401
402static void icl_native_gpio_set_value(struct drm_i915_privateinteldrm_softc *dev_priv,
403 int gpio, bool_Bool value)
404{
405 int index;
406
407 if (drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 11 && gpio >= MIPI_RESET_2)({ int __ret = !!((((&(dev_priv)->__runtime)->display
.ip.ver) == 11 && gpio >= MIPI_RESET_2)); if (__ret
) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->
drm))->dev), "", "drm_WARN_ON(" "((&(dev_priv)->__runtime)->display.ip.ver) == 11 && gpio >= MIPI_RESET_2"
")"); __builtin_expect(!!(__ret), 0); }))
408 return;
409
410 switch (gpio) {
411 case MIPI_RESET_1:
412 case MIPI_RESET_2:
413 index = gpio == MIPI_RESET_1 ? HPD_PORT_A : HPD_PORT_B;
414
415 /*
416 * Disable HPD to set the pin to output, and set output
417 * value. The HPD pin should not be enabled for DSI anyway,
418 * assuming the board design and VBT are sane, and the pin isn't
419 * used by a non-DSI encoder.
420 *
421 * The locking protects against concurrent SHOTPLUG_CTL_DDI
422 * modifications in irq setup and handling.
423 */
424 spin_lock_irq(&dev_priv->irq_lock)mtx_enter(&dev_priv->irq_lock);
425 intel_de_rmw(dev_priv, SHOTPLUG_CTL_DDI((const i915_reg_t){ .reg = (0xc4030) }),
426 SHOTPLUG_CTL_DDI_HPD_ENABLE(index)(0x8 << (((index) - HPD_PORT_A) * 4)) |
427 SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index)(0x4 << (((index) - HPD_PORT_A) * 4)),
428 value ? SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index)(0x4 << (((index) - HPD_PORT_A) * 4)) : 0);
429 spin_unlock_irq(&dev_priv->irq_lock)mtx_leave(&dev_priv->irq_lock);
430 break;
431 case MIPI_AVDD_EN_1:
432 case MIPI_AVDD_EN_2:
433 index = gpio == MIPI_AVDD_EN_1 ? 0 : 1;
434
435 intel_de_rmw(dev_priv, PP_CONTROL(index)((const i915_reg_t){ .reg = (dev_priv->display.pps.mmio_base
- 0x61200 + (0x61204) + (index) * 0x100) }), PANEL_POWER_ON((u32)((1UL << (0)) + 0)),
436 value ? PANEL_POWER_ON((u32)((1UL << (0)) + 0)) : 0);
437 break;
438 case MIPI_BKLT_EN_1:
439 case MIPI_BKLT_EN_2:
440 index = gpio == MIPI_BKLT_EN_1 ? 0 : 1;
441
442 intel_de_rmw(dev_priv, PP_CONTROL(index)((const i915_reg_t){ .reg = (dev_priv->display.pps.mmio_base
- 0x61200 + (0x61204) + (index) * 0x100) }), EDP_BLC_ENABLE((u32)((1UL << (2)) + 0)),
443 value ? EDP_BLC_ENABLE((u32)((1UL << (2)) + 0)) : 0);
444 break;
445 case MIPI_AVEE_EN_1:
446 case MIPI_AVEE_EN_2:
447 index = gpio == MIPI_AVEE_EN_1 ? 1 : 2;
448
449 intel_de_rmw(dev_priv, GPIO(dev_priv, index)((const i915_reg_t){ .reg = (((dev_priv)->display.gmbus.mmio_base
) + 0x5010 + 4 * (index)) }),
450 GPIO_CLOCK_VAL_OUT(1 << 3),
451 GPIO_CLOCK_DIR_MASK(1 << 0) | GPIO_CLOCK_DIR_OUT(1 << 1) |
452 GPIO_CLOCK_VAL_MASK(1 << 2) | (value ? GPIO_CLOCK_VAL_OUT(1 << 3) : 0));
453 break;
454 case MIPI_VIO_EN_1:
455 case MIPI_VIO_EN_2:
456 index = gpio == MIPI_VIO_EN_1 ? 1 : 2;
457
458 intel_de_rmw(dev_priv, GPIO(dev_priv, index)((const i915_reg_t){ .reg = (((dev_priv)->display.gmbus.mmio_base
) + 0x5010 + 4 * (index)) }),
459 GPIO_DATA_VAL_OUT(1 << 11),
460 GPIO_DATA_DIR_MASK(1 << 8) | GPIO_DATA_DIR_OUT(1 << 9) |
461 GPIO_DATA_VAL_MASK(1 << 10) | (value ? GPIO_DATA_VAL_OUT(1 << 11) : 0));
462 break;
463 default:
464 MISSING_CASE(gpio)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "gpio", (long)(gpio)); __builtin_expect(!!(__ret), 0); });
465 }
466}
467
468static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
469{
470 struct drm_device *dev = intel_dsi->base.base.dev;
471 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
472 struct intel_connector *connector = intel_dsi->attached_connector;
473 u8 gpio_source, gpio_index = 0, gpio_number;
474 bool_Bool value;
475 bool_Bool native = DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 11;
476
477 if (connector->panel.vbt.dsi.seq_version >= 3)
478 gpio_index = *data++;
479
480 gpio_number = *data++;
481
482 /* gpio source in sequence v2 only */
483 if (connector->panel.vbt.dsi.seq_version == 2)
484 gpio_source = (*data >> 1) & 3;
485 else
486 gpio_source = 0;
487
488 if (connector->panel.vbt.dsi.seq_version >= 4 && *data & BIT(1)(1UL << (1)))
489 native = false0;
490
491 /* pull up/down */
492 value = *data++ & 1;
493
494 drm_dbg_kms(&dev_priv->drm, "GPIO index %u, number %u, source %u, native %s, set to %s\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "GPIO index %u, number %u, source %u, native %s, set to %s\n"
, gpio_index, gpio_number, gpio_source, str_yes_no(native), str_on_off
(value))
495 gpio_index, gpio_number, gpio_source, str_yes_no(native), str_on_off(value))__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "GPIO index %u, number %u, source %u, native %s, set to %s\n"
, gpio_index, gpio_number, gpio_source, str_yes_no(native), str_on_off
(value));
496
497 if (native)
498 icl_native_gpio_set_value(dev_priv, gpio_number, value);
499 else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 11)
500 icl_exec_gpio(connector, gpio_source, gpio_index, value);
501 else if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW))
502 vlv_exec_gpio(connector, gpio_source, gpio_number, value);
503 else if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW))
504 chv_exec_gpio(connector, gpio_source, gpio_number, value);
505 else
506 bxt_exec_gpio(connector, gpio_source, gpio_index, value);
507
508 return data;
509}
510
511#if defined(CONFIG_ACPI1) && defined(__linux__)
512static int i2c_adapter_lookup(struct acpi_resource *ares, void *data)
513{
514 struct i2c_adapter_lookup *lookup = data;
515 struct intel_dsi *intel_dsi = lookup->intel_dsi;
516 struct acpi_resource_i2c_serialbus *sb;
517 struct i2c_adapter *adapter;
518 acpi_handle adapter_handle;
519 acpi_status status;
520
521 if (!i2c_acpi_get_i2c_resource(ares, &sb))
522 return 1;
523
524 if (lookup->slave_addr != sb->slave_address)
525 return 1;
526
527 status = acpi_get_handle(lookup->dev_handle,
528 sb->resource_source.string_ptr,
529 &adapter_handle);
530 if (ACPI_FAILURE(status)((status) != 0))
531 return 1;
532
533 adapter = i2c_acpi_find_adapter_by_handle(adapter_handle);
534 if (adapter)
535 intel_dsi->i2c_bus_num = adapter->nr;
536
537 return 1;
538}
539
540static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
541 const u16 slave_addr)
542{
543 struct drm_device *drm_dev = intel_dsi->base.base.dev;
544 struct acpi_device *adev = ACPI_COMPANION(drm_dev->dev);
545 struct i2c_adapter_lookup lookup = {
546 .slave_addr = slave_addr,
547 .intel_dsi = intel_dsi,
548 .dev_handle = acpi_device_handle(adev),
549 };
550 LIST_HEAD(resource_list);
551
552 acpi_dev_get_resources(adev, &resource_list, i2c_adapter_lookup, &lookup);
553 acpi_dev_free_resource_list(&resource_list);
554}
555#else
556static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
557 const u16 slave_addr)
558{
559}
560#endif
561
562static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
563{
564 STUB()do { printf("%s: stub\n", __func__); } while(0);
565 return NULL((void *)0);
566#ifdef notyet
567 struct drm_i915_privateinteldrm_softc *i915 = to_i915(intel_dsi->base.base.dev);
568 struct i2c_adapter *adapter;
569 struct i2c_msg msg;
570 int ret;
571 u8 vbt_i2c_bus_num = *(data + 2);
572 u16 slave_addr = *(u16 *)(data + 3);
573 u8 reg_offset = *(data + 5);
574 u8 payload_size = *(data + 6);
575 u8 *payload_data;
576
577 if (intel_dsi->i2c_bus_num < 0) {
578 intel_dsi->i2c_bus_num = vbt_i2c_bus_num;
579 i2c_acpi_find_adapter(intel_dsi, slave_addr);
580 }
581
582 adapter = i2c_get_adapter(intel_dsi->i2c_bus_num);
583 if (!adapter) {
584 drm_err(&i915->drm, "Cannot find a valid i2c bus for xfer\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Cannot find a valid i2c bus for xfer\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
585 goto err_bus;
586 }
587
588 payload_data = kzalloc(payload_size + 1, GFP_KERNEL(0x0001 | 0x0004));
589 if (!payload_data)
590 goto err_alloc;
591
592 payload_data[0] = reg_offset;
593 memcpy(&payload_data[1], (data + 7), payload_size)__builtin_memcpy((&payload_data[1]), ((data + 7)), (payload_size
));
594
595 msg.addr = slave_addr;
596 msg.flags = 0;
597 msg.len = payload_size + 1;
598 msg.buf = payload_data;
599
600 ret = i2c_transfer(adapter, &msg, 1);
601 if (ret < 0)
602 drm_err(&i915->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to xfer payload of size (%u) to reg (%u)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , payload_size
, reg_offset)
603 "Failed to xfer payload of size (%u) to reg (%u)\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to xfer payload of size (%u) to reg (%u)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , payload_size
, reg_offset)
604 payload_size, reg_offset)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to xfer payload of size (%u) to reg (%u)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , payload_size
, reg_offset);
605
606 kfree(payload_data);
607err_alloc:
608 i2c_put_adapter(adapter);
609err_bus:
610 return data + payload_size + 7;
611#endif
612}
613
614static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data)
615{
616 struct drm_i915_privateinteldrm_softc *i915 = to_i915(intel_dsi->base.base.dev);
617
618 drm_dbg_kms(&i915->drm, "Skipping SPI element execution\n")__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Skipping SPI element execution\n"
);
619
620 return data + *(data + 5) + 6;
621}
622
623static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data)
624{
625 struct drm_i915_privateinteldrm_softc *i915 = to_i915(intel_dsi->base.base.dev);
Value stored to 'i915' during its initialization is never read
626#ifdef CONFIG_PMIC_OPREGION
627 u32 value, mask, reg_address;
628 u16 i2c_address;
629 int ret;
630
631 /* byte 0 aka PMIC Flag is reserved */
632 i2c_address = get_unaligned_le16(data + 1);
633 reg_address = get_unaligned_le32(data + 3)((__uint32_t)(*(__uint32_t *)(data + 3)));
634 value = get_unaligned_le32(data + 7)((__uint32_t)(*(__uint32_t *)(data + 7)));
635 mask = get_unaligned_le32(data + 11)((__uint32_t)(*(__uint32_t *)(data + 11)));
636
637 ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address,
638 reg_address,
639 value, mask);
640 if (ret)
641 drm_err(&i915->drm, "%s failed, error: %d\n", __func__, ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s failed, error: %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__
, ret);
642#else
643 drm_err(&i915->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
644 "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
645#endif
646
647 return data + 15;
648}
649
650typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
651 const u8 *data);
652static const fn_mipi_elem_exec exec_elem[] = {
653 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
654 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
655 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
656 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
657 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi,
658 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic,
659};
660
661/*
662 * MIPI Sequence from VBT #53 parsing logic
663 * We have already separated each seqence during bios parsing
664 * Following is generic execution function for any sequence
665 */
666
667static const char * const seq_name[] = {
668 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
669 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
670 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
671 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF",
672 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
673 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON",
674 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF",
675 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON",
676 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF",
677 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON",
678 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF",
679};
680
681static const char *sequence_name(enum mipi_seq seq_id)
682{
683 if (seq_id < ARRAY_SIZE(seq_name)(sizeof((seq_name)) / sizeof((seq_name)[0])) && seq_name[seq_id])
684 return seq_name[seq_id];
685 else
686 return "(unknown)";
687}
688
689static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi,
690 enum mipi_seq seq_id)
691{
692 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(intel_dsi->base.base.dev);
693 struct intel_connector *connector = intel_dsi->attached_connector;
694 const u8 *data;
695 fn_mipi_elem_exec mipi_elem_exec;
696
697 if (drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((seq_id >= (sizeof((connector->panel.
vbt.dsi.sequence)) / sizeof((connector->panel.vbt.dsi.sequence
)[0])))); if (__ret) printf("%s %s: " "%s", dev_driver_string
(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "seq_id >= (sizeof((connector->panel.vbt.dsi.sequence)) / sizeof((connector->panel.vbt.dsi.sequence)[0]))"
")"); __builtin_expect(!!(__ret), 0); })
698 seq_id >= ARRAY_SIZE(connector->panel.vbt.dsi.sequence))({ int __ret = !!((seq_id >= (sizeof((connector->panel.
vbt.dsi.sequence)) / sizeof((connector->panel.vbt.dsi.sequence
)[0])))); if (__ret) printf("%s %s: " "%s", dev_driver_string
(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "seq_id >= (sizeof((connector->panel.vbt.dsi.sequence)) / sizeof((connector->panel.vbt.dsi.sequence)[0]))"
")"); __builtin_expect(!!(__ret), 0); }))
699 return;
700
701 data = connector->panel.vbt.dsi.sequence[seq_id];
702 if (!data)
703 return;
704
705 drm_WARN_ON(&dev_priv->drm, *data != seq_id)({ int __ret = !!((*data != seq_id)); if (__ret) printf("%s %s: "
"%s", dev_driver_string(((&dev_priv->drm))->dev), ""
, "drm_WARN_ON(" "*data != seq_id" ")"); __builtin_expect(!!(
__ret), 0); });
706
707 drm_dbg_kms(&dev_priv->drm, "Starting MIPI sequence %d - %s\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Starting MIPI sequence %d - %s\n"
, seq_id, sequence_name(seq_id))
708 seq_id, sequence_name(seq_id))__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Starting MIPI sequence %d - %s\n"
, seq_id, sequence_name(seq_id));
709
710 /* Skip Sequence Byte. */
711 data++;
712
713 /* Skip Size of Sequence. */
714 if (connector->panel.vbt.dsi.seq_version >= 3)
715 data += 4;
716
717 while (1) {
718 u8 operation_byte = *data++;
719 u8 operation_size = 0;
720
721 if (operation_byte == MIPI_SEQ_ELEM_END)
722 break;
723
724 if (operation_byte < ARRAY_SIZE(exec_elem)(sizeof((exec_elem)) / sizeof((exec_elem)[0])))
725 mipi_elem_exec = exec_elem[operation_byte];
726 else
727 mipi_elem_exec = NULL((void *)0);
728
729 /* Size of Operation. */
730 if (connector->panel.vbt.dsi.seq_version >= 3)
731 operation_size = *data++;
732
733 if (mipi_elem_exec) {
734 const u8 *next = data + operation_size;
735
736 data = mipi_elem_exec(intel_dsi, data);
737
738 /* Consistency check if we have size. */
739 if (operation_size && data != next) {
740 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Inconsistent operation size\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
741 "Inconsistent operation size\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Inconsistent operation size\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
742 return;
743 }
744 } else if (operation_size) {
745 /* We have size, skip. */
746 drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Unsupported MIPI operation byte %u\n"
, operation_byte)
747 "Unsupported MIPI operation byte %u\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Unsupported MIPI operation byte %u\n"
, operation_byte)
748 operation_byte)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Unsupported MIPI operation byte %u\n"
, operation_byte);
749 data += operation_size;
750 } else {
751 /* No size, can't skip without parsing. */
752 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Unsupported MIPI operation byte %u\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , operation_byte
)
753 "Unsupported MIPI operation byte %u\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Unsupported MIPI operation byte %u\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , operation_byte
)
754 operation_byte)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Unsupported MIPI operation byte %u\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , operation_byte
);
755 return;
756 }
757 }
758}
759
760void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
761 enum mipi_seq seq_id)
762{
763 STUB()do { printf("%s: stub\n", __func__); } while(0);
764#ifdef notyet
765 if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel)
766 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
767 if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight)
768 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1);
769
770 intel_dsi_vbt_exec(intel_dsi, seq_id);
771
772 if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel)
773 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
774 if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight)
775 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0);
776#endif
777}
778
779void intel_dsi_log_params(struct intel_dsi *intel_dsi)
780{
781 struct drm_i915_privateinteldrm_softc *i915 = to_i915(intel_dsi->base.base.dev);
782
783 drm_dbg_kms(&i915->drm, "Pclk %d\n", intel_dsi->pclk)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Pclk %d\n", intel_dsi
->pclk);
784 drm_dbg_kms(&i915->drm, "Pixel overlap %d\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Pixel overlap %d\n",
intel_dsi->pixel_overlap)
785 intel_dsi->pixel_overlap)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Pixel overlap %d\n",
intel_dsi->pixel_overlap);
786 drm_dbg_kms(&i915->drm, "Lane count %d\n", intel_dsi->lane_count)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Lane count %d\n", intel_dsi
->lane_count);
787 drm_dbg_kms(&i915->drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "DPHY param reg 0x%x\n"
, intel_dsi->dphy_reg);
788 drm_dbg_kms(&i915->drm, "Video mode format %s\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Video mode format %s\n"
, intel_dsi->video_mode == 0x1 ? "non-burst with sync pulse"
: intel_dsi->video_mode == 0x2 ? "non-burst with sync events"
: intel_dsi->video_mode == 0x3 ? "burst" : "<unknown>"
)
789 intel_dsi->video_mode == NON_BURST_SYNC_PULSE ?__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Video mode format %s\n"
, intel_dsi->video_mode == 0x1 ? "non-burst with sync pulse"
: intel_dsi->video_mode == 0x2 ? "non-burst with sync events"
: intel_dsi->video_mode == 0x3 ? "burst" : "<unknown>"
)
790 "non-burst with sync pulse" :__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Video mode format %s\n"
, intel_dsi->video_mode == 0x1 ? "non-burst with sync pulse"
: intel_dsi->video_mode == 0x2 ? "non-burst with sync events"
: intel_dsi->video_mode == 0x3 ? "burst" : "<unknown>"
)
791 intel_dsi->video_mode == NON_BURST_SYNC_EVENTS ?__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Video mode format %s\n"
, intel_dsi->video_mode == 0x1 ? "non-burst with sync pulse"
: intel_dsi->video_mode == 0x2 ? "non-burst with sync events"
: intel_dsi->video_mode == 0x3 ? "burst" : "<unknown>"
)
792 "non-burst with sync events" :__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Video mode format %s\n"
, intel_dsi->video_mode == 0x1 ? "non-burst with sync pulse"
: intel_dsi->video_mode == 0x2 ? "non-burst with sync events"
: intel_dsi->video_mode == 0x3 ? "burst" : "<unknown>"
)
793 intel_dsi->video_mode == BURST_MODE ?__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Video mode format %s\n"
, intel_dsi->video_mode == 0x1 ? "non-burst with sync pulse"
: intel_dsi->video_mode == 0x2 ? "non-burst with sync events"
: intel_dsi->video_mode == 0x3 ? "burst" : "<unknown>"
)
794 "burst" : "<unknown>")__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Video mode format %s\n"
, intel_dsi->video_mode == 0x1 ? "non-burst with sync pulse"
: intel_dsi->video_mode == 0x2 ? "non-burst with sync events"
: intel_dsi->video_mode == 0x3 ? "burst" : "<unknown>"
);
795 drm_dbg_kms(&i915->drm, "Burst mode ratio %d\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Burst mode ratio %d\n"
, intel_dsi->burst_mode_ratio)
796 intel_dsi->burst_mode_ratio)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Burst mode ratio %d\n"
, intel_dsi->burst_mode_ratio);
797 drm_dbg_kms(&i915->drm, "Reset timer %d\n", intel_dsi->rst_timer_val)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Reset timer %d\n", intel_dsi
->rst_timer_val);
798 drm_dbg_kms(&i915->drm, "Eot %s\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Eot %s\n", str_enabled_disabled
(intel_dsi->eotp_pkt))
799 str_enabled_disabled(intel_dsi->eotp_pkt))__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Eot %s\n", str_enabled_disabled
(intel_dsi->eotp_pkt));
800 drm_dbg_kms(&i915->drm, "Clockstop %s\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Clockstop %s\n", str_enabled_disabled
(!intel_dsi->clock_stop))
801 str_enabled_disabled(!intel_dsi->clock_stop))__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Clockstop %s\n", str_enabled_disabled
(!intel_dsi->clock_stop));
802 drm_dbg_kms(&i915->drm, "Mode %s\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Mode %s\n", intel_dsi
->operation_mode ? "command" : "video")
803 intel_dsi->operation_mode ? "command" : "video")__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Mode %s\n", intel_dsi
->operation_mode ? "command" : "video");
804 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK1)
805 drm_dbg_kms(&i915->drm,__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Dual link: DSI_DUAL_LINK_FRONT_BACK\n"
)
806 "Dual link: DSI_DUAL_LINK_FRONT_BACK\n")__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Dual link: DSI_DUAL_LINK_FRONT_BACK\n"
);
807 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT2)
808 drm_dbg_kms(&i915->drm,__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"
)
809 "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n")__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"
);
810 else
811 drm_dbg_kms(&i915->drm, "Dual link: NONE\n")__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Dual link: NONE\n");
812 drm_dbg_kms(&i915->drm, "Pixel Format %d\n", intel_dsi->pixel_format)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Pixel Format %d\n", intel_dsi
->pixel_format);
813 drm_dbg_kms(&i915->drm, "TLPX %d\n", intel_dsi->escape_clk_div)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "TLPX %d\n", intel_dsi
->escape_clk_div);
814 drm_dbg_kms(&i915->drm, "LP RX Timeout 0x%x\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "LP RX Timeout 0x%x\n"
, intel_dsi->lp_rx_timeout)
815 intel_dsi->lp_rx_timeout)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "LP RX Timeout 0x%x\n"
, intel_dsi->lp_rx_timeout);
816 drm_dbg_kms(&i915->drm, "Turnaround Timeout 0x%x\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Turnaround Timeout 0x%x\n"
, intel_dsi->turn_arnd_val)
817 intel_dsi->turn_arnd_val)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Turnaround Timeout 0x%x\n"
, intel_dsi->turn_arnd_val);
818 drm_dbg_kms(&i915->drm, "Init Count 0x%x\n", intel_dsi->init_count)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "Init Count 0x%x\n", intel_dsi
->init_count);
819 drm_dbg_kms(&i915->drm, "HS to LP Count 0x%x\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "HS to LP Count 0x%x\n"
, intel_dsi->hs_to_lp_count)
820 intel_dsi->hs_to_lp_count)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "HS to LP Count 0x%x\n"
, intel_dsi->hs_to_lp_count);
821 drm_dbg_kms(&i915->drm, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "LP Byte Clock %d\n",
intel_dsi->lp_byte_clk);
822 drm_dbg_kms(&i915->drm, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "DBI BW Timer 0x%x\n"
, intel_dsi->bw_timer);
823 drm_dbg_kms(&i915->drm, "LP to HS Clock Count 0x%x\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "LP to HS Clock Count 0x%x\n"
, intel_dsi->clk_lp_to_hs_count)
824 intel_dsi->clk_lp_to_hs_count)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "LP to HS Clock Count 0x%x\n"
, intel_dsi->clk_lp_to_hs_count);
825 drm_dbg_kms(&i915->drm, "HS to LP Clock Count 0x%x\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "HS to LP Clock Count 0x%x\n"
, intel_dsi->clk_hs_to_lp_count)
826 intel_dsi->clk_hs_to_lp_count)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "HS to LP Clock Count 0x%x\n"
, intel_dsi->clk_hs_to_lp_count);
827 drm_dbg_kms(&i915->drm, "BTA %s\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "BTA %s\n", str_enabled_disabled
(!(intel_dsi->video_frmt_cfg_bits & (1 << 3))))
828 str_enabled_disabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)))__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "BTA %s\n", str_enabled_disabled
(!(intel_dsi->video_frmt_cfg_bits & (1 << 3))));
829}
830
831bool_Bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
832{
833 struct drm_device *dev = intel_dsi->base.base.dev;
834 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
835 struct intel_connector *connector = intel_dsi->attached_connector;
836 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
837 struct mipi_pps_data *pps = connector->panel.vbt.dsi.pps;
838 struct drm_display_mode *mode = connector->panel.vbt.lfp_lvds_vbt_mode;
839 u16 burst_mode_ratio;
840 enum port port;
841
842 drm_dbg_kms(&dev_priv->drm, "\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "\n");
843
844 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
845 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
846 intel_dsi->lane_count = mipi_config->lane_cnt + 1;
847 intel_dsi->pixel_format =
848 pixel_format_from_register_bits(
849 mipi_config->videomode_color_format << 7);
850
851 intel_dsi->dual_link = mipi_config->dual_link;
852 intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
853 intel_dsi->operation_mode = mipi_config->is_cmd_mode;
854 intel_dsi->video_mode = mipi_config->video_transfer_mode;
855 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
856 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
857 intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout;
858 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
859 intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
860 intel_dsi->init_count = mipi_config->master_init_timer;
861 intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
862 intel_dsi->video_frmt_cfg_bits =
863 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA(1 << 3) : 0;
864 intel_dsi->bgr_enabled = mipi_config->rgb_flip;
865
866 /* Starting point, adjusted depending on dual link and burst mode */
867 intel_dsi->pclk = mode->clock;
868
869 /* In dual link mode each port needs half of pixel clock */
870 if (intel_dsi->dual_link) {
871 intel_dsi->pclk /= 2;
872
873 /* we can enable pixel_overlap if needed by panel. In this
874 * case we need to increase the pixelclock for extra pixels
875 */
876 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK1) {
877 intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000)(((mode->vtotal * intel_dsi->pixel_overlap * 60) + ((1000
) - 1)) / (1000));
878 }
879 }
880
881 /* Burst Mode Ratio
882 * Target ddr frequency from VBT / non burst ddr freq
883 * multiply by 100 to preserve remainder
884 */
885 if (intel_dsi->video_mode == BURST_MODE0x3) {
886 if (mipi_config->target_burst_mode_freq) {
887 u32 bitrate = intel_dsi_bitrate(intel_dsi);
888
889 /*
890 * Sometimes the VBT contains a slightly lower clock,
891 * then the bitrate we have calculated, in this case
892 * just replace it with the calculated bitrate.
893 */
894 if (mipi_config->target_burst_mode_freq < bitrate &&
895 intel_fuzzy_clock_check(
896 mipi_config->target_burst_mode_freq,
897 bitrate))
898 mipi_config->target_burst_mode_freq = bitrate;
899
900 if (mipi_config->target_burst_mode_freq < bitrate) {
901 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Burst mode freq is less than computed\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
902 "Burst mode freq is less than computed\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Burst mode freq is less than computed\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
903 return false0;
904 }
905
906 burst_mode_ratio = DIV_ROUND_UP((((mipi_config->target_burst_mode_freq * 100) + ((bitrate)
- 1)) / (bitrate))
907 mipi_config->target_burst_mode_freq * 100,(((mipi_config->target_burst_mode_freq * 100) + ((bitrate)
- 1)) / (bitrate))
908 bitrate)(((mipi_config->target_burst_mode_freq * 100) + ((bitrate)
- 1)) / (bitrate));
909
910 intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100)(((intel_dsi->pclk * burst_mode_ratio) + ((100) - 1)) / (100
));
911 } else {
912 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Burst mode target is not set\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
913 "Burst mode target is not set\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Burst mode target is not set\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
914 return false0;
915 }
916 } else
917 burst_mode_ratio = 100;
918
919 intel_dsi->burst_mode_ratio = burst_mode_ratio;
920
921 /* delays in VBT are in unit of 100us, so need to convert
922 * here in ms
923 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
924 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
925 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
926 intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
927 intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
928 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
929
930 intel_dsi->i2c_bus_num = -1;
931
932 /* a regular driver would get the device in probe */
933 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
934 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
935 }
936
937 return true1;
938}
939
940#ifdef notyet
941
942/*
943 * On some BYT/CHT devs some sequences are incomplete and we need to manually
944 * control some GPIOs. We need to add a GPIO lookup table before we get these.
945 * If the GOP did not initialize the panel (HDMI inserted) we may need to also
946 * change the pinmux for the SoC's PWM0 pin from GPIO to PWM.
947 */
948static struct gpiod_lookup_table pmic_panel_gpio_table = {
949 /* Intel GFX is consumer */
950 .dev_id = "0000:00:02.0",
951 .table = {
952 /* Panel EN/DISABLE */
953 GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH),
954 { }
955 },
956};
957
958static struct gpiod_lookup_table soc_panel_gpio_table = {
959 .dev_id = "0000:00:02.0",
960 .table = {
961 GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH),
962 GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH),
963 { }
964 },
965};
966
967static const struct pinctrl_map soc_pwm_pinctrl_map[] = {
968 PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00",
969 "pwm0_grp", "pwm"),
970};
971
972#endif /* notyet */
973
974void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool_Bool panel_is_on)
975{
976 STUB()do { printf("%s: stub\n", __func__); } while(0);
977#ifdef notyet
978 struct drm_device *dev = intel_dsi->base.base.dev;
979 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
980 struct intel_connector *connector = intel_dsi->attached_connector;
981 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
982 enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH0x0002 : GPIOD_OUT_LOW;
983 bool_Bool want_backlight_gpio = false0;
984 bool_Bool want_panel_gpio = false0;
985 struct pinctrl *pinctrl;
986 int ret;
987
988 if ((IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) &&
989 mipi_config->pwm_blc == PPS_BLC_PMIC0) {
990 gpiod_add_lookup_table(&pmic_panel_gpio_table);
991 want_panel_gpio = true1;
992 }
993
994 if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) && mipi_config->pwm_blc == PPS_BLC_SOC1) {
995 gpiod_add_lookup_table(&soc_panel_gpio_table);
996 want_panel_gpio = true1;
997 want_backlight_gpio = true1;
998
999 /* Ensure PWM0 pin is muxed as PWM instead of GPIO */
1000 ret = pinctrl_register_mappings(soc_pwm_pinctrl_map,
1001 ARRAY_SIZE(soc_pwm_pinctrl_map)(sizeof((soc_pwm_pinctrl_map)) / sizeof((soc_pwm_pinctrl_map)
[0])));
1002 if (ret)
1003 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to register pwm0 pinmux mapping\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
1004 "Failed to register pwm0 pinmux mapping\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to register pwm0 pinmux mapping\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
1005
1006 pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0");
1007 if (IS_ERR(pinctrl))
1008 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to set pinmux to PWM\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
1009 "Failed to set pinmux to PWM\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to set pinmux to PWM\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
1010 }
1011
1012 if (want_panel_gpio) {
1013 intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags);
1014 if (IS_ERR(intel_dsi->gpio_panel)) {
1015 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to own gpio for panel control\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
1016 "Failed to own gpio for panel control\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to own gpio for panel control\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
1017 intel_dsi->gpio_panel = NULL((void *)0);
1018 }
1019 }
1020
1021 if (want_backlight_gpio) {
1022 intel_dsi->gpio_backlight =
1023 gpiod_get(dev->dev, "backlight", flags);
1024 if (IS_ERR(intel_dsi->gpio_backlight)) {
1025 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to own gpio for backlight control\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
1026 "Failed to own gpio for backlight control\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to own gpio for backlight control\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
1027 intel_dsi->gpio_backlight = NULL((void *)0);
1028 }
1029 }
1030#endif
1031}
1032
1033void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi)
1034{
1035 STUB()do { printf("%s: stub\n", __func__); } while(0);
1036#ifdef notyet
1037 struct drm_device *dev = intel_dsi->base.base.dev;
1038 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
1039 struct intel_connector *connector = intel_dsi->attached_connector;
1040 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
1041
1042 if (intel_dsi->gpio_panel) {
1043 gpiod_put(intel_dsi->gpio_panel);
1044 intel_dsi->gpio_panel = NULL((void *)0);
1045 }
1046
1047 if (intel_dsi->gpio_backlight) {
1048 gpiod_put(intel_dsi->gpio_backlight);
1049 intel_dsi->gpio_backlight = NULL((void *)0);
1050 }
1051
1052 if ((IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) &&
1053 mipi_config->pwm_blc == PPS_BLC_PMIC0)
1054 gpiod_remove_lookup_table(&pmic_panel_gpio_table);
1055
1056 if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) && mipi_config->pwm_blc == PPS_BLC_SOC1) {
1057 pinctrl_unregister_mappings(soc_pwm_pinctrl_map);
1058 gpiod_remove_lookup_table(&soc_panel_gpio_table);
1059 }
1060#endif
1061}