Bug Summary

File:dev/pci/drm/i915/display/intel_display_power_well.c
Warning:line 325, column 2
The result of the left shift is undefined due to shifting by '40', which is greater or equal to the width of type 'int'

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name intel_display_power_well.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/i915/display/intel_display_power_well.c
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2022 Intel Corporation
4 */
5
6#include "i915_drv.h"
7#include "i915_irq.h"
8#include "intel_backlight_regs.h"
9#include "intel_combo_phy.h"
10#include "intel_combo_phy_regs.h"
11#include "intel_crt.h"
12#include "intel_de.h"
13#include "intel_display_power_well.h"
14#include "intel_display_types.h"
15#include "intel_dkl_phy.h"
16#include "intel_dmc.h"
17#include "intel_dpio_phy.h"
18#include "intel_dpll.h"
19#include "intel_hotplug.h"
20#include "intel_pcode.h"
21#include "intel_pps.h"
22#include "intel_tc.h"
23#include "intel_vga.h"
24#include "skl_watermark.h"
25#include "vlv_sideband.h"
26#include "vlv_sideband_reg.h"
27
28struct i915_power_well_regs {
29 i915_reg_t bios;
30 i915_reg_t driver;
31 i915_reg_t kvmr;
32 i915_reg_t debug;
33};
34
35struct i915_power_well_ops {
36 const struct i915_power_well_regs *regs;
37 /*
38 * Synchronize the well's hw state to match the current sw state, for
39 * example enable/disable it based on the current refcount. Called
40 * during driver init and resume time, possibly after first calling
41 * the enable/disable handlers.
42 */
43 void (*sync_hw)(struct drm_i915_privateinteldrm_softc *i915,
44 struct i915_power_well *power_well);
45 /*
46 * Enable the well and resources that depend on it (for example
47 * interrupts located on the well). Called after the 0->1 refcount
48 * transition.
49 */
50 void (*enable)(struct drm_i915_privateinteldrm_softc *i915,
51 struct i915_power_well *power_well);
52 /*
53 * Disable the well and resources that depend on it. Called after
54 * the 1->0 refcount transition.
55 */
56 void (*disable)(struct drm_i915_privateinteldrm_softc *i915,
57 struct i915_power_well *power_well);
58 /* Returns the hw enabled state. */
59 bool_Bool (*is_enabled)(struct drm_i915_privateinteldrm_softc *i915,
60 struct i915_power_well *power_well);
61};
62
63static const struct i915_power_well_instance *
64i915_power_well_instance(const struct i915_power_well *power_well)
65{
66 return &power_well->desc->instances->list[power_well->instance_idx];
67}
68
69struct i915_power_well *
70lookup_power_well(struct drm_i915_privateinteldrm_softc *i915,
71 enum i915_power_well_id power_well_id)
72{
73 struct i915_power_well *power_well;
74
75 for_each_power_well(i915, power_well)for ((power_well) = (i915)->display.power.domains.power_wells
; (power_well) - (i915)->display.power.domains.power_wells
< (i915)->display.power.domains.power_well_count; (power_well
)++)
76 if (i915_power_well_instance(power_well)->id == power_well_id)
77 return power_well;
78
79 /*
80 * It's not feasible to add error checking code to the callers since
81 * this condition really shouldn't happen and it doesn't even make sense
82 * to abort things like display initialization sequences. Just return
83 * the first power well and hope the WARN gets reported so we can fix
84 * our driver.
85 */
86 drm_WARN(&i915->drm, 1,({ int __ret = !!(1); if (__ret) printf("%s %s: " "Power well %d not defined for this platform\n"
, dev_driver_string((&i915->drm)->dev), "", power_well_id
); __builtin_expect(!!(__ret), 0); })
87 "Power well %d not defined for this platform\n",({ int __ret = !!(1); if (__ret) printf("%s %s: " "Power well %d not defined for this platform\n"
, dev_driver_string((&i915->drm)->dev), "", power_well_id
); __builtin_expect(!!(__ret), 0); })
88 power_well_id)({ int __ret = !!(1); if (__ret) printf("%s %s: " "Power well %d not defined for this platform\n"
, dev_driver_string((&i915->drm)->dev), "", power_well_id
); __builtin_expect(!!(__ret), 0); });
89 return &i915->display.power.domains.power_wells[0];
90}
91
92void intel_power_well_enable(struct drm_i915_privateinteldrm_softc *i915,
93 struct i915_power_well *power_well)
94{
95 drm_dbg_kms(&i915->drm, "enabling %s\n", intel_power_well_name(power_well))__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "enabling %s\n", intel_power_well_name
(power_well));
96 power_well->desc->ops->enable(i915, power_well);
97 power_well->hw_enabled = true1;
98}
99
100void intel_power_well_disable(struct drm_i915_privateinteldrm_softc *i915,
101 struct i915_power_well *power_well)
102{
103 drm_dbg_kms(&i915->drm, "disabling %s\n", intel_power_well_name(power_well))__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "disabling %s\n", intel_power_well_name
(power_well));
104 power_well->hw_enabled = false0;
105 power_well->desc->ops->disable(i915, power_well);
106}
107
108void intel_power_well_sync_hw(struct drm_i915_privateinteldrm_softc *i915,
109 struct i915_power_well *power_well)
110{
111 power_well->desc->ops->sync_hw(i915, power_well);
112 power_well->hw_enabled =
113 power_well->desc->ops->is_enabled(i915, power_well);
114}
115
116void intel_power_well_get(struct drm_i915_privateinteldrm_softc *i915,
117 struct i915_power_well *power_well)
118{
119 if (!power_well->count++)
120 intel_power_well_enable(i915, power_well);
121}
122
123void intel_power_well_put(struct drm_i915_privateinteldrm_softc *i915,
124 struct i915_power_well *power_well)
125{
126 drm_WARN(&i915->drm, !power_well->count,({ int __ret = !!(!power_well->count); if (__ret) printf("%s %s: "
"Use count on power well %s is already zero", dev_driver_string
((&i915->drm)->dev), "", i915_power_well_instance(power_well
)->name); __builtin_expect(!!(__ret), 0); })
127 "Use count on power well %s is already zero",({ int __ret = !!(!power_well->count); if (__ret) printf("%s %s: "
"Use count on power well %s is already zero", dev_driver_string
((&i915->drm)->dev), "", i915_power_well_instance(power_well
)->name); __builtin_expect(!!(__ret), 0); })
128 i915_power_well_instance(power_well)->name)({ int __ret = !!(!power_well->count); if (__ret) printf("%s %s: "
"Use count on power well %s is already zero", dev_driver_string
((&i915->drm)->dev), "", i915_power_well_instance(power_well
)->name); __builtin_expect(!!(__ret), 0); });
129
130 if (!--power_well->count)
131 intel_power_well_disable(i915, power_well);
132}
133
134bool_Bool intel_power_well_is_enabled(struct drm_i915_privateinteldrm_softc *i915,
135 struct i915_power_well *power_well)
136{
137 return power_well->desc->ops->is_enabled(i915, power_well);
138}
139
140bool_Bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well)
141{
142 return power_well->hw_enabled;
143}
144
145bool_Bool intel_display_power_well_is_enabled(struct drm_i915_privateinteldrm_softc *dev_priv,
146 enum i915_power_well_id power_well_id)
147{
148 struct i915_power_well *power_well;
149
150 power_well = lookup_power_well(dev_priv, power_well_id);
151
152 return intel_power_well_is_enabled(dev_priv, power_well);
153}
154
155bool_Bool intel_power_well_is_always_on(struct i915_power_well *power_well)
156{
157 return power_well->desc->always_on;
158}
159
160const char *intel_power_well_name(struct i915_power_well *power_well)
161{
162 return i915_power_well_instance(power_well)->name;
163}
164
165struct intel_power_domain_mask *intel_power_well_domains(struct i915_power_well *power_well)
166{
167 return &power_well->domains;
168}
169
170int intel_power_well_refcount(struct i915_power_well *power_well)
171{
172 return power_well->count;
173}
174
175/*
176 * Starting with Haswell, we have a "Power Down Well" that can be turned off
177 * when not needed anymore. We have 4 registers that can request the power well
178 * to be enabled, and it will only be disabled if none of the registers is
179 * requesting it to be enabled.
180 */
181static void hsw_power_well_post_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
182 u8 irq_pipe_mask, bool_Bool has_vga)
183{
184 if (has_vga)
185 intel_vga_reset_io_mem(dev_priv);
186
187 if (irq_pipe_mask)
188 gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
189}
190
191static void hsw_power_well_pre_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
192 u8 irq_pipe_mask)
193{
194 if (irq_pipe_mask)
195 gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
196}
197
198#define ICL_AUX_PW_TO_CH(pw_idx)((pw_idx) - 0 + AUX_CH_A) \
199 ((pw_idx) - ICL_PW_CTL_IDX_AUX_A0 + AUX_CH_A)
200
201#define ICL_TBT_AUX_PW_TO_CH(pw_idx)((pw_idx) - 8 + AUX_CH_C) \
202 ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT18 + AUX_CH_C)
203
204static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well *power_well)
205{
206 int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
207
208 return power_well->desc->is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx)((pw_idx) - 8 + AUX_CH_C) :
209 ICL_AUX_PW_TO_CH(pw_idx)((pw_idx) - 0 + AUX_CH_A);
210}
211
212static struct intel_digital_port *
213aux_ch_to_digital_port(struct drm_i915_privateinteldrm_softc *dev_priv,
214 enum aux_ch aux_ch)
215{
216 struct intel_digital_port *dig_port = NULL((void *)0);
217 struct intel_encoder *encoder;
218
219 for_each_intel_encoder(&dev_priv->drm, encoder)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)->
base.head ) *__mptr = ((&(&dev_priv->drm)->mode_config
.encoder_list)->next); (__typeof(*encoder) *)( (char *)__mptr
- __builtin_offsetof(__typeof(*encoder), base.head) );}); &
encoder->base.head != (&(&dev_priv->drm)->mode_config
.encoder_list); encoder = ({ const __typeof( ((__typeof(*encoder
) *)0)->base.head ) *__mptr = (encoder->base.head.next)
; (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*encoder), base.head) );})) {
220 /* We'll check the MST primary port */
221 if (encoder->type == INTEL_OUTPUT_DP_MST)
222 continue;
223
224 dig_port = enc_to_dig_port(encoder);
225 if (!dig_port)
226 continue;
227
228 if (dig_port->aux_ch != aux_ch) {
229 dig_port = NULL((void *)0);
230 continue;
231 }
232
233 break;
234 }
235
236 return dig_port;
237}
238
239static enum phy icl_aux_pw_to_phy(struct drm_i915_privateinteldrm_softc *i915,
240 const struct i915_power_well *power_well)
241{
242 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
243 struct intel_digital_port *dig_port = aux_ch_to_digital_port(i915, aux_ch);
244
245 return intel_port_to_phy(i915, dig_port->base.port);
246}
247
248static void hsw_wait_for_power_well_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
249 struct i915_power_well *power_well,
250 bool_Bool timeout_expected)
251{
252 const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
253 int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
254
255 /*
256 * For some power wells we're not supposed to watch the status bit for
257 * an ack, but rather just wait a fixed amount of time and then
258 * proceed. This is only used on DG2.
259 */
260 if (IS_DG2(dev_priv)IS_PLATFORM(dev_priv, INTEL_DG2) && power_well->desc->fixed_enable_delay) {
261 usleep_range(600, 1200);
262 return;
263 }
264
265 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
266 if (intel_de_wait_for_set(dev_priv, regs->driver,
267 HSW_PWR_WELL_CTL_STATE(pw_idx)(0x1 << ((pw_idx) * 2)), 1)) {
268 drm_dbg_kms(&dev_priv->drm, "%s power well enable timeout\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "%s power well enable timeout\n"
, intel_power_well_name(power_well))
269 intel_power_well_name(power_well))__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "%s power well enable timeout\n"
, intel_power_well_name(power_well));
270
271 drm_WARN_ON(&dev_priv->drm, !timeout_expected)({ int __ret = !!((!timeout_expected)); if (__ret) printf("%s %s: "
"%s", dev_driver_string(((&dev_priv->drm))->dev), ""
, "drm_WARN_ON(" "!timeout_expected" ")"); __builtin_expect(!
!(__ret), 0); });
272
273 }
274}
275
276static u32 hsw_power_well_requesters(struct drm_i915_privateinteldrm_softc *dev_priv,
277 const struct i915_power_well_regs *regs,
278 int pw_idx)
279{
280 u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx)(0x2 << ((pw_idx) * 2));
281 u32 ret;
282
283 ret = intel_de_read(dev_priv, regs->bios) & req_mask ? 1 : 0;
284 ret |= intel_de_read(dev_priv, regs->driver) & req_mask ? 2 : 0;
285 if (regs->kvmr.reg)
286 ret |= intel_de_read(dev_priv, regs->kvmr) & req_mask ? 4 : 0;
287 ret |= intel_de_read(dev_priv, regs->debug) & req_mask ? 8 : 0;
288
289 return ret;
290}
291
292static void hsw_wait_for_power_well_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
293 struct i915_power_well *power_well)
294{
295 const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
296 int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
297 bool_Bool disabled;
298 u32 reqs;
299
300 /*
301 * Bspec doesn't require waiting for PWs to get disabled, but still do
302 * this for paranoia. The known cases where a PW will be forced on:
303 * - a KVMR request on any power well via the KVMR request register
304 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and
305 * DEBUG request registers
306 * Skip the wait in case any of the request bits are set and print a
307 * diagnostic message.
308 */
309 wait_for((disabled = !(intel_de_read(dev_priv, regs->driver) &({ const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll
* (((1) * 1000))); long wait__ = ((10)); int ret__; assertwaitok
(); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw
(), end__); ; __asm volatile("" : : : "memory"); if ((((disabled
= !(intel_de_read(dev_priv, regs->driver) & (0x1 <<
((pw_idx) * 2)))) || (reqs = hsw_power_well_requesters(dev_priv
, regs, pw_idx))))) { ret__ = 0; break; } if (expired__) { ret__
= -60; break; } usleep_range(wait__, wait__ * 2); if (wait__
< ((1000))) wait__ <<= 1; } ret__; })
310 HSW_PWR_WELL_CTL_STATE(pw_idx))) ||({ const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll
* (((1) * 1000))); long wait__ = ((10)); int ret__; assertwaitok
(); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw
(), end__); ; __asm volatile("" : : : "memory"); if ((((disabled
= !(intel_de_read(dev_priv, regs->driver) & (0x1 <<
((pw_idx) * 2)))) || (reqs = hsw_power_well_requesters(dev_priv
, regs, pw_idx))))) { ret__ = 0; break; } if (expired__) { ret__
= -60; break; } usleep_range(wait__, wait__ * 2); if (wait__
< ((1000))) wait__ <<= 1; } ret__; })
311 (reqs = hsw_power_well_requesters(dev_priv, regs, pw_idx)), 1)({ const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll
* (((1) * 1000))); long wait__ = ((10)); int ret__; assertwaitok
(); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw
(), end__); ; __asm volatile("" : : : "memory"); if ((((disabled
= !(intel_de_read(dev_priv, regs->driver) & (0x1 <<
((pw_idx) * 2)))) || (reqs = hsw_power_well_requesters(dev_priv
, regs, pw_idx))))) { ret__ = 0; break; } if (expired__) { ret__
= -60; break; } usleep_range(wait__, wait__ * 2); if (wait__
< ((1000))) wait__ <<= 1; } ret__; });
312 if (disabled)
313 return;
314
315 drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n"
, intel_power_well_name(power_well), !!(reqs & 1), !!(reqs
& 2), !!(reqs & 4), !!(reqs & 8))
316 "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n"
, intel_power_well_name(power_well), !!(reqs & 1), !!(reqs
& 2), !!(reqs & 4), !!(reqs & 8))
317 intel_power_well_name(power_well),__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n"
, intel_power_well_name(power_well), !!(reqs & 1), !!(reqs
& 2), !!(reqs & 4), !!(reqs & 8))
318 !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8))__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n"
, intel_power_well_name(power_well), !!(reqs & 1), !!(reqs
& 2), !!(reqs & 4), !!(reqs & 8));
319}
320
321static void gen9_wait_for_power_well_fuses(struct drm_i915_privateinteldrm_softc *dev_priv,
322 enum skl_power_gate pg)
323{
324 /* Timeout 5us for PG#0, for other PGs 1us */
325 drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((intel_de_wait_for_set(dev_priv, ((const i915_reg_t
){ .reg = (0x42000) }), (1 << (27 - (pg))), 1))); if (__ret
) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->
drm))->dev), "", "drm_WARN_ON(" "intel_de_wait_for_set(dev_priv, ((const i915_reg_t){ .reg = (0x42000) }), (1 << (27 - (pg))), 1)"
")"); __builtin_expect(!!(__ret), 0); })
17
←
The result of the left shift is undefined due to shifting by '40', which is greater or equal to the width of type 'int'
326 intel_de_wait_for_set(dev_priv, SKL_FUSE_STATUS,({ int __ret = !!((intel_de_wait_for_set(dev_priv, ((const i915_reg_t
){ .reg = (0x42000) }), (1 << (27 - (pg))), 1))); if (__ret
) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->
drm))->dev), "", "drm_WARN_ON(" "intel_de_wait_for_set(dev_priv, ((const i915_reg_t){ .reg = (0x42000) }), (1 << (27 - (pg))), 1)"
")"); __builtin_expect(!!(__ret), 0); })
327 SKL_FUSE_PG_DIST_STATUS(pg), 1))({ int __ret = !!((intel_de_wait_for_set(dev_priv, ((const i915_reg_t
){ .reg = (0x42000) }), (1 << (27 - (pg))), 1))); if (__ret
) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->
drm))->dev), "", "drm_WARN_ON(" "intel_de_wait_for_set(dev_priv, ((const i915_reg_t){ .reg = (0x42000) }), (1 << (27 - (pg))), 1)"
")"); __builtin_expect(!!(__ret), 0); });
328}
329
330static void hsw_power_well_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
331 struct i915_power_well *power_well)
332{
333 const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
334 int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
335 u32 val;
336
337 if (power_well->desc->has_fuses) {
6
←
Assuming field 'has_fuses' is not equal to 0
→
7
←
Taking true branch
→
338 enum skl_power_gate pg;
339
340 pg = DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx)((pw_idx) - 0 + SKL_PG1) :
8
←
Assuming field 'ver' is >= 11
→
9
←
'?' condition is true
→
341 SKL_PW_CTL_IDX_TO_PG(pw_idx)((pw_idx) - 14 + SKL_PG1);
342
343 /* Wa_16013190616:adlp */
344 if (IS_ALDERLAKE_P(dev_priv)IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P) && pg == SKL_PG1)
10
←
Assuming the condition is false
→
345 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1((const i915_reg_t){ .reg = (0x46430) }), 0, DISABLE_FLR_SRC((u32)((1UL << (15)) + 0)));
346
347 /*
348 * For PW1 we have to wait both for the PW0/PG0 fuse state
349 * before enabling the power well and PW1/PG1's own fuse
350 * state after the enabling. For all other power wells with
351 * fuses we only have to wait for that PW/PG's fuse state
352 * after the enabling.
353 */
354 if (pg == SKL_PG1)
11
←
Assuming 'pg' is equal to SKL_PG1
→
12
←
Taking true branch
→
355 gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0);
356 }
357
358 val = intel_de_read(dev_priv, regs->driver);
359 intel_de_write(dev_priv, regs->driver,
360 val | HSW_PWR_WELL_CTL_REQ(pw_idx)(0x2 << ((pw_idx) * 2)));
361
362 hsw_wait_for_power_well_enable(dev_priv, power_well, false0);
363
364 if (power_well->desc->has_fuses
12.1
Field 'has_fuses' is not equal to 0
) {
13
←
Taking true branch
→
365 enum skl_power_gate pg;
366
367 pg = DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx)((pw_idx) - 0 + SKL_PG1) :
14
←
Assuming field 'ver' is < 11
→
15
←
'?' condition is false
→
368 SKL_PW_CTL_IDX_TO_PG(pw_idx)((pw_idx) - 14 + SKL_PG1);
369 gen9_wait_for_power_well_fuses(dev_priv, pg);
16
←
Calling 'gen9_wait_for_power_well_fuses'
→
370 }
371
372 hsw_power_well_post_enable(dev_priv,
373 power_well->desc->irq_pipe_mask,
374 power_well->desc->has_vga);
375}
376
377static void hsw_power_well_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
378 struct i915_power_well *power_well)
379{
380 const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
381 int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
382 u32 val;
383
384 hsw_power_well_pre_disable(dev_priv,
385 power_well->desc->irq_pipe_mask);
386
387 val = intel_de_read(dev_priv, regs->driver);
388 intel_de_write(dev_priv, regs->driver,
389 val & ~HSW_PWR_WELL_CTL_REQ(pw_idx)(0x2 << ((pw_idx) * 2)));
390 hsw_wait_for_power_well_disable(dev_priv, power_well);
391}
392
393static void
394icl_combo_phy_aux_power_well_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
395 struct i915_power_well *power_well)
396{
397 const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
398 int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
399 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
400 u32 val;
401
402 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv))({ int __ret = !!((!IS_PLATFORM(dev_priv, INTEL_ICELAKE))); if
(__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv
->drm))->dev), "", "drm_WARN_ON(" "!IS_PLATFORM(dev_priv, INTEL_ICELAKE)"
")"); __builtin_expect(!!(__ret), 0); });
403
404 val = intel_de_read(dev_priv, regs->driver);
405 intel_de_write(dev_priv, regs->driver,
406 val | HSW_PWR_WELL_CTL_REQ(pw_idx)(0x2 << ((pw_idx) * 2)));
407
408 if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) < 12) {
409 val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000, 0x16B000 })[phy]) + 4 * (12))) }));
410 intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000, 0x16B000 })[phy]) + 4 * (12))) }),
411 val | ICL_LANE_ENABLE_AUX(1 << 0));
412 }
413
414 hsw_wait_for_power_well_enable(dev_priv, power_well, false0);
415
416 /* Display WA #1178: icl */
417 if (pw_idx >= ICL_PW_CTL_IDX_AUX_A0 && pw_idx <= ICL_PW_CTL_IDX_AUX_B1 &&
418 !intel_bios_is_port_edp(dev_priv, (enum port)phy)) {
419 val = intel_de_read(dev_priv, ICL_AUX_ANAOVRD1(pw_idx)((const i915_reg_t){ .reg = ((((const u32 []){ 0x162398, 0x6C398
})[((pw_idx) - 0)])) }));
420 val |= ICL_AUX_ANAOVRD1_ENABLE(1 << 0) | ICL_AUX_ANAOVRD1_LDO_BYPASS(1 << 7);
421 intel_de_write(dev_priv, ICL_AUX_ANAOVRD1(pw_idx)((const i915_reg_t){ .reg = ((((const u32 []){ 0x162398, 0x6C398
})[((pw_idx) - 0)])) }), val);
422 }
423}
424
425static void
426icl_combo_phy_aux_power_well_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
427 struct i915_power_well *power_well)
428{
429 const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
430 int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
431 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
432 u32 val;
433
434 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv))({ int __ret = !!((!IS_PLATFORM(dev_priv, INTEL_ICELAKE))); if
(__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv
->drm))->dev), "", "drm_WARN_ON(" "!IS_PLATFORM(dev_priv, INTEL_ICELAKE)"
")"); __builtin_expect(!!(__ret), 0); });
435
436 val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000, 0x16B000 })[phy]) + 4 * (12))) }));
437 intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000
, 0x160000, 0x161000, 0x16B000 })[phy]) + 4 * (12))) }),
438 val & ~ICL_LANE_ENABLE_AUX(1 << 0));
439
440 val = intel_de_read(dev_priv, regs->driver);
441 intel_de_write(dev_priv, regs->driver,
442 val & ~HSW_PWR_WELL_CTL_REQ(pw_idx)(0x2 << ((pw_idx) * 2)));
443
444 hsw_wait_for_power_well_disable(dev_priv, power_well);
445}
446
447#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)0
448
449static void icl_tc_port_assert_ref_held(struct drm_i915_privateinteldrm_softc *dev_priv,
450 struct i915_power_well *power_well,
451 struct intel_digital_port *dig_port)
452{
453 if (drm_WARN_ON(&dev_priv->drm, !dig_port)({ int __ret = !!((!dig_port)); if (__ret) printf("%s %s: " "%s"
, dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON("
"!dig_port" ")"); __builtin_expect(!!(__ret), 0); }))
454 return;
455
456 if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) == 11 && intel_tc_cold_requires_aux_pw(dig_port))
457 return;
458
459 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port))({ int __ret = !!((!intel_tc_port_ref_held(dig_port))); if (__ret
) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->
drm))->dev), "", "drm_WARN_ON(" "!intel_tc_port_ref_held(dig_port)"
")"); __builtin_expect(!!(__ret), 0); });
460}
461
462#else
463
464static void icl_tc_port_assert_ref_held(struct drm_i915_privateinteldrm_softc *dev_priv,
465 struct i915_power_well *power_well,
466 struct intel_digital_port *dig_port)
467{
468}
469
470#endif
471
472#define TGL_AUX_PW_TO_TC_PORT(pw_idx)((pw_idx) - 3) ((pw_idx) - TGL_PW_CTL_IDX_AUX_TC13)
473
474static void icl_tc_cold_exit(struct drm_i915_privateinteldrm_softc *i915)
475{
476 int ret, tries = 0;
477
478 while (1) {
479 ret = snb_pcode_write_timeout(&i915->uncore, ICL_PCODE_EXIT_TCCOLD0x12, 0,
480 250, 1);
481 if (ret != -EAGAIN35 || ++tries == 3)
482 break;
483 drm_msleep(1)mdelay(1);
484 }
485
486 /* Spec states that TC cold exit can take up to 1ms to complete */
487 if (!ret)
488 drm_msleep(1)mdelay(1);
489
490 /* TODO: turn failure into a error as soon i915 CI updates ICL IFWI */
491 drm_dbg_kms(&i915->drm, "TC cold block %s\n", ret ? "failed" :__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "TC cold block %s\n",
ret ? "failed" : "succeeded")
492 "succeeded")__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "TC cold block %s\n",
ret ? "failed" : "succeeded");
493}
494
495static void
496icl_tc_phy_aux_power_well_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
497 struct i915_power_well *power_well)
498{
499 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
500 struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
501 const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
502 bool_Bool is_tbt = power_well->desc->is_tc_tbt;
503 bool_Bool timeout_expected;
504 u32 val;
505
506 icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port);
507
508 val = intel_de_read(dev_priv, DP_AUX_CH_CTL(aux_ch)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info)
->display.mmio_offset) + 0x64010)) + (aux_ch) * (((((&
(dev_priv)->__info)->display.mmio_offset) + 0x64110)) -
((((&(dev_priv)->__info)->display.mmio_offset) + 0x64010
))))) }));
509 val &= ~DP_AUX_CH_CTL_TBT_IO(1 << 11);
510 if (is_tbt)
511 val |= DP_AUX_CH_CTL_TBT_IO(1 << 11);
512 intel_de_write(dev_priv, DP_AUX_CH_CTL(aux_ch)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info)
->display.mmio_offset) + 0x64010)) + (aux_ch) * (((((&
(dev_priv)->__info)->display.mmio_offset) + 0x64110)) -
((((&(dev_priv)->__info)->display.mmio_offset) + 0x64010
))))) }), val);
513
514 val = intel_de_read(dev_priv, regs->driver);
515 intel_de_write(dev_priv, regs->driver,
516 val | HSW_PWR_WELL_CTL_REQ(i915_power_well_instance(power_well)->hsw.idx)(0x2 << ((i915_power_well_instance(power_well)->hsw.
idx) * 2)));
517
518 /*
519 * An AUX timeout is expected if the TBT DP tunnel is down,
520 * or need to enable AUX on a legacy TypeC port as part of the TC-cold
521 * exit sequence.
522 */
523 timeout_expected = is_tbt || intel_tc_cold_requires_aux_pw(dig_port);
524 if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) == 11 && intel_tc_cold_requires_aux_pw(dig_port))
525 icl_tc_cold_exit(dev_priv);
526
527 hsw_wait_for_power_well_enable(dev_priv, power_well, timeout_expected);
528
529 if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12 && !is_tbt) {
530 enum tc_port tc_port;
531
532 tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx)((i915_power_well_instance(power_well)->hsw.idx) - 3);
533
534 if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port), 2) &({ const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll
* (((1) * 1000))); long wait__ = ((10)); int ret__; assertwaitok
(); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw
(), end__); ; __asm volatile("" : : : "memory"); if (((intel_dkl_phy_read
(dev_priv, ((const i915_reg_t){ .reg = (((0x168000) + (tc_port
) * ((0x169000) - (0x168000))) + 0x36C) }), 2) & (0x1 <<
15)))) { ret__ = 0; break; } if (expired__) { ret__ = -60; break
; } usleep_range(wait__, wait__ * 2); if (wait__ < ((1000)
)) wait__ <<= 1; } ret__; })
535 DKL_CMN_UC_DW27_UC_HEALTH, 1)({ const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll
* (((1) * 1000))); long wait__ = ((10)); int ret__; assertwaitok
(); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw
(), end__); ; __asm volatile("" : : : "memory"); if (((intel_dkl_phy_read
(dev_priv, ((const i915_reg_t){ .reg = (((0x168000) + (tc_port
) * ((0x169000) - (0x168000))) + 0x36C) }), 2) & (0x1 <<
15)))) { ret__ = 0; break; } if (expired__) { ret__ = -60; break
; } usleep_range(wait__, wait__ * 2); if (wait__ < ((1000)
)) wait__ <<= 1; } ret__; }))
536 drm_warn(&dev_priv->drm,printf("drm:pid%d:%s *WARNING* " "[drm] " "Timeout waiting TC uC health\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
537 "Timeout waiting TC uC health\n")printf("drm:pid%d:%s *WARNING* " "[drm] " "Timeout waiting TC uC health\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
538 }
539}
540
541static void
542icl_aux_power_well_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
543 struct i915_power_well *power_well)
544{
545 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
546
547 if (intel_phy_is_tc(dev_priv, phy))
1
Assuming the condition is false
→
2
←
Taking false branch
→
548 return icl_tc_phy_aux_power_well_enable(dev_priv, power_well);
549 else if (IS_ICELAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ICELAKE))
3
←
Assuming the condition is false
→
4
←
Taking false branch
→
550 return icl_combo_phy_aux_power_well_enable(dev_priv,
551 power_well);
552 else
553 return hsw_power_well_enable(dev_priv, power_well);
5
←
Calling 'hsw_power_well_enable'
→
554}
555
556static void
557icl_aux_power_well_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
558 struct i915_power_well *power_well)
559{
560 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
561
562 if (intel_phy_is_tc(dev_priv, phy))
563 return hsw_power_well_disable(dev_priv, power_well);
564 else if (IS_ICELAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ICELAKE))
565 return icl_combo_phy_aux_power_well_disable(dev_priv,
566 power_well);
567 else
568 return hsw_power_well_disable(dev_priv, power_well);
569}
570
571/*
572 * We should only use the power well if we explicitly asked the hardware to
573 * enable it, so check if it's enabled and also check if we've requested it to
574 * be enabled.
575 */
576static bool_Bool hsw_power_well_enabled(struct drm_i915_privateinteldrm_softc *dev_priv,
577 struct i915_power_well *power_well)
578{
579 const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
580 enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
581 int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
582 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx)(0x2 << ((pw_idx) * 2)) |
583 HSW_PWR_WELL_CTL_STATE(pw_idx)(0x1 << ((pw_idx) * 2));
584 u32 val;
585
586 val = intel_de_read(dev_priv, regs->driver);
587
588 /*
589 * On GEN9 big core due to a DMC bug the driver's request bits for PW1
590 * and the MISC_IO PW will be not restored, so check instead for the
591 * BIOS's own request bits, which are forced-on for these power wells
592 * when exiting DC5/6.
593 */
594 if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) == 9 && !IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON) &&
595 (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO))
596 val |= intel_de_read(dev_priv, regs->bios);
597
598 return (val & mask) == mask;
599}
600
601static void assert_can_enable_dc9(struct drm_i915_privateinteldrm_softc *dev_priv)
602{
603 drm_WARN_ONCE(&dev_priv->drm,({ static int __warned; int __ret = !!((intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x45504) })) & (1 <<
3))); if (__ret && !__warned) { printf("%s %s: " "DC9 already programmed to be enabled.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); })
604 (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC9),({ static int __warned; int __ret = !!((intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x45504) })) & (1 <<
3))); if (__ret && !__warned) { printf("%s %s: " "DC9 already programmed to be enabled.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); })
605 "DC9 already programmed to be enabled.\n")({ static int __warned; int __ret = !!((intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x45504) })) & (1 <<
3))); if (__ret && !__warned) { printf("%s %s: " "DC9 already programmed to be enabled.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); });
606 drm_WARN_ONCE(&dev_priv->drm,({ static int __warned; int __ret = !!(intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x45504) })) & (1 <<
0)); if (__ret && !__warned) { printf("%s %s: " "DC5 still not disabled to enable DC9.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); })
607 intel_de_read(dev_priv, DC_STATE_EN) &({ static int __warned; int __ret = !!(intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x45504) })) & (1 <<
0)); if (__ret && !__warned) { printf("%s %s: " "DC5 still not disabled to enable DC9.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); })
608 DC_STATE_EN_UPTO_DC5,({ static int __warned; int __ret = !!(intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x45504) })) & (1 <<
0)); if (__ret && !__warned) { printf("%s %s: " "DC5 still not disabled to enable DC9.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); })
609 "DC5 still not disabled to enable DC9.\n")({ static int __warned; int __ret = !!(intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x45504) })) & (1 <<
0)); if (__ret && !__warned) { printf("%s %s: " "DC5 still not disabled to enable DC9.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); });
610 drm_WARN_ONCE(&dev_priv->drm,({ static int __warned; int __ret = !!(intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x45404) })) & (0x2 <<
((15) * 2))); if (__ret && !__warned) { printf("%s %s: "
"Power well 2 on.\n", dev_driver_string((&dev_priv->drm
)->dev), ""); __warned = 1; } __builtin_expect(!!(__ret), 0
); })
611 intel_de_read(dev_priv, HSW_PWR_WELL_CTL2) &({ static int __warned; int __ret = !!(intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x45404) })) & (0x2 <<
((15) * 2))); if (__ret && !__warned) { printf("%s %s: "
"Power well 2 on.\n", dev_driver_string((&dev_priv->drm
)->dev), ""); __warned = 1; } __builtin_expect(!!(__ret), 0
); })
612 HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2),({ static int __warned; int __ret = !!(intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x45404) })) & (0x2 <<
((15) * 2))); if (__ret && !__warned) { printf("%s %s: "
"Power well 2 on.\n", dev_driver_string((&dev_priv->drm
)->dev), ""); __warned = 1; } __builtin_expect(!!(__ret), 0
); })
613 "Power well 2 on.\n")({ static int __warned; int __ret = !!(intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x45404) })) & (0x2 <<
((15) * 2))); if (__ret && !__warned) { printf("%s %s: "
"Power well 2 on.\n", dev_driver_string((&dev_priv->drm
)->dev), ""); __warned = 1; } __builtin_expect(!!(__ret), 0
); });
614 drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv),({ static int __warned; int __ret = !!(intel_irqs_enabled(dev_priv
)); if (__ret && !__warned) { printf("%s %s: " "Interrupts not disabled yet.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); })
615 "Interrupts not disabled yet.\n")({ static int __warned; int __ret = !!(intel_irqs_enabled(dev_priv
)); if (__ret && !__warned) { printf("%s %s: " "Interrupts not disabled yet.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); });
616
617 /*
618 * TODO: check for the following to verify the conditions to enter DC9
619 * state are satisfied:
620 * 1] Check relevant display engine registers to verify if mode set
621 * disable sequence was followed.
622 * 2] Check if display uninitialize sequence is initialized.
623 */
624}
625
626static void assert_can_disable_dc9(struct drm_i915_privateinteldrm_softc *dev_priv)
627{
628 drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv),({ static int __warned; int __ret = !!(intel_irqs_enabled(dev_priv
)); if (__ret && !__warned) { printf("%s %s: " "Interrupts not disabled yet.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); })
629 "Interrupts not disabled yet.\n")({ static int __warned; int __ret = !!(intel_irqs_enabled(dev_priv
)); if (__ret && !__warned) { printf("%s %s: " "Interrupts not disabled yet.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); });
630 drm_WARN_ONCE(&dev_priv->drm,({ static int __warned; int __ret = !!(intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x45504) })) & (1 <<
0)); if (__ret && !__warned) { printf("%s %s: " "DC5 still not disabled.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); })
631 intel_de_read(dev_priv, DC_STATE_EN) &({ static int __warned; int __ret = !!(intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x45504) })) & (1 <<
0)); if (__ret && !__warned) { printf("%s %s: " "DC5 still not disabled.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); })
632 DC_STATE_EN_UPTO_DC5,({ static int __warned; int __ret = !!(intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x45504) })) & (1 <<
0)); if (__ret && !__warned) { printf("%s %s: " "DC5 still not disabled.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); })
633 "DC5 still not disabled.\n")({ static int __warned; int __ret = !!(intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x45504) })) & (1 <<
0)); if (__ret && !__warned) { printf("%s %s: " "DC5 still not disabled.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); });
634
635 /*
636 * TODO: check for the following to verify DC9 state was indeed
637 * entered before programming to disable it:
638 * 1] Check relevant display engine registers to verify if mode
639 * set disable sequence was followed.
640 * 2] Check if display uninitialize sequence is initialized.
641 */
642}
643
644static void gen9_write_dc_state(struct drm_i915_privateinteldrm_softc *dev_priv,
645 u32 state)
646{
647 int rewrites = 0;
648 int rereads = 0;
649 u32 v;
650
651 intel_de_write(dev_priv, DC_STATE_EN((const i915_reg_t){ .reg = (0x45504) }), state);
652
653 /* It has been observed that disabling the dc6 state sometimes
654 * doesn't stick and dmc keeps returning old value. Make sure
655 * the write really sticks enough times and also force rewrite until
656 * we are confident that state is exactly what we want.
657 */
658 do {
659 v = intel_de_read(dev_priv, DC_STATE_EN((const i915_reg_t){ .reg = (0x45504) }));
660
661 if (v != state) {
662 intel_de_write(dev_priv, DC_STATE_EN((const i915_reg_t){ .reg = (0x45504) }), state);
663 rewrites++;
664 rereads = 0;
665 } else if (rereads++ > 5) {
666 break;
667 }
668
669 } while (rewrites < 100);
670
671 if (v != state)
672 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Writing dc state to 0x%x failed, now 0x%x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , state,
v)
673 "Writing dc state to 0x%x failed, now 0x%x\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Writing dc state to 0x%x failed, now 0x%x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , state,
v)
674 state, v)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Writing dc state to 0x%x failed, now 0x%x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , state,
v);
675
676 /* Most of the times we need one retry, avoid spam */
677 if (rewrites > 1)
678 drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Rewrote dc state to 0x%x %d times\n"
, state, rewrites)
679 "Rewrote dc state to 0x%x %d times\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Rewrote dc state to 0x%x %d times\n"
, state, rewrites)
680 state, rewrites)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Rewrote dc state to 0x%x %d times\n"
, state, rewrites);
681}
682
683static u32 gen9_dc_mask(struct drm_i915_privateinteldrm_softc *dev_priv)
684{
685 u32 mask;
686
687 mask = DC_STATE_EN_UPTO_DC5(1 << 0);
688
689 if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12)
690 mask |= DC_STATE_EN_DC3CO((u32)((1UL << (30)) + 0)) | DC_STATE_EN_UPTO_DC6(2 << 0)
691 | DC_STATE_EN_DC9(1 << 3);
692 else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) == 11)
693 mask |= DC_STATE_EN_UPTO_DC6(2 << 0) | DC_STATE_EN_DC9(1 << 3);
694 else if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON))
695 mask |= DC_STATE_EN_DC9(1 << 3);
696 else
697 mask |= DC_STATE_EN_UPTO_DC6(2 << 0);
698
699 return mask;
700}
701
702void gen9_sanitize_dc_state(struct drm_i915_privateinteldrm_softc *dev_priv)
703{
704 u32 val;
705
706 if (!HAS_DISPLAY(dev_priv)((&(dev_priv)->__runtime)->pipe_mask != 0))
707 return;
708
709 val = intel_de_read(dev_priv, DC_STATE_EN((const i915_reg_t){ .reg = (0x45504) })) & gen9_dc_mask(dev_priv);
710
711 drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Resetting DC state tracking from %02x to %02x\n"
, dev_priv->display.dmc.dc_state, val)
712 "Resetting DC state tracking from %02x to %02x\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Resetting DC state tracking from %02x to %02x\n"
, dev_priv->display.dmc.dc_state, val)
713 dev_priv->display.dmc.dc_state, val)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Resetting DC state tracking from %02x to %02x\n"
, dev_priv->display.dmc.dc_state, val);
714 dev_priv->display.dmc.dc_state = val;
715}
716
717/**
718 * gen9_set_dc_state - set target display C power state
719 * @dev_priv: i915 device instance
720 * @state: target DC power state
721 * - DC_STATE_DISABLE
722 * - DC_STATE_EN_UPTO_DC5
723 * - DC_STATE_EN_UPTO_DC6
724 * - DC_STATE_EN_DC9
725 *
726 * Signal to DMC firmware/HW the target DC power state passed in @state.
727 * DMC/HW can turn off individual display clocks and power rails when entering
728 * a deeper DC power state (higher in number) and turns these back when exiting
729 * that state to a shallower power state (lower in number). The HW will decide
730 * when to actually enter a given state on an on-demand basis, for instance
731 * depending on the active state of display pipes. The state of display
732 * registers backed by affected power rails are saved/restored as needed.
733 *
734 * Based on the above enabling a deeper DC power state is asynchronous wrt.
735 * enabling it. Disabling a deeper power state is synchronous: for instance
736 * setting %DC_STATE_DISABLE won't complete until all HW resources are turned
737 * back on and register state is restored. This is guaranteed by the MMIO write
738 * to DC_STATE_EN blocking until the state is restored.
739 */
740void gen9_set_dc_state(struct drm_i915_privateinteldrm_softc *dev_priv, u32 state)
741{
742 u32 val;
743 u32 mask;
744
745 if (!HAS_DISPLAY(dev_priv)((&(dev_priv)->__runtime)->pipe_mask != 0))
746 return;
747
748 if (drm_WARN_ON_ONCE(&dev_priv->drm,({ static int __warned; int __ret = !!((state & ~dev_priv
->display.dmc.allowed_dc_mask)); if (__ret && !__warned
) { printf("%s %s: " "%s", dev_driver_string(((&dev_priv->
drm))->dev), "", "drm_WARN_ON_ONCE(" "state & ~dev_priv->display.dmc.allowed_dc_mask"
")"); __warned = 1; } __builtin_expect(!!(__ret), 0); })
749 state & ~dev_priv->display.dmc.allowed_dc_mask)({ static int __warned; int __ret = !!((state & ~dev_priv
->display.dmc.allowed_dc_mask)); if (__ret && !__warned
) { printf("%s %s: " "%s", dev_driver_string(((&dev_priv->
drm))->dev), "", "drm_WARN_ON_ONCE(" "state & ~dev_priv->display.dmc.allowed_dc_mask"
")"); __warned = 1; } __builtin_expect(!!(__ret), 0); }))
750 state &= dev_priv->display.dmc.allowed_dc_mask;
751
752 val = intel_de_read(dev_priv, DC_STATE_EN((const i915_reg_t){ .reg = (0x45504) }));
753 mask = gen9_dc_mask(dev_priv);
754 drm_dbg_kms(&dev_priv->drm, "Setting DC state from %02x to %02x\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Setting DC state from %02x to %02x\n"
, val & mask, state)
755 val & mask, state)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Setting DC state from %02x to %02x\n"
, val & mask, state);
756
757 /* Check if DMC is ignoring our DC state requests */
758 if ((val & mask) != dev_priv->display.dmc.dc_state)
759 drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "DC state mismatch (0x%x -> 0x%x)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , dev_priv
->display.dmc.dc_state, val & mask)
760 dev_priv->display.dmc.dc_state, val & mask)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "DC state mismatch (0x%x -> 0x%x)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , dev_priv
->display.dmc.dc_state, val & mask);
761
762 val &= ~mask;
763 val |= state;
764
765 gen9_write_dc_state(dev_priv, val);
766
767 dev_priv->display.dmc.dc_state = val & mask;
768}
769
770static void tgl_enable_dc3co(struct drm_i915_privateinteldrm_softc *dev_priv)
771{
772 drm_dbg_kms(&dev_priv->drm, "Enabling DC3CO\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Enabling DC3CO\n"
);
773 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO((u32)((1UL << (30)) + 0)));
774}
775
776static void tgl_disable_dc3co(struct drm_i915_privateinteldrm_softc *dev_priv)
777{
778 u32 val;
779
780 drm_dbg_kms(&dev_priv->drm, "Disabling DC3CO\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Disabling DC3CO\n"
);
781 val = intel_de_read(dev_priv, DC_STATE_EN((const i915_reg_t){ .reg = (0x45504) }));
782 val &= ~DC_STATE_DC3CO_STATUS((u32)((1UL << (29)) + 0));
783 intel_de_write(dev_priv, DC_STATE_EN((const i915_reg_t){ .reg = (0x45504) }), val);
784 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE0);
785 /*
786 * Delay of 200us DC3CO Exit time B.Spec 49196
787 */
788 usleep_range(200, 210);
789}
790
791static void assert_can_enable_dc5(struct drm_i915_privateinteldrm_softc *dev_priv)
792{
793 enum i915_power_well_id high_pg;
794
795 /* Power wells at this level and above must be disabled for DC5 entry */
796 if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) == 12)
797 high_pg = ICL_DISP_PW_3;
798 else
799 high_pg = SKL_DISP_PW_2;
800
801 drm_WARN_ONCE(&dev_priv->drm,({ static int __warned; int __ret = !!(intel_display_power_well_is_enabled
(dev_priv, high_pg)); if (__ret && !__warned) { printf
("%s %s: " "Power wells above platform's DC5 limit still enabled.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); })
802 intel_display_power_well_is_enabled(dev_priv, high_pg),({ static int __warned; int __ret = !!(intel_display_power_well_is_enabled
(dev_priv, high_pg)); if (__ret && !__warned) { printf
("%s %s: " "Power wells above platform's DC5 limit still enabled.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); })
803 "Power wells above platform's DC5 limit still enabled.\n")({ static int __warned; int __ret = !!(intel_display_power_well_is_enabled
(dev_priv, high_pg)); if (__ret && !__warned) { printf
("%s %s: " "Power wells above platform's DC5 limit still enabled.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); });
804
805 drm_WARN_ONCE(&dev_priv->drm,({ static int __warned; int __ret = !!((intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x45504) })) & (1 <<
0))); if (__ret && !__warned) { printf("%s %s: " "DC5 already programmed to be enabled.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); })
806 (intel_de_read(dev_priv, DC_STATE_EN) &({ static int __warned; int __ret = !!((intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x45504) })) & (1 <<
0))); if (__ret && !__warned) { printf("%s %s: " "DC5 already programmed to be enabled.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); })
807 DC_STATE_EN_UPTO_DC5),({ static int __warned; int __ret = !!((intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x45504) })) & (1 <<
0))); if (__ret && !__warned) { printf("%s %s: " "DC5 already programmed to be enabled.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); })
808 "DC5 already programmed to be enabled.\n")({ static int __warned; int __ret = !!((intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x45504) })) & (1 <<
0))); if (__ret && !__warned) { printf("%s %s: " "DC5 already programmed to be enabled.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); });
809 assert_rpm_wakelock_held(&dev_priv->runtime_pm);
810
811 assert_dmc_loaded(dev_priv);
812}
813
814void gen9_enable_dc5(struct drm_i915_privateinteldrm_softc *dev_priv)
815{
816 assert_can_enable_dc5(dev_priv);
817
818 drm_dbg_kms(&dev_priv->drm, "Enabling DC5\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Enabling DC5\n"
);
819
820 /* Wa Display #1183: skl,kbl,cfl */
821 if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) == 9 && !IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON))
822 intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1((const i915_reg_t){ .reg = (0x46430) }),
823 intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1((const i915_reg_t){ .reg = (0x46430) })) | SKL_SELECT_ALTERNATE_DC_EXIT((u32)((1UL << (30)) + 0)));
824
825 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5(1 << 0));
826}
827
828static void assert_can_enable_dc6(struct drm_i915_privateinteldrm_softc *dev_priv)
829{
830 drm_WARN_ONCE(&dev_priv->drm,({ static int __warned; int __ret = !!(intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x48400) })) & (1 <<
31)); if (__ret && !__warned) { printf("%s %s: " "Backlight is not disabled.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); })
831 intel_de_read(dev_priv, UTIL_PIN_CTL) & UTIL_PIN_ENABLE,({ static int __warned; int __ret = !!(intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x48400) })) & (1 <<
31)); if (__ret && !__warned) { printf("%s %s: " "Backlight is not disabled.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); })
832 "Backlight is not disabled.\n")({ static int __warned; int __ret = !!(intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x48400) })) & (1 <<
31)); if (__ret && !__warned) { printf("%s %s: " "Backlight is not disabled.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); });
833 drm_WARN_ONCE(&dev_priv->drm,({ static int __warned; int __ret = !!((intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x45504) })) & (2 <<
0))); if (__ret && !__warned) { printf("%s %s: " "DC6 already programmed to be enabled.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); })
834 (intel_de_read(dev_priv, DC_STATE_EN) &({ static int __warned; int __ret = !!((intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x45504) })) & (2 <<
0))); if (__ret && !__warned) { printf("%s %s: " "DC6 already programmed to be enabled.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); })
835 DC_STATE_EN_UPTO_DC6),({ static int __warned; int __ret = !!((intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x45504) })) & (2 <<
0))); if (__ret && !__warned) { printf("%s %s: " "DC6 already programmed to be enabled.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); })
836 "DC6 already programmed to be enabled.\n")({ static int __warned; int __ret = !!((intel_de_read(dev_priv
, ((const i915_reg_t){ .reg = (0x45504) })) & (2 <<
0))); if (__ret && !__warned) { printf("%s %s: " "DC6 already programmed to be enabled.\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __warned
= 1; } __builtin_expect(!!(__ret), 0); });
837
838 assert_dmc_loaded(dev_priv);
839}
840
841void skl_enable_dc6(struct drm_i915_privateinteldrm_softc *dev_priv)
842{
843 assert_can_enable_dc6(dev_priv);
844
845 drm_dbg_kms(&dev_priv->drm, "Enabling DC6\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Enabling DC6\n"
);
846
847 /* Wa Display #1183: skl,kbl,cfl */
848 if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) == 9 && !IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON))
849 intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1((const i915_reg_t){ .reg = (0x46430) }),
850 intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1((const i915_reg_t){ .reg = (0x46430) })) | SKL_SELECT_ALTERNATE_DC_EXIT((u32)((1UL << (30)) + 0)));
851
852 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6(2 << 0));
853}
854
855void bxt_enable_dc9(struct drm_i915_privateinteldrm_softc *dev_priv)
856{
857 assert_can_enable_dc9(dev_priv);
858
859 drm_dbg_kms(&dev_priv->drm, "Enabling DC9\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Enabling DC9\n"
);
860 /*
861 * Power sequencer reset is not needed on
862 * platforms with South Display Engine on PCH,
863 * because PPS registers are always on.
864 */
865 if (!HAS_PCH_SPLIT(dev_priv)(((dev_priv)->pch_type) != PCH_NONE))
866 intel_pps_reset_all(dev_priv);
867 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9(1 << 3));
868}
869
870void bxt_disable_dc9(struct drm_i915_privateinteldrm_softc *dev_priv)
871{
872 assert_can_disable_dc9(dev_priv);
873
874 drm_dbg_kms(&dev_priv->drm, "Disabling DC9\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Disabling DC9\n"
);
875
876 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE0);
877
878 intel_pps_unlock_regs_wa(dev_priv);
879}
880
881static void hsw_power_well_sync_hw(struct drm_i915_privateinteldrm_softc *dev_priv,
882 struct i915_power_well *power_well)
883{
884 const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
885 int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
886 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx)(0x2 << ((pw_idx) * 2));
887 u32 bios_req = intel_de_read(dev_priv, regs->bios);
888
889 /* Take over the request bit if set by BIOS. */
890 if (bios_req & mask) {
891 u32 drv_req = intel_de_read(dev_priv, regs->driver);
892
893 if (!(drv_req & mask))
894 intel_de_write(dev_priv, regs->driver, drv_req | mask);
895 intel_de_write(dev_priv, regs->bios, bios_req & ~mask);
896 }
897}
898
899static void bxt_dpio_cmn_power_well_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
900 struct i915_power_well *power_well)
901{
902 bxt_ddi_phy_init(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
903}
904
905static void bxt_dpio_cmn_power_well_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
906 struct i915_power_well *power_well)
907{
908 bxt_ddi_phy_uninit(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
909}
910
911static bool_Bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_privateinteldrm_softc *dev_priv,
912 struct i915_power_well *power_well)
913{
914 return bxt_ddi_phy_is_enabled(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
915}
916
917static void bxt_verify_ddi_phy_power_wells(struct drm_i915_privateinteldrm_softc *dev_priv)
918{
919 struct i915_power_well *power_well;
920
921 power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A);
922 if (intel_power_well_refcount(power_well) > 0)
923 bxt_ddi_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
924
925 power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
926 if (intel_power_well_refcount(power_well) > 0)
927 bxt_ddi_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
928
929 if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)) {
930 power_well = lookup_power_well(dev_priv,
931 GLK_DISP_PW_DPIO_CMN_C);
932 if (intel_power_well_refcount(power_well) > 0)
933 bxt_ddi_phy_verify_state(dev_priv,
934 i915_power_well_instance(power_well)->bxt.phy);
935 }
936}
937
938static bool_Bool gen9_dc_off_power_well_enabled(struct drm_i915_privateinteldrm_softc *dev_priv,
939 struct i915_power_well *power_well)
940{
941 return ((intel_de_read(dev_priv, DC_STATE_EN((const i915_reg_t){ .reg = (0x45504) })) & DC_STATE_EN_DC3CO((u32)((1UL << (30)) + 0))) == 0 &&
942 (intel_de_read(dev_priv, DC_STATE_EN((const i915_reg_t){ .reg = (0x45504) })) & DC_STATE_EN_UPTO_DC5_DC6_MASK0x3) == 0);
943}
944
945static void gen9_assert_dbuf_enabled(struct drm_i915_privateinteldrm_softc *dev_priv)
946{
947 u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(dev_priv);
948 u8 enabled_dbuf_slices = dev_priv->display.dbuf.enabled_slices;
949
950 drm_WARN(&dev_priv->drm,({ int __ret = !!(hw_enabled_dbuf_slices != enabled_dbuf_slices
); if (__ret) printf("%s %s: " "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n"
, dev_driver_string((&dev_priv->drm)->dev), "", hw_enabled_dbuf_slices
, enabled_dbuf_slices); __builtin_expect(!!(__ret), 0); })
951 hw_enabled_dbuf_slices != enabled_dbuf_slices,({ int __ret = !!(hw_enabled_dbuf_slices != enabled_dbuf_slices
); if (__ret) printf("%s %s: " "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n"
, dev_driver_string((&dev_priv->drm)->dev), "", hw_enabled_dbuf_slices
, enabled_dbuf_slices); __builtin_expect(!!(__ret), 0); })
952 "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n",({ int __ret = !!(hw_enabled_dbuf_slices != enabled_dbuf_slices
); if (__ret) printf("%s %s: " "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n"
, dev_driver_string((&dev_priv->drm)->dev), "", hw_enabled_dbuf_slices
, enabled_dbuf_slices); __builtin_expect(!!(__ret), 0); })
953 hw_enabled_dbuf_slices,({ int __ret = !!(hw_enabled_dbuf_slices != enabled_dbuf_slices
); if (__ret) printf("%s %s: " "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n"
, dev_driver_string((&dev_priv->drm)->dev), "", hw_enabled_dbuf_slices
, enabled_dbuf_slices); __builtin_expect(!!(__ret), 0); })
954 enabled_dbuf_slices)({ int __ret = !!(hw_enabled_dbuf_slices != enabled_dbuf_slices
); if (__ret) printf("%s %s: " "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n"
, dev_driver_string((&dev_priv->drm)->dev), "", hw_enabled_dbuf_slices
, enabled_dbuf_slices); __builtin_expect(!!(__ret), 0); });
955}
956
957void gen9_disable_dc_states(struct drm_i915_privateinteldrm_softc *dev_priv)
958{
959 struct intel_cdclk_config cdclk_config = {};
960
961 if (dev_priv->display.dmc.target_dc_state == DC_STATE_EN_DC3CO((u32)((1UL << (30)) + 0))) {
962 tgl_disable_dc3co(dev_priv);
963 return;
964 }
965
966 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE0);
967
968 if (!HAS_DISPLAY(dev_priv)((&(dev_priv)->__runtime)->pipe_mask != 0))
969 return;
970
971 intel_cdclk_get_cdclk(dev_priv, &cdclk_config);
972 /* Can't read out voltage_level so can't use intel_cdclk_changed() */
973 drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((intel_cdclk_needs_modeset(&dev_priv->
display.cdclk.hw, &cdclk_config))); if (__ret) printf("%s %s: "
"%s", dev_driver_string(((&dev_priv->drm))->dev), ""
, "drm_WARN_ON(" "intel_cdclk_needs_modeset(&dev_priv->display.cdclk.hw, &cdclk_config)"
")"); __builtin_expect(!!(__ret), 0); })
974 intel_cdclk_needs_modeset(&dev_priv->display.cdclk.hw,({ int __ret = !!((intel_cdclk_needs_modeset(&dev_priv->
display.cdclk.hw, &cdclk_config))); if (__ret) printf("%s %s: "
"%s", dev_driver_string(((&dev_priv->drm))->dev), ""
, "drm_WARN_ON(" "intel_cdclk_needs_modeset(&dev_priv->display.cdclk.hw, &cdclk_config)"
")"); __builtin_expect(!!(__ret), 0); })
975 &cdclk_config))({ int __ret = !!((intel_cdclk_needs_modeset(&dev_priv->
display.cdclk.hw, &cdclk_config))); if (__ret) printf("%s %s: "
"%s", dev_driver_string(((&dev_priv->drm))->dev), ""
, "drm_WARN_ON(" "intel_cdclk_needs_modeset(&dev_priv->display.cdclk.hw, &cdclk_config)"
")"); __builtin_expect(!!(__ret), 0); });
976
977 gen9_assert_dbuf_enabled(dev_priv);
978
979 if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON))
980 bxt_verify_ddi_phy_power_wells(dev_priv);
981
982 if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 11)
983 /*
984 * DMC retains HW context only for port A, the other combo
985 * PHY's HW context for port B is lost after DC transitions,
986 * so we need to restore it manually.
987 */
988 intel_combo_phy_init(dev_priv);
989}
990
991static void gen9_dc_off_power_well_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
992 struct i915_power_well *power_well)
993{
994 gen9_disable_dc_states(dev_priv);
995}
996
997static void gen9_dc_off_power_well_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
998 struct i915_power_well *power_well)
999{
1000 if (!intel_dmc_has_payload(dev_priv))
1001 return;
1002
1003 switch (dev_priv->display.dmc.target_dc_state) {
1004 case DC_STATE_EN_DC3CO((u32)((1UL << (30)) + 0)):
1005 tgl_enable_dc3co(dev_priv);
1006 break;
1007 case DC_STATE_EN_UPTO_DC6(2 << 0):
1008 skl_enable_dc6(dev_priv);
1009 break;
1010 case DC_STATE_EN_UPTO_DC5(1 << 0):
1011 gen9_enable_dc5(dev_priv);
1012 break;
1013 }
1014}
1015
1016static void i9xx_power_well_sync_hw_noop(struct drm_i915_privateinteldrm_softc *dev_priv,
1017 struct i915_power_well *power_well)
1018{
1019}
1020
1021static void i9xx_always_on_power_well_noop(struct drm_i915_privateinteldrm_softc *dev_priv,
1022 struct i915_power_well *power_well)
1023{
1024}
1025
1026static bool_Bool i9xx_always_on_power_well_enabled(struct drm_i915_privateinteldrm_softc *dev_priv,
1027 struct i915_power_well *power_well)
1028{
1029 return true1;
1030}
1031
1032static void i830_pipes_power_well_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
1033 struct i915_power_well *power_well)
1034{
1035 if ((intel_de_read(dev_priv, PIPECONF(PIPE_A)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
display.pipe_offsets[(PIPE_A)] - (&(dev_priv)->__info)
->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info
)->display.mmio_offset) + (0x70008)) })) & PIPECONF_ENABLE((u32)((1UL << (31)) + 0))) == 0)
1036 i830_enable_pipe(dev_priv, PIPE_A);
1037 if ((intel_de_read(dev_priv, PIPECONF(PIPE_B)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
display.pipe_offsets[(PIPE_B)] - (&(dev_priv)->__info)
->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info
)->display.mmio_offset) + (0x70008)) })) & PIPECONF_ENABLE((u32)((1UL << (31)) + 0))) == 0)
1038 i830_enable_pipe(dev_priv, PIPE_B);
1039}
1040
1041static void i830_pipes_power_well_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
1042 struct i915_power_well *power_well)
1043{
1044 i830_disable_pipe(dev_priv, PIPE_B);
1045 i830_disable_pipe(dev_priv, PIPE_A);
1046}
1047
1048static bool_Bool i830_pipes_power_well_enabled(struct drm_i915_privateinteldrm_softc *dev_priv,
1049 struct i915_power_well *power_well)
1050{
1051 return intel_de_read(dev_priv, PIPECONF(PIPE_A)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
display.pipe_offsets[(PIPE_A)] - (&(dev_priv)->__info)
->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info
)->display.mmio_offset) + (0x70008)) })) & PIPECONF_ENABLE((u32)((1UL << (31)) + 0)) &&
1052 intel_de_read(dev_priv, PIPECONF(PIPE_B)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
display.pipe_offsets[(PIPE_B)] - (&(dev_priv)->__info)
->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info
)->display.mmio_offset) + (0x70008)) })) & PIPECONF_ENABLE((u32)((1UL << (31)) + 0));
1053}
1054
1055static void i830_pipes_power_well_sync_hw(struct drm_i915_privateinteldrm_softc *dev_priv,
1056 struct i915_power_well *power_well)
1057{
1058 if (intel_power_well_refcount(power_well) > 0)
1059 i830_pipes_power_well_enable(dev_priv, power_well);
1060 else
1061 i830_pipes_power_well_disable(dev_priv, power_well);
1062}
1063
1064static void vlv_set_power_well(struct drm_i915_privateinteldrm_softc *dev_priv,
1065 struct i915_power_well *power_well, bool_Bool enable)
1066{
1067 int pw_idx = i915_power_well_instance(power_well)->vlv.idx;
1068 u32 mask;
1069 u32 state;
1070 u32 ctrl;
1071
1072 mask = PUNIT_PWRGT_MASK(pw_idx)(3 << ((pw_idx) * 2));
1073 state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx)(0 << ((pw_idx) * 2)) :
1074 PUNIT_PWRGT_PWR_GATE(pw_idx)(3 << ((pw_idx) * 2));
1075
1076 vlv_punit_get(dev_priv);
1077
1078#define COND \
1079 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS0x61) & mask) == state)
1080
1081 if (COND)
1082 goto out;
1083
1084 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL0x60);
1085 ctrl &= ~mask;
1086 ctrl |= state;
1087 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL0x60, ctrl);
1088
1089 if (wait_for(COND, 100)({ const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll
* (((100) * 1000))); long wait__ = ((10)); int ret__; assertwaitok
(); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw
(), end__); ; __asm volatile("" : : : "memory"); if (((COND))
) { ret__ = 0; break; } if (expired__) { ret__ = -60; break; }
usleep_range(wait__, wait__ * 2); if (wait__ < ((1000))) wait__
<<= 1; } ret__; }))
1090 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "timeout setting power well state %08x (%08x)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , state,
vlv_punit_read(dev_priv, 0x60))
1091 "timeout setting power well state %08x (%08x)\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "timeout setting power well state %08x (%08x)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , state,
vlv_punit_read(dev_priv, 0x60))
1092 state,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "timeout setting power well state %08x (%08x)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , state,
vlv_punit_read(dev_priv, 0x60))
1093 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL))printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "timeout setting power well state %08x (%08x)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , state,
vlv_punit_read(dev_priv, 0x60));
1094
1095#undef COND
1096
1097out:
1098 vlv_punit_put(dev_priv);
1099}
1100
1101static void vlv_power_well_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
1102 struct i915_power_well *power_well)
1103{
1104 vlv_set_power_well(dev_priv, power_well, true1);
1105}
1106
1107static void vlv_power_well_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
1108 struct i915_power_well *power_well)
1109{
1110 vlv_set_power_well(dev_priv, power_well, false0);
1111}
1112
1113static bool_Bool vlv_power_well_enabled(struct drm_i915_privateinteldrm_softc *dev_priv,
1114 struct i915_power_well *power_well)
1115{
1116 int pw_idx = i915_power_well_instance(power_well)->vlv.idx;
1117 bool_Bool enabled = false0;
1118 u32 mask;
1119 u32 state;
1120 u32 ctrl;
1121
1122 mask = PUNIT_PWRGT_MASK(pw_idx)(3 << ((pw_idx) * 2));
1123 ctrl = PUNIT_PWRGT_PWR_ON(pw_idx)(0 << ((pw_idx) * 2));
1124
1125 vlv_punit_get(dev_priv);
1126
1127 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS0x61) & mask;
1128 /*
1129 * We only ever set the power-on and power-gate states, anything
1130 * else is unexpected.
1131 */
1132 drm_WARN_ON(&dev_priv->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) &&({ int __ret = !!((state != (0 << ((pw_idx) * 2)) &&
state != (3 << ((pw_idx) * 2)))); if (__ret) printf("%s %s: "
"%s", dev_driver_string(((&dev_priv->drm))->dev), ""
, "drm_WARN_ON(" "state != (0 << ((pw_idx) * 2)) && state != (3 << ((pw_idx) * 2))"
")"); __builtin_expect(!!(__ret), 0); })
1133 state != PUNIT_PWRGT_PWR_GATE(pw_idx))({ int __ret = !!((state != (0 << ((pw_idx) * 2)) &&
state != (3 << ((pw_idx) * 2)))); if (__ret) printf("%s %s: "
"%s", dev_driver_string(((&dev_priv->drm))->dev), ""
, "drm_WARN_ON(" "state != (0 << ((pw_idx) * 2)) && state != (3 << ((pw_idx) * 2))"
")"); __builtin_expect(!!(__ret), 0); });
1134 if (state == ctrl)
1135 enabled = true1;
1136
1137 /*
1138 * A transient state at this point would mean some unexpected party
1139 * is poking at the power controls too.
1140 */
1141 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL0x60) & mask;
1142 drm_WARN_ON(&dev_priv->drm, ctrl != state)({ int __ret = !!((ctrl != state)); if (__ret) printf("%s %s: "
"%s", dev_driver_string(((&dev_priv->drm))->dev), ""
, "drm_WARN_ON(" "ctrl != state" ")"); __builtin_expect(!!(__ret
), 0); });
1143
1144 vlv_punit_put(dev_priv);
1145
1146 return enabled;
1147}
1148
1149static void vlv_init_display_clock_gating(struct drm_i915_privateinteldrm_softc *dev_priv)
1150{
1151 u32 val;
1152
1153 /*
1154 * On driver load, a pipe may be active and driving a DSI display.
1155 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck
1156 * (and never recovering) in this case. intel_dsi_post_disable() will
1157 * clear it when we turn off the display.
1158 */
1159 val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display.mmio_offset) + 0x6200) }));
1160 val &= DPOUNIT_CLOCK_GATE_DISABLE(1 << 11);
1161 val |= VRHUNIT_CLOCK_GATE_DISABLE(1 << 28);
1162 intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display.mmio_offset) + 0x6200) }), val);
1163
1164 /*
1165 * Disable trickle feed and enable pnd deadline calculation
1166 */
1167 intel_de_write(dev_priv, MI_ARB_VLV((const i915_reg_t){ .reg = (0x180000 + 0x6504) }),
1168 MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE(1 << 2));
1169 intel_de_write(dev_priv, CBR1_VLV((const i915_reg_t){ .reg = (0x180000 + 0x70400) }), 0);
1170
1171 drm_WARN_ON(&dev_priv->drm, RUNTIME_INFO(dev_priv)->rawclk_freq == 0)({ int __ret = !!(((&(dev_priv)->__runtime)->rawclk_freq
== 0)); if (__ret) printf("%s %s: " "%s", dev_driver_string(
((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "(&(dev_priv)->__runtime)->rawclk_freq == 0"
")"); __builtin_expect(!!(__ret), 0); });
1172 intel_de_write(dev_priv, RAWCLK_FREQ_VLV((const i915_reg_t){ .reg = (0x180000 + 0x6024) }),
1173 DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq,((((&(dev_priv)->__runtime)->rawclk_freq) + ((1000)
/ 2)) / (1000))
1174 1000)((((&(dev_priv)->__runtime)->rawclk_freq) + ((1000)
/ 2)) / (1000)));
1175}
1176
1177static void vlv_display_power_well_init(struct drm_i915_privateinteldrm_softc *dev_priv)
1178{
1179 struct intel_encoder *encoder;
1180 enum pipe pipe;
1181
1182 /*
1183 * Enable the CRI clock source so we can get at the
1184 * display and the reference clock for VGA
1185 * hotplug / manual detection. Supposedly DSI also
1186 * needs the ref clock up and running.
1187 *
1188 * CHV DPLL B/C have some issues if VGA mode is enabled.
1189 */
1190 for_each_pipe(dev_priv, pipe)for ((pipe) = 0; (pipe) < I915_MAX_PIPES; (pipe)++) if (!(
(&(dev_priv)->__runtime)->pipe_mask & (1UL <<
(pipe)))) {} else {
1191 u32 val = intel_de_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv
)->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv
)->__info)->display.mmio_offset) + 0x6030) })[(pipe)]))
}));
1192
1193 val |= DPLL_REF_CLK_ENABLE_VLV(1 << 29) | DPLL_VGA_MODE_DIS(1 << 28);
1194 if (pipe != PIPE_A)
1195 val |= DPLL_INTEGRATED_CRI_CLK_VLV(1 << 14);
1196
1197 intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv
)->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv
)->__info)->display.mmio_offset) + 0x6030) })[(pipe)]))
}), val);
1198 }
1199
1200 vlv_init_display_clock_gating(dev_priv);
1201
1202 spin_lock_irq(&dev_priv->irq_lock)mtx_enter(&dev_priv->irq_lock);
1203 valleyview_enable_display_irqs(dev_priv);
1204 spin_unlock_irq(&dev_priv->irq_lock)mtx_leave(&dev_priv->irq_lock);
1205
1206 /*
1207 * During driver initialization/resume we can avoid restoring the
1208 * part of the HW/SW state that will be inited anyway explicitly.
1209 */
1210 if (dev_priv->display.power.domains.initializing)
1211 return;
1212
1213 intel_hpd_init(dev_priv);
1214 intel_hpd_poll_disable(dev_priv);
1215
1216 /* Re-enable the ADPA, if we have one */
1217 for_each_intel_encoder(&dev_priv->drm, encoder)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)->
base.head ) *__mptr = ((&(&dev_priv->drm)->mode_config
.encoder_list)->next); (__typeof(*encoder) *)( (char *)__mptr
- __builtin_offsetof(__typeof(*encoder), base.head) );}); &
encoder->base.head != (&(&dev_priv->drm)->mode_config
.encoder_list); encoder = ({ const __typeof( ((__typeof(*encoder
) *)0)->base.head ) *__mptr = (encoder->base.head.next)
; (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*encoder), base.head) );})) {
1218 if (encoder->type == INTEL_OUTPUT_ANALOG)
1219 intel_crt_reset(&encoder->base);
1220 }
1221
1222 intel_vga_redisable_power_on(dev_priv);
1223
1224 intel_pps_unlock_regs_wa(dev_priv);
1225}
1226
1227static void vlv_display_power_well_deinit(struct drm_i915_privateinteldrm_softc *dev_priv)
1228{
1229 spin_lock_irq(&dev_priv->irq_lock)mtx_enter(&dev_priv->irq_lock);
1230 valleyview_disable_display_irqs(dev_priv);
1231 spin_unlock_irq(&dev_priv->irq_lock)mtx_leave(&dev_priv->irq_lock);
1232
1233 /* make sure we're done processing display irqs */
1234 intel_synchronize_irq(dev_priv);
1235
1236 intel_pps_reset_all(dev_priv);
1237
1238 /* Prevent us from re-enabling polling on accident in late suspend */
1239#ifdef __linux__
1240 if (!dev_priv->drm.dev->power.is_suspended)
1241#else
1242 if (!cold)
1243#endif
1244 intel_hpd_poll_enable(dev_priv);
1245}
1246
1247static void vlv_display_power_well_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
1248 struct i915_power_well *power_well)
1249{
1250 vlv_set_power_well(dev_priv, power_well, true1);
1251
1252 vlv_display_power_well_init(dev_priv);
1253}
1254
1255static void vlv_display_power_well_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
1256 struct i915_power_well *power_well)
1257{
1258 vlv_display_power_well_deinit(dev_priv);
1259
1260 vlv_set_power_well(dev_priv, power_well, false0);
1261}
1262
1263static void vlv_dpio_cmn_power_well_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
1264 struct i915_power_well *power_well)
1265{
1266 /* since ref/cri clock was enabled */
1267 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1268
1269 vlv_set_power_well(dev_priv, power_well, true1);
1270
1271 /*
1272 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1273 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1274 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1275 * b. The other bits such as sfr settings / modesel may all
1276 * be set to 0.
1277 *
1278 * This should only be done on init and resume from S3 with
1279 * both PLLs disabled, or we risk losing DPIO and PLL
1280 * synchronization.
1281 */
1282 intel_de_write(dev_priv, DPIO_CTL((const i915_reg_t){ .reg = (0x180000 + 0x2110) }),
1283 intel_de_read(dev_priv, DPIO_CTL((const i915_reg_t){ .reg = (0x180000 + 0x2110) })) | DPIO_CMNRST(1 << 0));
1284}
1285
1286static void vlv_dpio_cmn_power_well_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
1287 struct i915_power_well *power_well)
1288{
1289 enum pipe pipe;
1290
1291 for_each_pipe(dev_priv, pipe)for ((pipe) = 0; (pipe) < I915_MAX_PIPES; (pipe)++) if (!(
(&(dev_priv)->__runtime)->pipe_mask & (1UL <<
(pipe)))) {} else
1292 assert_pll_disabled(dev_priv, pipe);
1293
1294 /* Assert common reset */
1295 intel_de_write(dev_priv, DPIO_CTL((const i915_reg_t){ .reg = (0x180000 + 0x2110) }),
1296 intel_de_read(dev_priv, DPIO_CTL((const i915_reg_t){ .reg = (0x180000 + 0x2110) })) & ~DPIO_CMNRST(1 << 0));
1297
1298 vlv_set_power_well(dev_priv, power_well, false0);
1299}
1300
1301#define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1302
1303static void assert_chv_phy_status(struct drm_i915_privateinteldrm_softc *dev_priv)
1304{
1305 struct i915_power_well *cmn_bc =
1306 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
1307 struct i915_power_well *cmn_d =
1308 lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
1309 u32 phy_control = dev_priv->display.power.chv_phy_control;
1310 u32 phy_status = 0;
1311 u32 phy_status_mask = 0xffffffff;
1312
1313 /*
1314 * The BIOS can leave the PHY is some weird state
1315 * where it doesn't fully power down some parts.
1316 * Disable the asserts until the PHY has been fully
1317 * reset (ie. the power well has been disabled at
1318 * least once).
1319 */
1320 if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY0])
1321 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0)(1 << (6 - (6 * (DPIO_PHY0) + 3 * (DPIO_CH0)))) |
1322 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0)(1 << (8 - (6 * (DPIO_PHY0) + 3 * (DPIO_CH0) + (0)))) |
1323 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1)(1 << (8 - (6 * (DPIO_PHY0) + 3 * (DPIO_CH0) + (1)))) |
1324 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1)(1 << (6 - (6 * (DPIO_PHY0) + 3 * (DPIO_CH1)))) |
1325 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0)(1 << (8 - (6 * (DPIO_PHY0) + 3 * (DPIO_CH1) + (0)))) |
1326 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)(1 << (8 - (6 * (DPIO_PHY0) + 3 * (DPIO_CH1) + (1)))));
1327
1328 if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY1])
1329 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0)(1 << (6 - (6 * (DPIO_PHY1) + 3 * (DPIO_CH0)))) |
1330 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0)(1 << (8 - (6 * (DPIO_PHY1) + 3 * (DPIO_CH0) + (0)))) |
1331 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)(1 << (8 - (6 * (DPIO_PHY1) + 3 * (DPIO_CH0) + (1)))));
1332
1333 if (intel_power_well_is_enabled(dev_priv, cmn_bc)) {
1334 phy_status |= PHY_POWERGOOD(DPIO_PHY0)(((DPIO_PHY0) == DPIO_PHY0) ? (1 << 31) : (1 << 30
));
1335
1336 /* this assumes override is only used to enable lanes */
1337 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)(1 << (2 * (DPIO_PHY0) + (DPIO_CH0) + 27))) == 0)
1338 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0)((0xf) << (8 * (DPIO_PHY0) + 4 * (DPIO_CH0) + 11));
1339
1340 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)(1 << (2 * (DPIO_PHY0) + (DPIO_CH1) + 27))) == 0)
1341 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)((0xf) << (8 * (DPIO_PHY0) + 4 * (DPIO_CH1) + 11));
1342
1343 /* CL1 is on whenever anything is on in either channel */
1344 if (BITS_SET(phy_control,
1345 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0)((0xf) << (8 * (DPIO_PHY0) + 4 * (DPIO_CH0) + 11)) |
1346 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)((0xf) << (8 * (DPIO_PHY0) + 4 * (DPIO_CH1) + 11))))
1347 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0)(1 << (6 - (6 * (DPIO_PHY0) + 3 * (DPIO_CH0))));
1348
1349 /*
1350 * The DPLLB check accounts for the pipe B + port A usage
1351 * with CL2 powered up but all the lanes in the second channel
1352 * powered down.
1353 */
1354 if (BITS_SET(phy_control,
1355 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)((0xf) << (8 * (DPIO_PHY0) + 4 * (DPIO_CH1) + 11))) &&
1356 (intel_de_read(dev_priv, DPLL(PIPE_B)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv
)->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv
)->__info)->display.mmio_offset) + 0x6030) })[(PIPE_B)]
)) })) & DPLL_VCO_ENABLE(1 << 31)) == 0)
1357 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1)(1 << (6 - (6 * (DPIO_PHY0) + 3 * (DPIO_CH1))));
1358
1359 if (BITS_SET(phy_control,
1360 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)((0x3) << (8 * (DPIO_PHY0) + 4 * (DPIO_CH0) + 11))))
1361 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0)(1 << (8 - (6 * (DPIO_PHY0) + 3 * (DPIO_CH0) + (0))));
1362 if (BITS_SET(phy_control,
1363 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)((0xc) << (8 * (DPIO_PHY0) + 4 * (DPIO_CH0) + 11))))
1364 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1)(1 << (8 - (6 * (DPIO_PHY0) + 3 * (DPIO_CH0) + (1))));
1365
1366 if (BITS_SET(phy_control,
1367 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)((0x3) << (8 * (DPIO_PHY0) + 4 * (DPIO_CH1) + 11))))
1368 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0)(1 << (8 - (6 * (DPIO_PHY0) + 3 * (DPIO_CH1) + (0))));
1369 if (BITS_SET(phy_control,
1370 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)((0xc) << (8 * (DPIO_PHY0) + 4 * (DPIO_CH1) + 11))))
1371 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)(1 << (8 - (6 * (DPIO_PHY0) + 3 * (DPIO_CH1) + (1))));
1372 }
1373
1374 if (intel_power_well_is_enabled(dev_priv, cmn_d)) {
1375 phy_status |= PHY_POWERGOOD(DPIO_PHY1)(((DPIO_PHY1) == DPIO_PHY0) ? (1 << 31) : (1 << 30
));
1376
1377 /* this assumes override is only used to enable lanes */
1378 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)(1 << (2 * (DPIO_PHY1) + (DPIO_CH0) + 27))) == 0)
1379 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)((0xf) << (8 * (DPIO_PHY1) + 4 * (DPIO_CH0) + 11));
1380
1381 if (BITS_SET(phy_control,
1382 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)((0xf) << (8 * (DPIO_PHY1) + 4 * (DPIO_CH0) + 11))))
1383 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0)(1 << (6 - (6 * (DPIO_PHY1) + 3 * (DPIO_CH0))));
1384
1385 if (BITS_SET(phy_control,
1386 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)((0x3) << (8 * (DPIO_PHY1) + 4 * (DPIO_CH0) + 11))))
1387 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0)(1 << (8 - (6 * (DPIO_PHY1) + 3 * (DPIO_CH0) + (0))));
1388 if (BITS_SET(phy_control,
1389 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)((0xc) << (8 * (DPIO_PHY1) + 4 * (DPIO_CH0) + 11))))
1390 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)(1 << (8 - (6 * (DPIO_PHY1) + 3 * (DPIO_CH0) + (1))));
1391 }
1392
1393 phy_status &= phy_status_mask;
1394
1395 /*
1396 * The PHY may be busy with some initial calibration and whatnot,
1397 * so the power state can take a while to actually change.
1398 */
1399 if (intel_de_wait_for_register(dev_priv, DISPLAY_PHY_STATUS((const i915_reg_t){ .reg = (0x180000 + 0x60104) }),
1400 phy_status_mask, phy_status, 10))
1401 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , intel_de_read
(dev_priv, ((const i915_reg_t){ .reg = (0x180000 + 0x60104) }
)) & phy_status_mask, phy_status, dev_priv->display.power
.chv_phy_control)
1402 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , intel_de_read
(dev_priv, ((const i915_reg_t){ .reg = (0x180000 + 0x60104) }
)) & phy_status_mask, phy_status, dev_priv->display.power
.chv_phy_control)
1403 intel_de_read(dev_priv, DISPLAY_PHY_STATUS) & phy_status_mask,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , intel_de_read
(dev_priv, ((const i915_reg_t){ .reg = (0x180000 + 0x60104) }
)) & phy_status_mask, phy_status, dev_priv->display.power
.chv_phy_control)
1404 phy_status, dev_priv->display.power.chv_phy_control)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , intel_de_read
(dev_priv, ((const i915_reg_t){ .reg = (0x180000 + 0x60104) }
)) & phy_status_mask, phy_status, dev_priv->display.power
.chv_phy_control);
1405}
1406
1407#undef BITS_SET
1408
1409static void chv_dpio_cmn_power_well_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
1410 struct i915_power_well *power_well)
1411{
1412 enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
1413 enum dpio_phy phy;
1414 enum pipe pipe;
1415 u32 tmp;
1416
1417 drm_WARN_ON_ONCE(&dev_priv->drm,({ static int __warned; int __ret = !!((id != VLV_DISP_PW_DPIO_CMN_BC
&& id != CHV_DISP_PW_DPIO_CMN_D)); if (__ret &&
!__warned) { printf("%s %s: " "%s", dev_driver_string(((&
dev_priv->drm))->dev), "", "drm_WARN_ON_ONCE(" "id != VLV_DISP_PW_DPIO_CMN_BC && id != CHV_DISP_PW_DPIO_CMN_D"
")"); __warned = 1; } __builtin_expect(!!(__ret), 0); })
1418 id != VLV_DISP_PW_DPIO_CMN_BC &&({ static int __warned; int __ret = !!((id != VLV_DISP_PW_DPIO_CMN_BC
&& id != CHV_DISP_PW_DPIO_CMN_D)); if (__ret &&
!__warned) { printf("%s %s: " "%s", dev_driver_string(((&
dev_priv->drm))->dev), "", "drm_WARN_ON_ONCE(" "id != VLV_DISP_PW_DPIO_CMN_BC && id != CHV_DISP_PW_DPIO_CMN_D"
")"); __warned = 1; } __builtin_expect(!!(__ret), 0); })
1419 id != CHV_DISP_PW_DPIO_CMN_D)({ static int __warned; int __ret = !!((id != VLV_DISP_PW_DPIO_CMN_BC
&& id != CHV_DISP_PW_DPIO_CMN_D)); if (__ret &&
!__warned) { printf("%s %s: " "%s", dev_driver_string(((&
dev_priv->drm))->dev), "", "drm_WARN_ON_ONCE(" "id != VLV_DISP_PW_DPIO_CMN_BC && id != CHV_DISP_PW_DPIO_CMN_D"
")"); __warned = 1; } __builtin_expect(!!(__ret), 0); });
1420
1421 if (id == VLV_DISP_PW_DPIO_CMN_BC) {
1422 pipe = PIPE_A;
1423 phy = DPIO_PHY0;
1424 } else {
1425 pipe = PIPE_C;
1426 phy = DPIO_PHY1;
1427 }
1428
1429 /* since ref/cri clock was enabled */
1430 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1431 vlv_set_power_well(dev_priv, power_well, true1);
1432
1433 /* Poll for phypwrgood signal */
1434 if (intel_de_wait_for_set(dev_priv, DISPLAY_PHY_STATUS((const i915_reg_t){ .reg = (0x180000 + 0x60104) }),
1435 PHY_POWERGOOD(phy)(((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30)), 1))
1436 drm_err(&dev_priv->drm, "Display PHY %d is not power up\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Display PHY %d is not power up\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , phy)
1437 phy)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Display PHY %d is not power up\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , phy);
1438
1439 vlv_dpio_get(dev_priv);
1440
1441 /* Enable dynamic power down */
1442 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW280x8170);
1443 tmp |= DPIO_DYNPWRDOWNEN_CH0(1 << 22) | DPIO_CL1POWERDOWNEN(1 << 23) |
1444 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ(3 << 0);
1445 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW280x8170, tmp);
1446
1447 if (id == VLV_DISP_PW_DPIO_CMN_BC) {
1448 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH10x8098);
1449 tmp |= DPIO_DYNPWRDOWNEN_CH1(1 << 28);
1450 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH10x8098, tmp);
1451 } else {
1452 /*
1453 * Force the non-existing CL2 off. BXT does this
1454 * too, so maybe it saves some power even though
1455 * CL2 doesn't exist?
1456 */
1457 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW300x8178);
1458 tmp |= DPIO_CL2_LDOFUSE_PWRENB(1 << 6);
1459 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW300x8178, tmp);
1460 }
1461
1462 vlv_dpio_put(dev_priv);
1463
1464 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy)(1 << (phy));
1465 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL((const i915_reg_t){ .reg = (0x180000 + 0x60100) }),
1466 dev_priv->display.power.chv_phy_control);
1467
1468 drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n"
, phy, dev_priv->display.power.chv_phy_control)
1469 "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n"
, phy, dev_priv->display.power.chv_phy_control)
1470 phy, dev_priv->display.power.chv_phy_control)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n"
, phy, dev_priv->display.power.chv_phy_control);
1471
1472 assert_chv_phy_status(dev_priv);
1473}
1474
1475static void chv_dpio_cmn_power_well_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
1476 struct i915_power_well *power_well)
1477{
1478 enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
1479 enum dpio_phy phy;
1480
1481 drm_WARN_ON_ONCE(&dev_priv->drm,({ static int __warned; int __ret = !!((id != VLV_DISP_PW_DPIO_CMN_BC
&& id != CHV_DISP_PW_DPIO_CMN_D)); if (__ret &&
!__warned) { printf("%s %s: " "%s", dev_driver_string(((&
dev_priv->drm))->dev), "", "drm_WARN_ON_ONCE(" "id != VLV_DISP_PW_DPIO_CMN_BC && id != CHV_DISP_PW_DPIO_CMN_D"
")"); __warned = 1; } __builtin_expect(!!(__ret), 0); })
1482 id != VLV_DISP_PW_DPIO_CMN_BC &&({ static int __warned; int __ret = !!((id != VLV_DISP_PW_DPIO_CMN_BC
&& id != CHV_DISP_PW_DPIO_CMN_D)); if (__ret &&
!__warned) { printf("%s %s: " "%s", dev_driver_string(((&
dev_priv->drm))->dev), "", "drm_WARN_ON_ONCE(" "id != VLV_DISP_PW_DPIO_CMN_BC && id != CHV_DISP_PW_DPIO_CMN_D"
")"); __warned = 1; } __builtin_expect(!!(__ret), 0); })
1483 id != CHV_DISP_PW_DPIO_CMN_D)({ static int __warned; int __ret = !!((id != VLV_DISP_PW_DPIO_CMN_BC
&& id != CHV_DISP_PW_DPIO_CMN_D)); if (__ret &&
!__warned) { printf("%s %s: " "%s", dev_driver_string(((&
dev_priv->drm))->dev), "", "drm_WARN_ON_ONCE(" "id != VLV_DISP_PW_DPIO_CMN_BC && id != CHV_DISP_PW_DPIO_CMN_D"
")"); __warned = 1; } __builtin_expect(!!(__ret), 0); });
1484
1485 if (id == VLV_DISP_PW_DPIO_CMN_BC) {
1486 phy = DPIO_PHY0;
1487 assert_pll_disabled(dev_priv, PIPE_A);
1488 assert_pll_disabled(dev_priv, PIPE_B);
1489 } else {
1490 phy = DPIO_PHY1;
1491 assert_pll_disabled(dev_priv, PIPE_C);
1492 }
1493
1494 dev_priv->display.power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy)(1 << (phy));
1495 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL((const i915_reg_t){ .reg = (0x180000 + 0x60100) }),
1496 dev_priv->display.power.chv_phy_control);
1497
1498 vlv_set_power_well(dev_priv, power_well, false0);
1499
1500 drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n"
, phy, dev_priv->display.power.chv_phy_control)
1501 "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n"
, phy, dev_priv->display.power.chv_phy_control)
1502 phy, dev_priv->display.power.chv_phy_control)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n"
, phy, dev_priv->display.power.chv_phy_control);
1503
1504 /* PHY is fully reset now, so we can enable the PHY state asserts */
1505 dev_priv->display.power.chv_phy_assert[phy] = true1;
1506
1507 assert_chv_phy_status(dev_priv);
1508}
1509
1510static void assert_chv_phy_powergate(struct drm_i915_privateinteldrm_softc *dev_priv, enum dpio_phy phy,
1511 enum dpio_channel ch, bool_Bool override, unsigned int mask)
1512{
1513 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1514 u32 reg, val, expected, actual;
1515
1516 /*
1517 * The BIOS can leave the PHY is some weird state
1518 * where it doesn't fully power down some parts.
1519 * Disable the asserts until the PHY has been fully
1520 * reset (ie. the power well has been disabled at
1521 * least once).
1522 */
1523 if (!dev_priv->display.power.chv_phy_assert[phy])
1524 return;
1525
1526 if (ch == DPIO_CH0)
1527 reg = _CHV_CMN_DW0_CH00x8100;
1528 else
1529 reg = _CHV_CMN_DW6_CH10x8098;
1530
1531 vlv_dpio_get(dev_priv);
1532 val = vlv_dpio_read(dev_priv, pipe, reg);
1533 vlv_dpio_put(dev_priv);
1534
1535 /*
1536 * This assumes !override is only used when the port is disabled.
1537 * All lanes should power down even without the override when
1538 * the port is disabled.
1539 */
1540 if (!override || mask == 0xf) {
1541 expected = DPIO_ALLDL_POWERDOWN(1 << 1) | DPIO_ANYDL_POWERDOWN(1 << 0);
1542 /*
1543 * If CH1 common lane is not active anymore
1544 * (eg. for pipe B DPLL) the entire channel will
1545 * shut down, which causes the common lane registers
1546 * to read as 0. That means we can't actually check
1547 * the lane power down status bits, but as the entire
1548 * register reads as 0 it's a good indication that the
1549 * channel is indeed entirely powered down.
1550 */
1551 if (ch == DPIO_CH1 && val == 0)
1552 expected = 0;
1553 } else if (mask != 0x0) {
1554 expected = DPIO_ANYDL_POWERDOWN(1 << 0);
1555 } else {
1556 expected = 0;
1557 }
1558
1559 if (ch == DPIO_CH0)
1560 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH018;
1561 else
1562 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH129;
1563 actual &= DPIO_ALLDL_POWERDOWN(1 << 1) | DPIO_ANYDL_POWERDOWN(1 << 0);
1564
1565 drm_WARN(&dev_priv->drm, actual != expected,({ int __ret = !!(actual != expected); if (__ret) printf("%s %s: "
"Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n"
, dev_driver_string((&dev_priv->drm)->dev), "", !!(
actual & (1 << 1)), !!(actual & (1 << 0))
, !!(expected & (1 << 1)), !!(expected & (1 <<
0)), reg, val); __builtin_expect(!!(__ret), 0); })
1566 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",({ int __ret = !!(actual != expected); if (__ret) printf("%s %s: "
"Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n"
, dev_driver_string((&dev_priv->drm)->dev), "", !!(
actual & (1 << 1)), !!(actual & (1 << 0))
, !!(expected & (1 << 1)), !!(expected & (1 <<
0)), reg, val); __builtin_expect(!!(__ret), 0); })
1567 !!(actual & DPIO_ALLDL_POWERDOWN),({ int __ret = !!(actual != expected); if (__ret) printf("%s %s: "
"Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n"
, dev_driver_string((&dev_priv->drm)->dev), "", !!(
actual & (1 << 1)), !!(actual & (1 << 0))
, !!(expected & (1 << 1)), !!(expected & (1 <<
0)), reg, val); __builtin_expect(!!(__ret), 0); })
1568 !!(actual & DPIO_ANYDL_POWERDOWN),({ int __ret = !!(actual != expected); if (__ret) printf("%s %s: "
"Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n"
, dev_driver_string((&dev_priv->drm)->dev), "", !!(
actual & (1 << 1)), !!(actual & (1 << 0))
, !!(expected & (1 << 1)), !!(expected & (1 <<
0)), reg, val); __builtin_expect(!!(__ret), 0); })
1569 !!(expected & DPIO_ALLDL_POWERDOWN),({ int __ret = !!(actual != expected); if (__ret) printf("%s %s: "
"Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n"
, dev_driver_string((&dev_priv->drm)->dev), "", !!(
actual & (1 << 1)), !!(actual & (1 << 0))
, !!(expected & (1 << 1)), !!(expected & (1 <<
0)), reg, val); __builtin_expect(!!(__ret), 0); })
1570 !!(expected & DPIO_ANYDL_POWERDOWN),({ int __ret = !!(actual != expected); if (__ret) printf("%s %s: "
"Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n"
, dev_driver_string((&dev_priv->drm)->dev), "", !!(
actual & (1 << 1)), !!(actual & (1 << 0))
, !!(expected & (1 << 1)), !!(expected & (1 <<
0)), reg, val); __builtin_expect(!!(__ret), 0); })
1571 reg, val)({ int __ret = !!(actual != expected); if (__ret) printf("%s %s: "
"Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n"
, dev_driver_string((&dev_priv->drm)->dev), "", !!(
actual & (1 << 1)), !!(actual & (1 << 0))
, !!(expected & (1 << 1)), !!(expected & (1 <<
0)), reg, val); __builtin_expect(!!(__ret), 0); });
1572}
1573
1574bool_Bool chv_phy_powergate_ch(struct drm_i915_privateinteldrm_softc *dev_priv, enum dpio_phy phy,
1575 enum dpio_channel ch, bool_Bool override)
1576{
1577 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1578 bool_Bool was_override;
1579
1580 mutex_lock(&power_domains->lock)rw_enter_write(&power_domains->lock);
1581
1582 was_override = dev_priv->display.power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch)(1 << (2 * (phy) + (ch) + 27));
1583
1584 if (override == was_override)
1585 goto out;
1586
1587 if (override)
1588 dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch)(1 << (2 * (phy) + (ch) + 27));
1589 else
1590 dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch)(1 << (2 * (phy) + (ch) + 27));
1591
1592 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL((const i915_reg_t){ .reg = (0x180000 + 0x60100) }),
1593 dev_priv->display.power.chv_phy_control);
1594
1595 drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n"
, phy, ch, dev_priv->display.power.chv_phy_control)
1596 "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n"
, phy, ch, dev_priv->display.power.chv_phy_control)
1597 phy, ch, dev_priv->display.power.chv_phy_control)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n"
, phy, ch, dev_priv->display.power.chv_phy_control);
1598
1599 assert_chv_phy_status(dev_priv);
1600
1601out:
1602 mutex_unlock(&power_domains->lock)rw_exit_write(&power_domains->lock);
1603
1604 return was_override;
1605}
1606
1607void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1608 bool_Bool override, unsigned int mask)
1609{
1610 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
1611 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1612 enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder));
1613 enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));
1614
1615 mutex_lock(&power_domains->lock)rw_enter_write(&power_domains->lock);
1616
1617 dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch)((0xf) << (8 * (phy) + 4 * (ch) + 11));
1618 dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch)((mask) << (8 * (phy) + 4 * (ch) + 11));
1619
1620 if (override)
1621 dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch)(1 << (2 * (phy) + (ch) + 27));
1622 else
1623 dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch)(1 << (2 * (phy) + (ch) + 27));
1624
1625 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL((const i915_reg_t){ .reg = (0x180000 + 0x60100) }),
1626 dev_priv->display.power.chv_phy_control);
1627
1628 drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n"
, phy, ch, mask, dev_priv->display.power.chv_phy_control)
1629 "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n"
, phy, ch, mask, dev_priv->display.power.chv_phy_control)
1630 phy, ch, mask, dev_priv->display.power.chv_phy_control)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n"
, phy, ch, mask, dev_priv->display.power.chv_phy_control);
1631
1632 assert_chv_phy_status(dev_priv);
1633
1634 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1635
1636 mutex_unlock(&power_domains->lock)rw_exit_write(&power_domains->lock);
1637}
1638
1639static bool_Bool chv_pipe_power_well_enabled(struct drm_i915_privateinteldrm_softc *dev_priv,
1640 struct i915_power_well *power_well)
1641{
1642 enum pipe pipe = PIPE_A;
1643 bool_Bool enabled;
1644 u32 state, ctrl;
1645
1646 vlv_punit_get(dev_priv);
1647
1648 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM0x36) & DP_SSS_MASK(pipe)((0x3) << (2 * ((pipe)) + 16));
1649 /*
1650 * We only ever set the power-on and power-gate states, anything
1651 * else is unexpected.
1652 */
1653 drm_WARN_ON(&dev_priv->drm, state != DP_SSS_PWR_ON(pipe) &&({ int __ret = !!((state != ((0x0) << (2 * ((pipe)) + 16
)) && state != ((0x3) << (2 * ((pipe)) + 16))))
; if (__ret) printf("%s %s: " "%s", dev_driver_string(((&
dev_priv->drm))->dev), "", "drm_WARN_ON(" "state != ((0x0) << (2 * ((pipe)) + 16)) && state != ((0x3) << (2 * ((pipe)) + 16))"
")"); __builtin_expect(!!(__ret), 0); })
1654 state != DP_SSS_PWR_GATE(pipe))({ int __ret = !!((state != ((0x0) << (2 * ((pipe)) + 16
)) && state != ((0x3) << (2 * ((pipe)) + 16))))
; if (__ret) printf("%s %s: " "%s", dev_driver_string(((&
dev_priv->drm))->dev), "", "drm_WARN_ON(" "state != ((0x0) << (2 * ((pipe)) + 16)) && state != ((0x3) << (2 * ((pipe)) + 16))"
")"); __builtin_expect(!!(__ret), 0); });
1655 enabled = state == DP_SSS_PWR_ON(pipe)((0x0) << (2 * ((pipe)) + 16));
1656
1657 /*
1658 * A transient state at this point would mean some unexpected party
1659 * is poking at the power controls too.
1660 */
1661 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM0x36) & DP_SSC_MASK(pipe)((0x3) << (2 * ((pipe))));
1662 drm_WARN_ON(&dev_priv->drm, ctrl << 16 != state)({ int __ret = !!((ctrl << 16 != state)); if (__ret) printf
("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->
dev), "", "drm_WARN_ON(" "ctrl << 16 != state" ")"); __builtin_expect
(!!(__ret), 0); });
1663
1664 vlv_punit_put(dev_priv);
1665
1666 return enabled;
1667}
1668
1669static void chv_set_pipe_power_well(struct drm_i915_privateinteldrm_softc *dev_priv,
1670 struct i915_power_well *power_well,
1671 bool_Bool enable)
1672{
1673 enum pipe pipe = PIPE_A;
1674 u32 state;
1675 u32 ctrl;
1676
1677 state = enable ? DP_SSS_PWR_ON(pipe)((0x0) << (2 * ((pipe)) + 16)) : DP_SSS_PWR_GATE(pipe)((0x3) << (2 * ((pipe)) + 16));
1678
1679 vlv_punit_get(dev_priv);
1680
1681#define COND \
1682 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM0x36) & DP_SSS_MASK(pipe)((0x3) << (2 * ((pipe)) + 16))) == state)
1683
1684 if (COND)
1685 goto out;
1686
1687 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM0x36);
1688 ctrl &= ~DP_SSC_MASK(pipe)((0x3) << (2 * ((pipe))));
1689 ctrl |= enable ? DP_SSC_PWR_ON(pipe)((0x0) << (2 * ((pipe)))) : DP_SSC_PWR_GATE(pipe)((0x3) << (2 * ((pipe))));
1690 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM0x36, ctrl);
1691
1692 if (wait_for(COND, 100)({ const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll
* (((100) * 1000))); long wait__ = ((10)); int ret__; assertwaitok
(); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw
(), end__); ; __asm volatile("" : : : "memory"); if (((COND))
) { ret__ = 0; break; } if (expired__) { ret__ = -60; break; }
usleep_range(wait__, wait__ * 2); if (wait__ < ((1000))) wait__
<<= 1; } ret__; }))
1693 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "timeout setting power well state %08x (%08x)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , state,
vlv_punit_read(dev_priv, 0x36))
1694 "timeout setting power well state %08x (%08x)\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "timeout setting power well state %08x (%08x)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , state,
vlv_punit_read(dev_priv, 0x36))
1695 state,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "timeout setting power well state %08x (%08x)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , state,
vlv_punit_read(dev_priv, 0x36))
1696 vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM))printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "timeout setting power well state %08x (%08x)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , state,
vlv_punit_read(dev_priv, 0x36));
1697
1698#undef COND
1699
1700out:
1701 vlv_punit_put(dev_priv);
1702}
1703
1704static void chv_pipe_power_well_sync_hw(struct drm_i915_privateinteldrm_softc *dev_priv,
1705 struct i915_power_well *power_well)
1706{
1707 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL((const i915_reg_t){ .reg = (0x180000 + 0x60100) }),
1708 dev_priv->display.power.chv_phy_control);
1709}
1710
1711static void chv_pipe_power_well_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
1712 struct i915_power_well *power_well)
1713{
1714 chv_set_pipe_power_well(dev_priv, power_well, true1);
1715
1716 vlv_display_power_well_init(dev_priv);
1717}
1718
1719static void chv_pipe_power_well_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
1720 struct i915_power_well *power_well)
1721{
1722 vlv_display_power_well_deinit(dev_priv);
1723
1724 chv_set_pipe_power_well(dev_priv, power_well, false0);
1725}
1726
1727static void
1728tgl_tc_cold_request(struct drm_i915_privateinteldrm_softc *i915, bool_Bool block)
1729{
1730 u8 tries = 0;
1731 int ret;
1732
1733 while (1) {
1734 u32 low_val;
1735 u32 high_val = 0;
1736
1737 if (block)
1738 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ0;
1739 else
1740 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ((u32)((1UL << (0)) + 0));
1741
1742 /*
1743 * Spec states that we should timeout the request after 200us
1744 * but the function below will timeout after 500us
1745 */
1746 ret = snb_pcode_read(&i915->uncore, TGL_PCODE_TCCOLD0x26, &low_val, &high_val);
1747 if (ret == 0) {
1748 if (block &&
1749 (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED((u32)((1UL << (0)) + 0))))
1750 ret = -EIO5;
1751 else
1752 break;
1753 }
1754
1755 if (++tries == 3)
1756 break;
1757
1758 drm_msleep(1)mdelay(1);
1759 }
1760
1761 if (ret)
1762 drm_err(&i915->drm, "TC cold %sblock failed\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "TC cold %sblock failed\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , block ?
"" : "un")
1763 block ? "" : "un")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "TC cold %sblock failed\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , block ?
"" : "un");
1764 else
1765 drm_dbg_kms(&i915->drm, "TC cold %sblock succeeded\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "TC cold %sblock succeeded\n"
, block ? "" : "un")
1766 block ? "" : "un")__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "TC cold %sblock succeeded\n"
, block ? "" : "un");
1767}
1768
1769static void
1770tgl_tc_cold_off_power_well_enable(struct drm_i915_privateinteldrm_softc *i915,
1771 struct i915_power_well *power_well)
1772{
1773 tgl_tc_cold_request(i915, true1);
1774}
1775
1776static void
1777tgl_tc_cold_off_power_well_disable(struct drm_i915_privateinteldrm_softc *i915,
1778 struct i915_power_well *power_well)
1779{
1780 tgl_tc_cold_request(i915, false0);
1781}
1782
1783static void
1784tgl_tc_cold_off_power_well_sync_hw(struct drm_i915_privateinteldrm_softc *i915,
1785 struct i915_power_well *power_well)
1786{
1787 if (intel_power_well_refcount(power_well) > 0)
1788 tgl_tc_cold_off_power_well_enable(i915, power_well);
1789 else
1790 tgl_tc_cold_off_power_well_disable(i915, power_well);
1791}
1792
1793static bool_Bool
1794tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_privateinteldrm_softc *dev_priv,
1795 struct i915_power_well *power_well)
1796{
1797 /*
1798 * Not the correctly implementation but there is no way to just read it
1799 * from PCODE, so returning count to avoid state mismatch errors
1800 */
1801 return intel_power_well_refcount(power_well);
1802}
1803
1804static void xelpdp_aux_power_well_enable(struct drm_i915_privateinteldrm_softc *dev_priv,
1805 struct i915_power_well *power_well)
1806{
1807 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
1808
1809 intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display.mmio_offset) + 0x64010), (((&(dev_priv
)->__info)->display.mmio_offset) + 0x64110), 0, 0x16F210
, 0x16F410, 0x16F610, 0x16F810 })[aux_ch])) }),
1810 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST((u32)((1UL << (19)) + 0)),
1811 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST((u32)((1UL << (19)) + 0)));
1812
1813 /*
1814 * The power status flag cannot be used to determine whether aux
1815 * power wells have finished powering up. Instead we're
1816 * expected to just wait a fixed 600us after raising the request
1817 * bit.
1818 */
1819 usleep_range(600, 1200);
1820}
1821
1822static void xelpdp_aux_power_well_disable(struct drm_i915_privateinteldrm_softc *dev_priv,
1823 struct i915_power_well *power_well)
1824{
1825 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
1826
1827 intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display.mmio_offset) + 0x64010), (((&(dev_priv
)->__info)->display.mmio_offset) + 0x64110), 0, 0x16F210
, 0x16F410, 0x16F610, 0x16F810 })[aux_ch])) }),
1828 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST((u32)((1UL << (19)) + 0)),
1829 0);
1830 usleep_range(10, 30);
1831}
1832
1833static bool_Bool xelpdp_aux_power_well_enabled(struct drm_i915_privateinteldrm_softc *dev_priv,
1834 struct i915_power_well *power_well)
1835{
1836 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
1837
1838 return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display.mmio_offset) + 0x64010), (((&(dev_priv
)->__info)->display.mmio_offset) + 0x64110), 0, 0x16F210
, 0x16F410, 0x16F610, 0x16F810 })[aux_ch])) })) &
1839 XELPDP_DP_AUX_CH_CTL_POWER_STATUS((u32)((1UL << (18)) + 0));
1840}
1841
1842const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1843 .sync_hw = i9xx_power_well_sync_hw_noop,
1844 .enable = i9xx_always_on_power_well_noop,
1845 .disable = i9xx_always_on_power_well_noop,
1846 .is_enabled = i9xx_always_on_power_well_enabled,
1847};
1848
1849const struct i915_power_well_ops chv_pipe_power_well_ops = {
1850 .sync_hw = chv_pipe_power_well_sync_hw,
1851 .enable = chv_pipe_power_well_enable,
1852 .disable = chv_pipe_power_well_disable,
1853 .is_enabled = chv_pipe_power_well_enabled,
1854};
1855
1856const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1857 .sync_hw = i9xx_power_well_sync_hw_noop,
1858 .enable = chv_dpio_cmn_power_well_enable,
1859 .disable = chv_dpio_cmn_power_well_disable,
1860 .is_enabled = vlv_power_well_enabled,
1861};
1862
1863const struct i915_power_well_ops i830_pipes_power_well_ops = {
1864 .sync_hw = i830_pipes_power_well_sync_hw,
1865 .enable = i830_pipes_power_well_enable,
1866 .disable = i830_pipes_power_well_disable,
1867 .is_enabled = i830_pipes_power_well_enabled,
1868};
1869
1870static const struct i915_power_well_regs hsw_power_well_regs = {
1871 .bios = HSW_PWR_WELL_CTL1((const i915_reg_t){ .reg = (0x45400) }),
1872 .driver = HSW_PWR_WELL_CTL2((const i915_reg_t){ .reg = (0x45404) }),
1873 .kvmr = HSW_PWR_WELL_CTL3((const i915_reg_t){ .reg = (0x45408) }),
1874 .debug = HSW_PWR_WELL_CTL4((const i915_reg_t){ .reg = (0x4540C) }),
1875};
1876
1877const struct i915_power_well_ops hsw_power_well_ops = {
1878 .regs = &hsw_power_well_regs,
1879 .sync_hw = hsw_power_well_sync_hw,
1880 .enable = hsw_power_well_enable,
1881 .disable = hsw_power_well_disable,
1882 .is_enabled = hsw_power_well_enabled,
1883};
1884
1885const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1886 .sync_hw = i9xx_power_well_sync_hw_noop,
1887 .enable = gen9_dc_off_power_well_enable,
1888 .disable = gen9_dc_off_power_well_disable,
1889 .is_enabled = gen9_dc_off_power_well_enabled,
1890};
1891
1892const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
1893 .sync_hw = i9xx_power_well_sync_hw_noop,
1894 .enable = bxt_dpio_cmn_power_well_enable,
1895 .disable = bxt_dpio_cmn_power_well_disable,
1896 .is_enabled = bxt_dpio_cmn_power_well_enabled,
1897};
1898
1899const struct i915_power_well_ops vlv_display_power_well_ops = {
1900 .sync_hw = i9xx_power_well_sync_hw_noop,
1901 .enable = vlv_display_power_well_enable,
1902 .disable = vlv_display_power_well_disable,
1903 .is_enabled = vlv_power_well_enabled,
1904};
1905
1906const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1907 .sync_hw = i9xx_power_well_sync_hw_noop,
1908 .enable = vlv_dpio_cmn_power_well_enable,
1909 .disable = vlv_dpio_cmn_power_well_disable,
1910 .is_enabled = vlv_power_well_enabled,
1911};
1912
1913const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1914 .sync_hw = i9xx_power_well_sync_hw_noop,
1915 .enable = vlv_power_well_enable,
1916 .disable = vlv_power_well_disable,
1917 .is_enabled = vlv_power_well_enabled,
1918};
1919
1920static const struct i915_power_well_regs icl_aux_power_well_regs = {
1921 .bios = ICL_PWR_WELL_CTL_AUX1((const i915_reg_t){ .reg = (0x45440) }),
1922 .driver = ICL_PWR_WELL_CTL_AUX2((const i915_reg_t){ .reg = (0x45444) }),
1923 .debug = ICL_PWR_WELL_CTL_AUX4((const i915_reg_t){ .reg = (0x4544C) }),
1924};
1925
1926const struct i915_power_well_ops icl_aux_power_well_ops = {
1927 .regs = &icl_aux_power_well_regs,
1928 .sync_hw = hsw_power_well_sync_hw,
1929 .enable = icl_aux_power_well_enable,
1930 .disable = icl_aux_power_well_disable,
1931 .is_enabled = hsw_power_well_enabled,
1932};
1933
1934static const struct i915_power_well_regs icl_ddi_power_well_regs = {
1935 .bios = ICL_PWR_WELL_CTL_DDI1((const i915_reg_t){ .reg = (0x45450) }),
1936 .driver = ICL_PWR_WELL_CTL_DDI2((const i915_reg_t){ .reg = (0x45454) }),
1937 .debug = ICL_PWR_WELL_CTL_DDI4((const i915_reg_t){ .reg = (0x4545C) }),
1938};
1939
1940const struct i915_power_well_ops icl_ddi_power_well_ops = {
1941 .regs = &icl_ddi_power_well_regs,
1942 .sync_hw = hsw_power_well_sync_hw,
1943 .enable = hsw_power_well_enable,
1944 .disable = hsw_power_well_disable,
1945 .is_enabled = hsw_power_well_enabled,
1946};
1947
1948const struct i915_power_well_ops tgl_tc_cold_off_ops = {
1949 .sync_hw = tgl_tc_cold_off_power_well_sync_hw,
1950 .enable = tgl_tc_cold_off_power_well_enable,
1951 .disable = tgl_tc_cold_off_power_well_disable,
1952 .is_enabled = tgl_tc_cold_off_power_well_is_enabled,
1953};
1954
1955const struct i915_power_well_ops xelpdp_aux_power_well_ops = {
1956 .sync_hw = i9xx_power_well_sync_hw_noop,
1957 .enable = xelpdp_aux_power_well_enable,
1958 .disable = xelpdp_aux_power_well_disable,
1959 .is_enabled = xelpdp_aux_power_well_enabled,
1960};