/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc

Bug Summary

File:	dev/pci/drm/amd/display/dc/core/dc_link.c
Warning:	line 4485, column 7 Dereference of null pointer
Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name dc_link.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link.c
1/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/

26#include <linux/slab.h>

28#include "dm_services.h"
29#include "atomfirmware.h"
30#include "dm_helpers.h"
31#include "dc.h"
32#include "grph_object_id.h"
33#include "gpio_service_interface.h"
34#include "core_status.h"
35#include "dc_link_dp.h"
36#include "dc_link_dpia.h"
37#include "dc_link_ddc.h"
38#include "link_hwss.h"
39#include "opp.h"

41#include "link_encoder.h"
42#include "hw_sequencer.h"
43#include "resource.h"
44#include "abm.h"
45#include "fixed31_32.h"
46#include "dpcd_defs.h"
47#include "dmcu.h"
48#include "hw/clk_mgr.h"
49#include "dce/dmub_psr.h"
50#include "dmub/dmub_srv.h"
51#include "inc/hw/panel_cntl.h"
52#include "inc/link_enc_cfg.h"
53#include "inc/link_dpcd.h"
54#include "link/link_dp_trace.h"

56#include "dc/dcn30/dcn30_vpg.h"

58#define DC_LOGGER_INIT(logger)

60#define LINK_INFO(...)___drm_dbg(((void *)0), DRM_UT_KMS, ...) \
DC_LOG_HW_HOTPLUG(  \___drm_dbg(((void *)0), DRM_UT_KMS, __VA_ARGS__)
__VA_ARGS__)___drm_dbg(((void *)0), DRM_UT_KMS, __VA_ARGS__)

64#define RETIMER_REDRIVER_INFO(...)___drm_dbg(((void *)0), DRM_UT_KMS, ...) \
DC_LOG_RETIMER_REDRIVER(  \___drm_dbg(((void *)0), DRM_UT_KMS, __VA_ARGS__)
__VA_ARGS__)___drm_dbg(((void *)0), DRM_UT_KMS, __VA_ARGS__)

68/*******************************************************************************
* Private functions
******************************************************************************/
71static void dc_link_destruct(struct dc_link *link)
72{
int i;

if (link->hpd_gpio) {
dal_gpio_destroy_irq(&link->hpd_gpio);
link->hpd_gpio = NULL((void *)0);
}

if (link->ddc)
dal_ddc_service_destroy(&link->ddc);

if (link->panel_cntl)
link->panel_cntl->funcs->destroy(&link->panel_cntl);

if (link->link_enc) {
/* Update link encoder resource tracking variables. These are used for
 * the dynamic assignment of link encoders to streams. Virtual links
 * are not assigned encoder resources on creation.
 */
if (link->link_id.id != CONNECTOR_ID_VIRTUAL) {
	link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL((void *)0);
	link->dc->res_pool->dig_link_enc_count--;
}
link->link_enc->funcs->destroy(&link->link_enc);
}

if (link->local_sink)
dc_sink_release(link->local_sink);

for (i = 0; i < link->sink_count; ++i)
dc_sink_release(link->remote_sinks[i]);
103}

105struct gpio *get_hpd_gpio(struct dc_bios *dcb,
	  struct graphics_object_id link_id,
	  struct gpio_service *gpio_service)
108{
enum bp_result bp_result;
struct graphics_object_hpd_info hpd_info;
struct gpio_pin_info pin_info;

if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
return NULL((void *)0);

bp_result = dcb->funcs->get_gpio_pin_info(dcb,
hpd_info.hpd_int_gpio_uid, &pin_info);

if (bp_result != BP_RESULT_OK) {
ASSERT(bp_result == BP_RESULT_NORECORD)do { if (({ static int __warned; int __ret = !!(!(bp_result ==
 BP_RESULT_NORECORD)); if (__ret && !__warned) { printf
("WARNING %s failed at %s:%d\n", "!(bp_result == BP_RESULT_NORECORD)"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link.c", 120
); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while
 (0); } while (0);
return NULL((void *)0);
}

return dal_gpio_service_create_irq(gpio_service,
			   pin_info.offset,
			   pin_info.mask);
127}

129/*
*  Function: program_hpd_filter
*
*  @brief
*     Programs HPD filter on associated HPD line
*
*  @param [in] delay_on_connect_in_ms: Connect filter timeout
*  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
*
*  @return
*     true on success, false otherwise
*/
141static bool_Bool program_hpd_filter(const struct dc_link *link)
142{
bool_Bool result = false0;
struct gpio *hpd;
int delay_on_connect_in_ms = 0;
int delay_on_disconnect_in_ms = 0;

if (link->is_hpd_filter_disabled)
return false0;
/* Verify feature is supported */
switch (link->connector_signal) {
case SIGNAL_TYPE_DVI_SINGLE_LINK:
case SIGNAL_TYPE_DVI_DUAL_LINK:
case SIGNAL_TYPE_HDMI_TYPE_A:
/* Program hpd filter */
delay_on_connect_in_ms = 500;
delay_on_disconnect_in_ms = 100;
break;
case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_DISPLAY_PORT_MST:
/* Program hpd filter to allow DP signal to settle */
/* 500:	not able to detect MST <-> SST switch as HPD is low for
 * only 100ms on DELL U2413
 * 0: some passive dongle still show aux mode instead of i2c
 * 20-50: not enough to hide bouncing HPD with passive dongle.
 * also see intermittent i2c read issues.
 */
delay_on_connect_in_ms = 80;
delay_on_disconnect_in_ms = 0;
break;
case SIGNAL_TYPE_LVDS:
case SIGNAL_TYPE_EDP:
default:
/* Don't program hpd filter */
return false0;
}

/* Obtain HPD handle */
hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
	   link->ctx->gpio_service);

if (!hpd)
return result;

/* Setup HPD filtering */
if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
struct gpio_hpd_config config;

config.delay_on_connect = delay_on_connect_in_ms;
config.delay_on_disconnect = delay_on_disconnect_in_ms;

dal_irq_setup_hpd_filter(hpd, &config);

dal_gpio_close(hpd);

result = true1;
} else {
ASSERT_CRITICAL(false)do { if (({ int __ret = !!(!(0)); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link.c"
, 198); __builtin_expect(!!(__ret), 0); })) do {} while (0); }
 while (0);
}

/* Release HPD handle */
dal_gpio_destroy_irq(&hpd);

return result;
205}

207bool_Bool dc_link_wait_for_t12(struct dc_link *link)
208{
if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
link->dc->hwss.edp_wait_for_T12(link);

return true1;
}

return false0;
216}

218/**
* dc_link_detect_sink() - Determine if there is a sink connected
*
* @link: pointer to the dc link
* @type: Returned connection type
* Does not detect downstream devices, such as MST sinks
* or display connected through active dongles
*/
226bool_Bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
227{
uint32_t is_hpd_high = 0;
struct gpio *hpd_pin;

if (link->connector_signal == SIGNAL_TYPE_LVDS) {
*type = dc_connection_single;
return true1;
}

if (link->connector_signal == SIGNAL_TYPE_EDP) {
/*in case it is not on*/
if (!link->dc->config.edp_no_power_sequencing)
	link->dc->hwss.edp_power_control(link, true1);
link->dc->hwss.edp_wait_for_hpd_ready(link, true1);
}

/* Link may not have physical HPD pin. */
if (link->ep_type != DISPLAY_ENDPOINT_PHY) {
if (link->is_hpd_pending || !dc_link_dpia_query_hpd_status(link))
	*type = dc_connection_none;
else
	*type = dc_connection_single;

return true1;
}

/* todo: may need to lock gpio access */
hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
	       link->ctx->gpio_service);
if (!hpd_pin)
goto hpd_gpio_failure;

dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
dal_gpio_get_value(hpd_pin, &is_hpd_high);
dal_gpio_close(hpd_pin);
dal_gpio_destroy_irq(&hpd_pin);

if (is_hpd_high) {
*type = dc_connection_single;
/* TODO: need to do the actual detection */
} else {
*type = dc_connection_none;
}

return true1;

273hpd_gpio_failure:
return false0;
275}

277static enum ddc_transaction_type get_ddc_transaction_type(enum amd_signal_type sink_signal)
278{
enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;

switch (sink_signal) {
case SIGNAL_TYPE_DVI_SINGLE_LINK:
case SIGNAL_TYPE_DVI_DUAL_LINK:
case SIGNAL_TYPE_HDMI_TYPE_A:
case SIGNAL_TYPE_LVDS:
case SIGNAL_TYPE_RGB:
transaction_type = DDC_TRANSACTION_TYPE_I2C;
break;

case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_EDP:
transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
break;

case SIGNAL_TYPE_DISPLAY_PORT_MST:
/* MST does not use I2COverAux, but there is the
 * SPECIAL use case for "immediate dwnstrm device
 * access" (EPR#370830).
 */
transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
break;

default:
break;
}

return transaction_type;
308}

310static enum amd_signal_type get_basic_signal_type(struct graphics_object_id encoder,
			      struct graphics_object_id downstream)
312{
if (downstream.type == OBJECT_TYPE_CONNECTOR) {
switch (downstream.id) {
case CONNECTOR_ID_SINGLE_LINK_DVII:
	switch (encoder.id) {
	case ENCODER_ID_INTERNAL_DAC1:
	case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
	case ENCODER_ID_INTERNAL_DAC2:
	case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
		return SIGNAL_TYPE_RGB;
	default:
		return SIGNAL_TYPE_DVI_SINGLE_LINK;
	}
break;
case CONNECTOR_ID_DUAL_LINK_DVII:
{
	switch (encoder.id) {
	case ENCODER_ID_INTERNAL_DAC1:
	case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
	case ENCODER_ID_INTERNAL_DAC2:
	case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
		return SIGNAL_TYPE_RGB;
	default:
		return SIGNAL_TYPE_DVI_DUAL_LINK;
	}
}
break;
case CONNECTOR_ID_SINGLE_LINK_DVID:
	return SIGNAL_TYPE_DVI_SINGLE_LINK;
case CONNECTOR_ID_DUAL_LINK_DVID:
	return SIGNAL_TYPE_DVI_DUAL_LINK;
case CONNECTOR_ID_VGA:
	return SIGNAL_TYPE_RGB;
case CONNECTOR_ID_HDMI_TYPE_A:
	return SIGNAL_TYPE_HDMI_TYPE_A;
case CONNECTOR_ID_LVDS:
	return SIGNAL_TYPE_LVDS;
case CONNECTOR_ID_DISPLAY_PORT:
case CONNECTOR_ID_USBC:
	return SIGNAL_TYPE_DISPLAY_PORT;
case CONNECTOR_ID_EDP:
	return SIGNAL_TYPE_EDP;
default:
	return SIGNAL_TYPE_NONE;
}
} else if (downstream.type == OBJECT_TYPE_ENCODER) {
switch (downstream.id) {
case ENCODER_ID_EXTERNAL_NUTMEG:
case ENCODER_ID_EXTERNAL_TRAVIS:
	return SIGNAL_TYPE_DISPLAY_PORT;
default:
	return SIGNAL_TYPE_NONE;
}
}

return SIGNAL_TYPE_NONE;
368}

370/*
* dc_link_is_dp_sink_present() - Check if there is a native DP
* or passive DP-HDMI dongle connected
*/
374bool_Bool dc_link_is_dp_sink_present(struct dc_link *link)
375{
enum gpio_result gpio_result;
uint32_t clock_pin = 0;
uint8_t retry = 0;
struct ddc *ddc;

enum connector_id connector_id =
dal_graphics_object_id_get_connector_id(link->link_id);

bool_Bool present =
((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
(connector_id == CONNECTOR_ID_EDP) ||
(connector_id == CONNECTOR_ID_USBC));

ddc = dal_ddc_service_get_ddc_pin(link->ddc);

if (!ddc) {
BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__
, 392); do {} while (0); } while (0);
return present;
}

/* Open GPIO and set it to I2C mode */
/* Note: this GpioMode_Input will be converted
* to GpioConfigType_I2cAuxDualMode in GPIO component,
* which indicates we need additional delay
*/

if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
	 GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
dal_ddc_close(ddc);

return present;
}

/*
* Read GPIO: DP sink is present if both clock and data pins are zero
*
* [W/A] plug-unplug DP cable, sometimes customer board has
* one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
* then monitor can't br light up. Add retry 3 times
* But in real passive dongle, it need additional 3ms to detect
*/
do {
gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
ASSERT(gpio_result == GPIO_RESULT_OK)do { if (({ static int __warned; int __ret = !!(!(gpio_result
 == GPIO_RESULT_OK)); if (__ret && !__warned) { printf
("WARNING %s failed at %s:%d\n", "!(gpio_result == GPIO_RESULT_OK)"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link.c", 419
); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while
 (0); } while (0);
if (clock_pin)
	udelay(1000);
else
	break;
} while (retry++ < 3);

present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;

dal_ddc_close(ddc);

return present;
431}

433/*
* @brief
* Detect output sink type
*/
437static enum amd_signal_type link_detect_sink(struct dc_link *link,
			 enum dc_detect_reason reason)
439{
enum amd_signal_type result;
struct graphics_object_id enc_id;

if (link->is_dig_mapping_flexible)
enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN};
else
enc_id = link->link_enc->id;
result = get_basic_signal_type(enc_id, link->link_id);

/* Use basic signal type for link without physical connector. */
if (link->ep_type != DISPLAY_ENDPOINT_PHY)
return result;

/* Internal digital encoder will detect only dongles
* that require digital signal
*/

/* Detection mechanism is different
* for different native connectors.
* LVDS connector supports only LVDS signal;
* PCIE is a bus slot, the actual connector needs to be detected first;
* eDP connector supports only eDP signal;
* HDMI should check straps for audio
*/

/* PCIE detects the actual connector on add-on board */
if (link->link_id.id == CONNECTOR_ID_PCIE) {
/* ZAZTODO implement PCIE add-on card detection */
}

switch (link->link_id.id) {
case CONNECTOR_ID_HDMI_TYPE_A: {
/* check audio support:
 * if native HDMI is not supported, switch to DVI
 */
struct audio_support *aud_support =
			&link->dc->res_pool->audio_support;

if (!aud_support->hdmi_audio_native)
	if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
		result = SIGNAL_TYPE_DVI_SINGLE_LINK;
}
break;
case CONNECTOR_ID_DISPLAY_PORT:
case CONNECTOR_ID_USBC: {
/* DP HPD short pulse. Passive DP dongle will not
 * have short pulse
 */
if (reason != DETECT_REASON_HPDRX) {
	/* Check whether DP signal detected: if not -
	 * we assume signal is DVI; it could be corrected
	 * to HDMI after dongle detection
	 */
	if (!dm_helpers_is_dp_sink_present(link))
		result = SIGNAL_TYPE_DVI_SINGLE_LINK;
}
}
break;
default:
break;
}

return result;
503}

505static enum amd_signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
						 struct audio_support *audio_support)
507{
enum amd_signal_type signal = SIGNAL_TYPE_NONE;

switch (dongle_type) {
case DISPLAY_DONGLE_DP_HDMI_DONGLE:
if (audio_support->hdmi_audio_on_dongle)
	signal = SIGNAL_TYPE_HDMI_TYPE_A;
else
	signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
break;
case DISPLAY_DONGLE_DP_DVI_DONGLE:
signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
break;
case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
if (audio_support->hdmi_audio_native)
	signal =  SIGNAL_TYPE_HDMI_TYPE_A;
else
	signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
break;
default:
signal = SIGNAL_TYPE_NONE;
break;
}

return signal;
532}

534static enum amd_signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
				    struct display_sink_capability *sink_cap,
				    struct audio_support *audio_support)
537{
dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap);

return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
					audio_support);
542}

544static void link_disconnect_sink(struct dc_link *link)
545{
if (link->local_sink) {
dc_sink_release(link->local_sink);
link->local_sink = NULL((void *)0);
}

link->dpcd_sink_count = 0;
//link->dpcd_caps.dpcd_rev.raw = 0;
553}

555static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
556{
dc_sink_release(link->local_sink);
link->local_sink = prev_sink;
559}

561#if defined(CONFIG_DRM_AMD_DC_HDCP)
562bool_Bool dc_link_is_hdcp14(struct dc_link *link, enum amd_signal_type signal)
563{
bool_Bool ret = false0;

switch (signal)	{
case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_DISPLAY_PORT_MST:
ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
break;
case SIGNAL_TYPE_DVI_SINGLE_LINK:
case SIGNAL_TYPE_DVI_DUAL_LINK:
case SIGNAL_TYPE_HDMI_TYPE_A:
/* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
* we can poll for bksv but some displays have an issue with this. Since its so rare
* for a display to not be 1.4 capable, this assumtion is ok
*/
ret = true1;
break;
default:
break;
}
return ret;
584}

586bool_Bool dc_link_is_hdcp22(struct dc_link *link, enum amd_signal_type signal)
587{
bool_Bool ret = false0;

switch (signal)	{
case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_DISPLAY_PORT_MST:
ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
		link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
		(link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
break;
case SIGNAL_TYPE_DVI_SINGLE_LINK:
case SIGNAL_TYPE_DVI_DUAL_LINK:
case SIGNAL_TYPE_HDMI_TYPE_A:
ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
break;
default:
break;
}

return ret;
607}

609static void query_hdcp_capability(enum amd_signal_type signal, struct dc_link *link)
610{
struct hdcp_protection_message msg22;
struct hdcp_protection_message msg14;

memset(&msg22, 0, sizeof(struct hdcp_protection_message))__builtin_memset((&msg22), (0), (sizeof(struct hdcp_protection_message
)));
memset(&msg14, 0, sizeof(struct hdcp_protection_message))__builtin_memset((&msg14), (0), (sizeof(struct hdcp_protection_message
)));
memset(link->hdcp_caps.rx_caps.raw, 0,__builtin_memset((link->hdcp_caps.rx_caps.raw), (0), (sizeof
(link->hdcp_caps.rx_caps.raw)))
sizeof(link->hdcp_caps.rx_caps.raw))__builtin_memset((link->hdcp_caps.rx_caps.raw), (0), (sizeof
(link->hdcp_caps.rx_caps.raw)));

if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
	link->ddc->transaction_type ==
	DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
	link->connector_signal == SIGNAL_TYPE_EDP) {
msg22.data = link->hdcp_caps.rx_caps.raw;
msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
} else {
msg22.data = &link->hdcp_caps.rx_caps.fields.version;
msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
}
msg22.version = HDCP_VERSION_22;
msg22.link = HDCP_LINK_PRIMARY;
msg22.max_retries = 5;
dc_process_hdcp_msg(signal, link, &msg22);

if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
msg14.data = &link->hdcp_caps.bcaps.raw;
msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
msg14.version = HDCP_VERSION_14;
msg14.link = HDCP_LINK_PRIMARY;
msg14.max_retries = 5;

dc_process_hdcp_msg(signal, link, &msg14);
}

647}
648#endif

650static void read_current_link_settings_on_detect(struct dc_link *link)
651{
union lane_count_set lane_count_set = {0};
uint8_t link_bw_set;
uint8_t link_rate_set;
uint32_t read_dpcd_retry_cnt = 10;
enum dc_status status = DC_ERROR_UNEXPECTED;
int i;
union max_down_spread max_down_spread = {0};

// Read DPCD 00101h to find out the number of lanes currently set
for (i = 0; i < read_dpcd_retry_cnt; i++) {
status = core_link_read_dpcd(link,
			     DP_LANE_COUNT_SET0x101,
			     &lane_count_set.raw,
			     sizeof(lane_count_set));
/* First DPCD read after VDD ON can fail if the particular board
 * does not have HPD pin wired correctly. So if DPCD read fails,
 * which it should never happen, retry a few times. Target worst
 * case scenario of 80 ms.
 */
if (status == DC_OK) {
	link->cur_link_settings.lane_count =
			lane_count_set.bits.LANE_COUNT_SET;
	break;
}

drm_msleep(8)mdelay(8);
}

// Read DPCD 00100h to find if standard link rates are set
core_link_read_dpcd(link, DP_LINK_BW_SET0x100,
	    &link_bw_set, sizeof(link_bw_set));

if (link_bw_set == 0) {
if (link->connector_signal == SIGNAL_TYPE_EDP) {
	/* If standard link rates are not being used,
	 * Read DPCD 00115h to find the edp link rate set used
	 */
	core_link_read_dpcd(link, DP_LINK_RATE_SET0x115,
			    &link_rate_set, sizeof(link_rate_set));

	// edp_supported_link_rates_count = 0 for DP
	if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
		link->cur_link_settings.link_rate =
			link->dpcd_caps.edp_supported_link_rates[link_rate_set];
		link->cur_link_settings.link_rate_set = link_rate_set;
		link->cur_link_settings.use_link_rate_set = true1;
	}
} else {
	// Link Rate not found. Seamless boot may not work.
	ASSERT(false)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret
 && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link.c"
, 701); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
 {} while (0); } while (0);
}
} else {
link->cur_link_settings.link_rate = link_bw_set;
link->cur_link_settings.use_link_rate_set = false0;
}
// Read DPCD 00003h to find the max down spread.
core_link_read_dpcd(link, DP_MAX_DOWNSPREAD0x003,
	    &max_down_spread.raw, sizeof(max_down_spread));
link->cur_link_settings.link_spread =
max_down_spread.bits.MAX_DOWN_SPREAD ?
LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
713}

715static bool_Bool detect_dp(struct dc_link *link,
      struct display_sink_capability *sink_caps,
      enum dc_detect_reason reason)
718{
struct audio_support *audio_support = &link->dc->res_pool->audio_support;

sink_caps->signal = link_detect_sink(link, reason);
sink_caps->transaction_type =
get_ddc_transaction_type(sink_caps->signal);

if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
if (!detect_dp_sink_caps(link))
	return false0;

if (is_dp_branch_device(link))
	/* DP SST branch */
	link->type = dc_connection_sst_branch;
} else {
/* DP passive dongles */
sink_caps->signal = dp_passive_dongle_detection(link->ddc,
						sink_caps,
						audio_support);
link->dpcd_caps.dongle_type = sink_caps->dongle_type;
link->dpcd_caps.is_dongle_type_one = sink_caps->is_dongle_type_one;
link->dpcd_caps.dpcd_rev.raw = 0;
}

return true1;
744}

746static bool_Bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
747{
if (old_edid->length != new_edid->length)
return false0;

if (new_edid->length == 0)
return false0;

return (memcmp(old_edid->raw_edid,__builtin_memcmp((old_edid->raw_edid), (new_edid->raw_edid
), (new_edid->length))
       new_edid->raw_edid, new_edid->length)__builtin_memcmp((old_edid->raw_edid), (new_edid->raw_edid
), (new_edid->length)) == 0);
756}

758static bool_Bool wait_for_entering_dp_alt_mode(struct dc_link *link)
759{
/**
* something is terribly wrong if time out is > 200ms. (5Hz)
* 500 microseconds * 400 tries us 200 ms
**/
unsigned int sleep_time_in_microseconds = 500;
unsigned int tries_allowed = 400;
bool_Bool is_in_alt_mode;
unsigned long long enter_timestamp;
unsigned long long finish_timestamp;
unsigned long long time_taken_in_ns;
int tries_taken;

DC_LOGGER_INIT(link->ctx->logger);

if (!link->link_enc->funcs->is_in_alt_mode)
return true1;

is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode)printk("\0014" "[" "drm" "] " "DP Alt mode state on HPD: %d\n"
, is_in_alt_mode);

if (is_in_alt_mode)
return true1;

enter_timestamp = dm_get_timestamp(link->ctx);

for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
udelay(sleep_time_in_microseconds);
/* ask the link if alt mode is enabled, if so return ok */
if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
	finish_timestamp = dm_get_timestamp(link->ctx);
	time_taken_in_ns =
		dm_get_elapse_time_in_ns(link->ctx,
					 finish_timestamp,
					 enter_timestamp);
	DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",printk("\0014" "[" "drm" "] " "Alt mode entered finished after %llu ms\n"
, div_u64(time_taken_in_ns, 1000000))
		       div_u64(time_taken_in_ns, 1000000))printk("\0014" "[" "drm" "] " "Alt mode entered finished after %llu ms\n"
, div_u64(time_taken_in_ns, 1000000));
	return true1;
}
}
finish_timestamp = dm_get_timestamp(link->ctx);
time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
				    enter_timestamp);
DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",printk("\0014" "[" "drm" "] " "Alt mode has timed out after %llu ms\n"
, div_u64(time_taken_in_ns, 1000000))
       div_u64(time_taken_in_ns, 1000000))printk("\0014" "[" "drm" "] " "Alt mode has timed out after %llu ms\n"
, div_u64(time_taken_in_ns, 1000000));
return false0;
805}

807static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
808{
/* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock
* reports DSC support.
*/
if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
	link->type == dc_connection_mst_branch &&
	link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC240x90CC24 &&
	link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_200x20 &&
	link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
	!link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
link->wa_flags.dpia_mst_dsc_always_on = true1;
819}

821static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link)
822{
/* Disable work around which keeps DSC on for tunneled MST on certain USB4 docks. */
if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
link->wa_flags.dpia_mst_dsc_always_on = false0;
826}

828static bool_Bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason reason)
829{
DC_LOGGER_INIT(link->ctx->logger);

LINK_INFO("link=%d, mst branch is now Connected\n",___drm_dbg(((void *)0), DRM_UT_KMS, "link=%d, mst branch is now Connected\n"
, link->link_index)
  link->link_index)___drm_dbg(((void *)0), DRM_UT_KMS, "link=%d, mst branch is now Connected\n"
, link->link_index);

link->type = dc_connection_mst_branch;
apply_dpia_mst_dsc_always_on_wa(link);

dm_helpers_dp_update_branch_info(link->ctx, link);
if (dm_helpers_dp_mst_start_top_mgr(link->ctx,
	link, (reason == DETECT_REASON_BOOT || reason == DETECT_REASON_RESUMEFROMS3S4))) {
link_disconnect_sink(link);
} else {
link->type = dc_connection_sst_branch;
}

return link->type == dc_connection_mst_branch;
847}

849bool_Bool reset_cur_dp_mst_topology(struct dc_link *link)
850{
DC_LOGGER_INIT(link->ctx->logger);

LINK_INFO("link=%d, mst branch is now Disconnected\n",___drm_dbg(((void *)0), DRM_UT_KMS, "link=%d, mst branch is now Disconnected\n"
, link->link_index)
  link->link_index)___drm_dbg(((void *)0), DRM_UT_KMS, "link=%d, mst branch is now Disconnected\n"
, link->link_index);

revert_dpia_mst_dsc_always_on_wa(link);
return dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
858}

860static bool_Bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc,
enum dc_detect_reason reason)
862{
int i;
bool_Bool can_apply_seamless_boot = false0;

for (i = 0; i < dc->current_state->stream_count; i++) {
if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
	can_apply_seamless_boot = true1;
	break;
}
}

return !can_apply_seamless_boot && reason != DETECT_REASON_BOOT;
874}

876static void prepare_phy_clocks_for_destructive_link_verification(const struct dc *dc)
877{
dc_z10_restore(dc);
clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
880}

882static void restore_phy_clocks_for_destructive_link_verification(const struct dc *dc)
883{
clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
885}

887static void set_all_streams_dpms_off_for_link(struct dc_link *link)
888{
int i;
struct pipe_ctx *pipe_ctx;
struct dc_stream_update stream_update;
bool_Bool dpms_off = true1;
struct link_resource link_res = {0};

memset(&stream_update, 0, sizeof(stream_update))__builtin_memset((&stream_update), (0), (sizeof(stream_update
)));
stream_update.dpms_off = &dpms_off;

for (i = 0; i < MAX_PIPES6; i++) {
pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
		pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe) {
	stream_update.stream = pipe_ctx->stream;
	dc_commit_updates_for_stream(link->ctx->dc, NULL((void *)0), 0,
			pipe_ctx->stream, &stream_update,
			link->ctx->dc->current_state);
}
}

/* link can be also enabled by vbios. In this case it is not recorded
* in pipe_ctx. Disable link phy here to make sure it is completely off
*/
dp_disable_link_phy(link, &link_res, link->connector_signal);
913}

915static void verify_link_capability_destructive(struct dc_link *link,
struct dc_sink *sink,
enum dc_detect_reason reason)
918{
bool_Bool should_prepare_phy_clocks =
	should_prepare_phy_clocks_for_link_verification(link->dc, reason);

if (should_prepare_phy_clocks)
prepare_phy_clocks_for_destructive_link_verification(link->dc);

if (dc_is_dp_signal(link->local_sink->sink_signal)) {
struct dc_link_settings known_limit_link_setting =
		dp_get_max_link_cap(link);
set_all_streams_dpms_off_for_link(link);
dp_verify_link_cap_with_retries(
		link, &known_limit_link_setting,
		LINK_TRAINING_MAX_VERIFY_RETRY);
} else {
ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret
 && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link.c"
, 933); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
 {} while (0); } while (0);
}

if (should_prepare_phy_clocks)
restore_phy_clocks_for_destructive_link_verification(link->dc);
938}

940static void verify_link_capability_non_destructive(struct dc_link *link)
941{
if (dc_is_dp_signal(link->local_sink->sink_signal)) {
if (dc_is_embedded_signal(link->local_sink->sink_signal) ||
		link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
	/* TODO - should we check link encoder's max link caps here?
	 * How do we know which link encoder to check from?
	 */
	link->verified_link_cap = link->reported_link_cap;
else
	link->verified_link_cap = dp_get_max_link_cap(link);
}
952}

954static bool_Bool should_verify_link_capability_destructively(struct dc_link *link,
enum dc_detect_reason reason)
956{
bool_Bool destrictive = false0;
struct dc_link_settings max_link_cap;
bool_Bool is_link_enc_unavailable = link->link_enc &&
	link->dc->res_pool->funcs->link_encs_assign &&
	!link_enc_cfg_is_link_enc_avail(
			link->ctx->dc,
			link->link_enc->preferred_engine,
			link);

if (dc_is_dp_signal(link->local_sink->sink_signal)) {
max_link_cap = dp_get_max_link_cap(link);
destrictive = true1;

if (link->dc->debug.skip_detection_link_training ||
		dc_is_embedded_signal(link->local_sink->sink_signal) ||
		link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
	destrictive = false0;
} else if (dp_get_link_encoding_format(&max_link_cap) ==
		DP_8b_10b_ENCODING) {
	if (link->dpcd_caps.is_mst_capable ||
			is_link_enc_unavailable) {
		destrictive = false0;
	}
}
}

return destrictive;
984}

986static void verify_link_capability(struct dc_link *link, struct dc_sink *sink,
enum dc_detect_reason reason)
988{
if (should_verify_link_capability_destructively(link, reason))
verify_link_capability_destructive(link, sink, reason);
else
verify_link_capability_non_destructive(link);
993}


996/**
* detect_link_and_local_sink() - Detect if a sink is attached to a given link
*
* link->local_sink is created or destroyed as needed.
*
* This does not create remote sinks.
*/
1003static bool_Bool detect_link_and_local_sink(struct dc_link *link,
		  enum dc_detect_reason reason)
1005{
struct dc_sink_init_data sink_init_data = { 0 };
struct display_sink_capability sink_caps = { 0 };
uint32_t i;
bool_Bool converter_disable_audio = false0;
struct audio_support *aud_support = &link->dc->res_pool->audio_support;
bool_Bool same_edid = false0;
enum dc_edid_status edid_status;
struct dc_context *dc_ctx = link->ctx;
struct dc *dc = dc_ctx->dc;
struct dc_sink *sink = NULL((void *)0);
struct dc_sink *prev_sink = NULL((void *)0);
struct dpcd_caps prev_dpcd_caps;
enum dc_connection_type new_connection_type = dc_connection_none;
enum dc_connection_type pre_connection_type = link->type;
const uint32_t post_oui_delay = 30; // 30ms

DC_LOGGER_INIT(link->ctx->logger);

if (dc_is_virtual_signal(link->connector_signal))
return false0;

if (((link->connector_signal == SIGNAL_TYPE_LVDS ||
link->connector_signal == SIGNAL_TYPE_EDP) &&
(!link->dc->config.allow_edp_hotplug_detection)) &&
link->local_sink) {
// need to re-write OUI and brightness in resume case
if (link->connector_signal == SIGNAL_TYPE_EDP &&
	(link->dpcd_sink_ext_caps.bits.oled == 1)) {
	dpcd_set_source_specific_data(link);
	drm_msleep(post_oui_delay)mdelay(post_oui_delay);
	dc_link_set_default_brightness_aux(link);
	//TODO: use cached
}

return true1;
}

if (!dc_link_detect_sink(link, &new_connection_type)) {
BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__
, 1044); do {} while (0); } while (0);
return false0;
}

prev_sink = link->local_sink;
if (prev_sink) {
dc_sink_retain(prev_sink);
memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps))__builtin_memcpy((&prev_dpcd_caps), (&link->dpcd_caps
), (sizeof(struct dpcd_caps)));
}

link_disconnect_sink(link);
if (new_connection_type != dc_connection_none) {
link->type = new_connection_type;
link->link_state_valid = false0;

/* From Disconnected-to-Connected. */
switch (link->connector_signal) {
case SIGNAL_TYPE_HDMI_TYPE_A: {
	sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
	if (aud_support->hdmi_audio_native)
		sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
	else
		sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
	break;
}

case SIGNAL_TYPE_DVI_SINGLE_LINK: {
	sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
	sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
	break;
}

case SIGNAL_TYPE_DVI_DUAL_LINK: {
	sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
	sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
	break;
}

case SIGNAL_TYPE_LVDS: {
	sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
	sink_caps.signal = SIGNAL_TYPE_LVDS;
	break;
}

case SIGNAL_TYPE_EDP: {
	read_current_link_settings_on_detect(link);

	detect_edp_sink_caps(link);
	read_current_link_settings_on_detect(link);

	/* Disable power sequence on MIPI panel + converter
	 */
	if (dc->config.enable_mipi_converter_optimization &&
		dc_ctx->dce_version == DCN_VERSION_3_01 &&
		link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0022B90x0022B9 &&
		memcmp(&link->dpcd_caps.branch_dev_name, DP_SINK_BRANCH_DEV_NAME_7580,__builtin_memcmp((&link->dpcd_caps.branch_dev_name), (
DP_SINK_BRANCH_DEV_NAME_7580), (sizeof(link->dpcd_caps.branch_dev_name
)))
			sizeof(link->dpcd_caps.branch_dev_name))__builtin_memcmp((&link->dpcd_caps.branch_dev_name), (
DP_SINK_BRANCH_DEV_NAME_7580), (sizeof(link->dpcd_caps.branch_dev_name
))) == 0) {
		dc->config.edp_no_power_sequencing = true1;

		if (!link->dpcd_caps.set_power_state_capable_edp)
			link->wa_flags.dp_keep_receiver_powered = true1;
	}

	sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
	sink_caps.signal = SIGNAL_TYPE_EDP;
	break;
}

case SIGNAL_TYPE_DISPLAY_PORT: {
	/* wa HPD high coming too early*/
	if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
	    link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
		/* if alt mode times out, return false */
		if (!wait_for_entering_dp_alt_mode(link))
			return false0;
	}

	if (!detect_dp(link, &sink_caps, reason)) {
		link->type = pre_connection_type;

		if (prev_sink)
			dc_sink_release(prev_sink);
		return false0;
	}

	/* Active SST downstream branch device unplug*/
	if (link->type == dc_connection_sst_branch &&
	    link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
		if (prev_sink)
			/* Downstream unplug */
			dc_sink_release(prev_sink);
		return true1;
	}

	/* disable audio for non DP to HDMI active sst converter */
	if (link->type == dc_connection_sst_branch &&
			is_dp_active_dongle(link) &&
			(link->dpcd_caps.dongle_type !=
					DISPLAY_DONGLE_DP_HDMI_CONVERTER))
		converter_disable_audio = true1;

	/* limited link rate to HBR3 for DPIA until we implement USB4 V2 */
	if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
			link->reported_link_cap.link_rate > LINK_RATE_HIGH3)
		link->reported_link_cap.link_rate = LINK_RATE_HIGH3;
	break;
}

default:
	DC_ERROR("Invalid connector type! signal:%d\n",do { (void)(dc_ctx); __drm_err("Invalid connector type! signal:%d\n"
, link->connector_signal); } while (0)
		 link->connector_signal)do { (void)(dc_ctx); __drm_err("Invalid connector type! signal:%d\n"
, link->connector_signal); } while (0);
	if (prev_sink)
		dc_sink_release(prev_sink);
	return false0;
} /* switch() */

if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
	link->dpcd_sink_count =
		link->dpcd_caps.sink_count.bits.SINK_COUNT;
else
	link->dpcd_sink_count = 1;

dal_ddc_service_set_transaction_type(link->ddc,
				     sink_caps.transaction_type);

link->aux_mode =
	dal_ddc_service_is_in_aux_transaction_mode(link->ddc);

sink_init_data.link = link;
sink_init_data.sink_signal = sink_caps.signal;

sink = dc_sink_create(&sink_init_data);
if (!sink) {
	DC_ERROR("Failed to create sink!\n")do { (void)(dc_ctx); __drm_err("Failed to create sink!\n"); }
 while (0);
	if (prev_sink)
		dc_sink_release(prev_sink);
	return false0;
}

sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
sink->converter_disable_audio = converter_disable_audio;

/* dc_sink_create returns a new reference */
link->local_sink = sink;

edid_status = dm_helpers_read_local_edid(link->ctx,
					 link, sink);

switch (edid_status) {
case EDID_BAD_CHECKSUM:
	DC_LOG_ERROR("EDID checksum invalid.\n")__drm_err("EDID checksum invalid.\n");
	break;
case EDID_PARTIAL_VALID:
	DC_LOG_ERROR("Partial EDID valid, abandon invalid blocks.\n")__drm_err("Partial EDID valid, abandon invalid blocks.\n");
	break;
case EDID_NO_RESPONSE:
	DC_LOG_ERROR("No EDID read.\n")__drm_err("No EDID read.\n");
	/*
	 * Abort detection for non-DP connectors if we have
	 * no EDID
	 *
	 * DP needs to report as connected if HDP is high
	 * even if we have no EDID in order to go to
	 * fail-safe mode
	 */
	if (dc_is_hdmi_signal(link->connector_signal) ||
	    dc_is_dvi_signal(link->connector_signal)) {
		if (prev_sink)
			dc_sink_release(prev_sink);

		return false0;
	}

	if (link->type == dc_connection_sst_branch &&
			link->dpcd_caps.dongle_type ==
				DISPLAY_DONGLE_DP_VGA_CONVERTER &&
			reason == DETECT_REASON_HPDRX) {
		/* Abort detection for DP-VGA adapters when EDID
		 * can't be read and detection reason is VGA-side
		 * hotplug
		 */
		if (prev_sink)
			dc_sink_release(prev_sink);
		link_disconnect_sink(link);

		return true1;
	}

	break;
default:
	break;
}

// Check if edid is the same
if ((prev_sink) &&
    (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
	same_edid = is_same_edid(&prev_sink->dc_edid,
				 &sink->dc_edid);

if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
	link->ctx->dc->debug.hdmi20_disable = true1;

if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
    sink_caps.transaction_type ==
    DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
	/*
	 * TODO debug why Dell 2413 doesn't like
	 *  two link trainings
	 */
1253#if defined(CONFIG_DRM_AMD_DC_HDCP)
	query_hdcp_capability(sink->sink_signal, link);
1255#endif
} else {
	// If edid is the same, then discard new sink and revert back to original sink
	if (same_edid) {
		link_disconnect_remap(prev_sink, link);
		sink = prev_sink;
		prev_sink = NULL((void *)0);
	}
1263#if defined(CONFIG_DRM_AMD_DC_HDCP)
	query_hdcp_capability(sink->sink_signal, link);
1265#endif
}

/* HDMI-DVI Dongle */
if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
    !sink->edid_caps.edid_hdmi)
	sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;

if (link->local_sink && dc_is_dp_signal(sink_caps.signal))
	dp_trace_init(link);

/* Connectivity log: detection */
for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE128; i++) {
	CONN_DATA_DETECT(link,do { (void)(link); ___drm_dbg(((void *)0), DRM_UT_KMS, "%s: [Block %d] "
, sink->edid_caps.display_name, i); } while (0)
			 &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],do { (void)(link); ___drm_dbg(((void *)0), DRM_UT_KMS, "%s: [Block %d] "
, sink->edid_caps.display_name, i); } while (0)
			 DC_EDID_BLOCK_SIZE,do { (void)(link); ___drm_dbg(((void *)0), DRM_UT_KMS, "%s: [Block %d] "
, sink->edid_caps.display_name, i); } while (0)
			 "%s: [Block %d] ", sink->edid_caps.display_name, i)do { (void)(link); ___drm_dbg(((void *)0), DRM_UT_KMS, "%s: [Block %d] "
, sink->edid_caps.display_name, i); } while (0);
}

DC_LOG_DETECTION_EDID_PARSER("%s: "___drm_dbg(((void *)0), DRM_UT_KMS, "%s: " "manufacturer_id = %X, "
 "product_id = %X, " "serial_number = %X, " "manufacture_week = %d, "
 "manufacture_year = %d, " "display_name = %s, " "speaker_flag = %d, "
 "audio_mode_count = %d\n", __func__, sink->edid_caps.manufacturer_id
, sink->edid_caps.product_id, sink->edid_caps.serial_number
, sink->edid_caps.manufacture_week, sink->edid_caps.manufacture_year
, sink->edid_caps.display_name, sink->edid_caps.speaker_flags
, sink->edid_caps.audio_mode_count)
	"manufacturer_id = %X, "___drm_dbg(((void *)0), DRM_UT_KMS, "%s: " "manufacturer_id = %X, "
 "product_id = %X, " "serial_number = %X, " "manufacture_week = %d, "
 "manufacture_year = %d, " "display_name = %s, " "speaker_flag = %d, "
 "audio_mode_count = %d\n", __func__, sink->edid_caps.manufacturer_id
, sink->edid_caps.product_id, sink->edid_caps.serial_number
, sink->edid_caps.manufacture_week, sink->edid_caps.manufacture_year
, sink->edid_caps.display_name, sink->edid_caps.speaker_flags
, sink->edid_caps.audio_mode_count)
	"product_id = %X, "___drm_dbg(((void *)0), DRM_UT_KMS, "%s: " "manufacturer_id = %X, "
 "product_id = %X, " "serial_number = %X, " "manufacture_week = %d, "
 "manufacture_year = %d, " "display_name = %s, " "speaker_flag = %d, "
 "audio_mode_count = %d\n", __func__, sink->edid_caps.manufacturer_id
, sink->edid_caps.product_id, sink->edid_caps.serial_number
, sink->edid_caps.manufacture_week, sink->edid_caps.manufacture_year
, sink->edid_caps.display_name, sink->edid_caps.speaker_flags
, sink->edid_caps.audio_mode_count)
	"serial_number = %X, "___drm_dbg(((void *)0), DRM_UT_KMS, "%s: " "manufacturer_id = %X, "
 "product_id = %X, " "serial_number = %X, " "manufacture_week = %d, "
 "manufacture_year = %d, " "display_name = %s, " "speaker_flag = %d, "
 "audio_mode_count = %d\n", __func__, sink->edid_caps.manufacturer_id
, sink->edid_caps.product_id, sink->edid_caps.serial_number
, sink->edid_caps.manufacture_week, sink->edid_caps.manufacture_year
, sink->edid_caps.display_name, sink->edid_caps.speaker_flags
, sink->edid_caps.audio_mode_count)
	"manufacture_week = %d, "___drm_dbg(((void *)0), DRM_UT_KMS, "%s: " "manufacturer_id = %X, "
 "product_id = %X, " "serial_number = %X, " "manufacture_week = %d, "
 "manufacture_year = %d, " "display_name = %s, " "speaker_flag = %d, "
 "audio_mode_count = %d\n", __func__, sink->edid_caps.manufacturer_id
, sink->edid_caps.product_id, sink->edid_caps.serial_number
, sink->edid_caps.manufacture_week, sink->edid_caps.manufacture_year
, sink->edid_caps.display_name, sink->edid_caps.speaker_flags
, sink->edid_caps.audio_mode_count)
	"manufacture_year = %d, "___drm_dbg(((void *)0), DRM_UT_KMS, "%s: " "manufacturer_id = %X, "
 "product_id = %X, " "serial_number = %X, " "manufacture_week = %d, "
 "manufacture_year = %d, " "display_name = %s, " "speaker_flag = %d, "
 "audio_mode_count = %d\n", __func__, sink->edid_caps.manufacturer_id
, sink->edid_caps.product_id, sink->edid_caps.serial_number
, sink->edid_caps.manufacture_week, sink->edid_caps.manufacture_year
, sink->edid_caps.display_name, sink->edid_caps.speaker_flags
, sink->edid_caps.audio_mode_count)
	"display_name = %s, "___drm_dbg(((void *)0), DRM_UT_KMS, "%s: " "manufacturer_id = %X, "
 "product_id = %X, " "serial_number = %X, " "manufacture_week = %d, "
 "manufacture_year = %d, " "display_name = %s, " "speaker_flag = %d, "
 "audio_mode_count = %d\n", __func__, sink->edid_caps.manufacturer_id
, sink->edid_caps.product_id, sink->edid_caps.serial_number
, sink->edid_caps.manufacture_week, sink->edid_caps.manufacture_year
, sink->edid_caps.display_name, sink->edid_caps.speaker_flags
, sink->edid_caps.audio_mode_count)
	"speaker_flag = %d, "___drm_dbg(((void *)0), DRM_UT_KMS, "%s: " "manufacturer_id = %X, "
 "product_id = %X, " "serial_number = %X, " "manufacture_week = %d, "
 "manufacture_year = %d, " "display_name = %s, " "speaker_flag = %d, "
 "audio_mode_count = %d\n", __func__, sink->edid_caps.manufacturer_id
, sink->edid_caps.product_id, sink->edid_caps.serial_number
, sink->edid_caps.manufacture_week, sink->edid_caps.manufacture_year
, sink->edid_caps.display_name, sink->edid_caps.speaker_flags
, sink->edid_caps.audio_mode_count)
	"audio_mode_count = %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "%s: " "manufacturer_id = %X, "
 "product_id = %X, " "serial_number = %X, " "manufacture_week = %d, "
 "manufacture_year = %d, " "display_name = %s, " "speaker_flag = %d, "
 "audio_mode_count = %d\n", __func__, sink->edid_caps.manufacturer_id
, sink->edid_caps.product_id, sink->edid_caps.serial_number
, sink->edid_caps.manufacture_week, sink->edid_caps.manufacture_year
, sink->edid_caps.display_name, sink->edid_caps.speaker_flags
, sink->edid_caps.audio_mode_count)
	__func__,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: " "manufacturer_id = %X, "
 "product_id = %X, " "serial_number = %X, " "manufacture_week = %d, "
 "manufacture_year = %d, " "display_name = %s, " "speaker_flag = %d, "
 "audio_mode_count = %d\n", __func__, sink->edid_caps.manufacturer_id
, sink->edid_caps.product_id, sink->edid_caps.serial_number
, sink->edid_caps.manufacture_week, sink->edid_caps.manufacture_year
, sink->edid_caps.display_name, sink->edid_caps.speaker_flags
, sink->edid_caps.audio_mode_count)
	sink->edid_caps.manufacturer_id,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: " "manufacturer_id = %X, "
 "product_id = %X, " "serial_number = %X, " "manufacture_week = %d, "
 "manufacture_year = %d, " "display_name = %s, " "speaker_flag = %d, "
 "audio_mode_count = %d\n", __func__, sink->edid_caps.manufacturer_id
, sink->edid_caps.product_id, sink->edid_caps.serial_number
, sink->edid_caps.manufacture_week, sink->edid_caps.manufacture_year
, sink->edid_caps.display_name, sink->edid_caps.speaker_flags
, sink->edid_caps.audio_mode_count)
	sink->edid_caps.product_id,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: " "manufacturer_id = %X, "
 "product_id = %X, " "serial_number = %X, " "manufacture_week = %d, "
 "manufacture_year = %d, " "display_name = %s, " "speaker_flag = %d, "
 "audio_mode_count = %d\n", __func__, sink->edid_caps.manufacturer_id
, sink->edid_caps.product_id, sink->edid_caps.serial_number
, sink->edid_caps.manufacture_week, sink->edid_caps.manufacture_year
, sink->edid_caps.display_name, sink->edid_caps.speaker_flags
, sink->edid_caps.audio_mode_count)
	sink->edid_caps.serial_number,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: " "manufacturer_id = %X, "
 "product_id = %X, " "serial_number = %X, " "manufacture_week = %d, "
 "manufacture_year = %d, " "display_name = %s, " "speaker_flag = %d, "
 "audio_mode_count = %d\n", __func__, sink->edid_caps.manufacturer_id
, sink->edid_caps.product_id, sink->edid_caps.serial_number
, sink->edid_caps.manufacture_week, sink->edid_caps.manufacture_year
, sink->edid_caps.display_name, sink->edid_caps.speaker_flags
, sink->edid_caps.audio_mode_count)
	sink->edid_caps.manufacture_week,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: " "manufacturer_id = %X, "
 "product_id = %X, " "serial_number = %X, " "manufacture_week = %d, "
 "manufacture_year = %d, " "display_name = %s, " "speaker_flag = %d, "
 "audio_mode_count = %d\n", __func__, sink->edid_caps.manufacturer_id
, sink->edid_caps.product_id, sink->edid_caps.serial_number
, sink->edid_caps.manufacture_week, sink->edid_caps.manufacture_year
, sink->edid_caps.display_name, sink->edid_caps.speaker_flags
, sink->edid_caps.audio_mode_count)
	sink->edid_caps.manufacture_year,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: " "manufacturer_id = %X, "
 "product_id = %X, " "serial_number = %X, " "manufacture_week = %d, "
 "manufacture_year = %d, " "display_name = %s, " "speaker_flag = %d, "
 "audio_mode_count = %d\n", __func__, sink->edid_caps.manufacturer_id
, sink->edid_caps.product_id, sink->edid_caps.serial_number
, sink->edid_caps.manufacture_week, sink->edid_caps.manufacture_year
, sink->edid_caps.display_name, sink->edid_caps.speaker_flags
, sink->edid_caps.audio_mode_count)
	sink->edid_caps.display_name,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: " "manufacturer_id = %X, "
 "product_id = %X, " "serial_number = %X, " "manufacture_week = %d, "
 "manufacture_year = %d, " "display_name = %s, " "speaker_flag = %d, "
 "audio_mode_count = %d\n", __func__, sink->edid_caps.manufacturer_id
, sink->edid_caps.product_id, sink->edid_caps.serial_number
, sink->edid_caps.manufacture_week, sink->edid_caps.manufacture_year
, sink->edid_caps.display_name, sink->edid_caps.speaker_flags
, sink->edid_caps.audio_mode_count)
	sink->edid_caps.speaker_flags,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: " "manufacturer_id = %X, "
 "product_id = %X, " "serial_number = %X, " "manufacture_week = %d, "
 "manufacture_year = %d, " "display_name = %s, " "speaker_flag = %d, "
 "audio_mode_count = %d\n", __func__, sink->edid_caps.manufacturer_id
, sink->edid_caps.product_id, sink->edid_caps.serial_number
, sink->edid_caps.manufacture_week, sink->edid_caps.manufacture_year
, sink->edid_caps.display_name, sink->edid_caps.speaker_flags
, sink->edid_caps.audio_mode_count)
	sink->edid_caps.audio_mode_count)___drm_dbg(((void *)0), DRM_UT_KMS, "%s: " "manufacturer_id = %X, "
 "product_id = %X, " "serial_number = %X, " "manufacture_week = %d, "
 "manufacture_year = %d, " "display_name = %s, " "speaker_flag = %d, "
 "audio_mode_count = %d\n", __func__, sink->edid_caps.manufacturer_id
, sink->edid_caps.product_id, sink->edid_caps.serial_number
, sink->edid_caps.manufacture_week, sink->edid_caps.manufacture_year
, sink->edid_caps.display_name, sink->edid_caps.speaker_flags
, sink->edid_caps.audio_mode_count);

for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
	DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "___drm_dbg(((void *)0), DRM_UT_KMS, "%s: mode number = %d, " "format_code = %d, "
 "channel_count = %d, " "sample_rate = %d, " "sample_size = %d\n"
, __func__, i, sink->edid_caps.audio_modes[i].format_code,
 sink->edid_caps.audio_modes[i].channel_count, sink->edid_caps
.audio_modes[i].sample_rate, sink->edid_caps.audio_modes[i
].sample_size)
		"format_code = %d, "___drm_dbg(((void *)0), DRM_UT_KMS, "%s: mode number = %d, " "format_code = %d, "
 "channel_count = %d, " "sample_rate = %d, " "sample_size = %d\n"
, __func__, i, sink->edid_caps.audio_modes[i].format_code,
 sink->edid_caps.audio_modes[i].channel_count, sink->edid_caps
.audio_modes[i].sample_rate, sink->edid_caps.audio_modes[i
].sample_size)
		"channel_count = %d, "___drm_dbg(((void *)0), DRM_UT_KMS, "%s: mode number = %d, " "format_code = %d, "
 "channel_count = %d, " "sample_rate = %d, " "sample_size = %d\n"
, __func__, i, sink->edid_caps.audio_modes[i].format_code,
 sink->edid_caps.audio_modes[i].channel_count, sink->edid_caps
.audio_modes[i].sample_rate, sink->edid_caps.audio_modes[i
].sample_size)
		"sample_rate = %d, "___drm_dbg(((void *)0), DRM_UT_KMS, "%s: mode number = %d, " "format_code = %d, "
 "channel_count = %d, " "sample_rate = %d, " "sample_size = %d\n"
, __func__, i, sink->edid_caps.audio_modes[i].format_code,
 sink->edid_caps.audio_modes[i].channel_count, sink->edid_caps
.audio_modes[i].sample_rate, sink->edid_caps.audio_modes[i
].sample_size)
		"sample_size = %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "%s: mode number = %d, " "format_code = %d, "
 "channel_count = %d, " "sample_rate = %d, " "sample_size = %d\n"
, __func__, i, sink->edid_caps.audio_modes[i].format_code,
 sink->edid_caps.audio_modes[i].channel_count, sink->edid_caps
.audio_modes[i].sample_rate, sink->edid_caps.audio_modes[i
].sample_size)
		__func__,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: mode number = %d, " "format_code = %d, "
 "channel_count = %d, " "sample_rate = %d, " "sample_size = %d\n"
, __func__, i, sink->edid_caps.audio_modes[i].format_code,
 sink->edid_caps.audio_modes[i].channel_count, sink->edid_caps
.audio_modes[i].sample_rate, sink->edid_caps.audio_modes[i
].sample_size)
		i,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: mode number = %d, " "format_code = %d, "
 "channel_count = %d, " "sample_rate = %d, " "sample_size = %d\n"
, __func__, i, sink->edid_caps.audio_modes[i].format_code,
 sink->edid_caps.audio_modes[i].channel_count, sink->edid_caps
.audio_modes[i].sample_rate, sink->edid_caps.audio_modes[i
].sample_size)
		sink->edid_caps.audio_modes[i].format_code,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: mode number = %d, " "format_code = %d, "
 "channel_count = %d, " "sample_rate = %d, " "sample_size = %d\n"
, __func__, i, sink->edid_caps.audio_modes[i].format_code,
 sink->edid_caps.audio_modes[i].channel_count, sink->edid_caps
.audio_modes[i].sample_rate, sink->edid_caps.audio_modes[i
].sample_size)
		sink->edid_caps.audio_modes[i].channel_count,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: mode number = %d, " "format_code = %d, "
 "channel_count = %d, " "sample_rate = %d, " "sample_size = %d\n"
, __func__, i, sink->edid_caps.audio_modes[i].format_code,
 sink->edid_caps.audio_modes[i].channel_count, sink->edid_caps
.audio_modes[i].sample_rate, sink->edid_caps.audio_modes[i
].sample_size)
		sink->edid_caps.audio_modes[i].sample_rate,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: mode number = %d, " "format_code = %d, "
 "channel_count = %d, " "sample_rate = %d, " "sample_size = %d\n"
, __func__, i, sink->edid_caps.audio_modes[i].format_code,
 sink->edid_caps.audio_modes[i].channel_count, sink->edid_caps
.audio_modes[i].sample_rate, sink->edid_caps.audio_modes[i
].sample_size)
		sink->edid_caps.audio_modes[i].sample_size)___drm_dbg(((void *)0), DRM_UT_KMS, "%s: mode number = %d, " "format_code = %d, "
 "channel_count = %d, " "sample_rate = %d, " "sample_size = %d\n"
, __func__, i, sink->edid_caps.audio_modes[i].format_code,
 sink->edid_caps.audio_modes[i].channel_count, sink->edid_caps
.audio_modes[i].sample_rate, sink->edid_caps.audio_modes[i
].sample_size);
}

if (link->connector_signal == SIGNAL_TYPE_EDP) {
	/* Init dc_panel_config by HW config */
	if (dc_ctx->dc->res_pool->funcs->get_panel_config_defaults)
		dc_ctx->dc->res_pool->funcs->get_panel_config_defaults(&link->panel_config);
	/* Pickup base DM settings */
	dm_helpers_init_panel_settings(dc_ctx, &link->panel_config, sink);
	// Override dc_panel_config if system has specific settings
	dm_helpers_override_panel_settings(dc_ctx, &link->panel_config);
}

} else {
/* From Connected-to-Disconnected. */
link->type = dc_connection_none;
sink_caps.signal = SIGNAL_TYPE_NONE;
/* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
 *  is not cleared. If we emulate a DP signal on this connection, it thinks
 *  the dongle is still there and limits the number of modes we can emulate.
 *  Clear dongle_max_pix_clk on disconnect to fix this
 */
link->dongle_max_pix_clk = 0;

dc_link_clear_dprx_states(link);
dp_trace_reset(link);
}

LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n"
, link->link_index, sink, (sink_caps.signal == SIGNAL_TYPE_NONE
 ? "Disconnected" : "Connected"), prev_sink, same_edid)
  link->link_index, sink,___drm_dbg(((void *)0), DRM_UT_KMS, "link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n"
, link->link_index, sink, (sink_caps.signal == SIGNAL_TYPE_NONE
 ? "Disconnected" : "Connected"), prev_sink, same_edid)
  (sink_caps.signal ==___drm_dbg(((void *)0), DRM_UT_KMS, "link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n"
, link->link_index, sink, (sink_caps.signal == SIGNAL_TYPE_NONE
 ? "Disconnected" : "Connected"), prev_sink, same_edid)
   SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),___drm_dbg(((void *)0), DRM_UT_KMS, "link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n"
, link->link_index, sink, (sink_caps.signal == SIGNAL_TYPE_NONE
 ? "Disconnected" : "Connected"), prev_sink, same_edid)
  prev_sink, same_edid)___drm_dbg(((void *)0), DRM_UT_KMS, "link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n"
, link->link_index, sink, (sink_caps.signal == SIGNAL_TYPE_NONE
 ? "Disconnected" : "Connected"), prev_sink, same_edid);

if (prev_sink)
dc_sink_release(prev_sink);

return true1;
1352}

1354bool_Bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
1355{
bool_Bool is_local_sink_detect_success;
bool_Bool is_delegated_to_mst_top_mgr = false0;
enum dc_connection_type pre_link_type = link->type;

DC_LOGGER_INIT(link->ctx->logger);

is_local_sink_detect_success = detect_link_and_local_sink(link, reason);

if (is_local_sink_detect_success && link->local_sink)
verify_link_capability(link, link->local_sink, reason);

if (is_local_sink_detect_success && link->local_sink &&
	dc_is_dp_signal(link->local_sink->sink_signal) &&
	link->dpcd_caps.is_mst_capable)
is_delegated_to_mst_top_mgr = discover_dp_mst_topology(link, reason);

DC_LOG_DC("%s: link_index=%d is_local_sink_detect_success=%d pre_link_type=%d link_type=%d\n", __func__,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: link_index=%d is_local_sink_detect_success=%d pre_link_type=%d link_type=%d\n"
, __func__, link->link_index, is_local_sink_detect_success
, pre_link_type, link->type)
 link->link_index, is_local_sink_detect_success, pre_link_type, link->type)___drm_dbg(((void *)0), DRM_UT_KMS, "%s: link_index=%d is_local_sink_detect_success=%d pre_link_type=%d link_type=%d\n"
, __func__, link->link_index, is_local_sink_detect_success
, pre_link_type, link->type);


if (is_local_sink_detect_success &&
	pre_link_type == dc_connection_mst_branch &&
	link->type != dc_connection_mst_branch)
is_delegated_to_mst_top_mgr = reset_cur_dp_mst_topology(link);

return is_local_sink_detect_success && !is_delegated_to_mst_top_mgr;
1382}

1384bool_Bool dc_link_get_hpd_state(struct dc_link *dc_link)
1385{
uint32_t state;

dal_gpio_lock_pin(dc_link->hpd_gpio);
dal_gpio_get_value(dc_link->hpd_gpio, &state);
dal_gpio_unlock_pin(dc_link->hpd_gpio);

return state;
1393}

1395static enum hpd_source_id get_hpd_line(struct dc_link *link)
1396{
struct gpio *hpd;
enum hpd_source_id hpd_id;

hpd_id = HPD_SOURCEID_UNKNOWN;

hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
	   link->ctx->gpio_service);

if (hpd) {
switch (dal_irq_get_source(hpd)) {
case DC_IRQ_SOURCE_HPD1:
	hpd_id = HPD_SOURCEID1;
break;
case DC_IRQ_SOURCE_HPD2:
	hpd_id = HPD_SOURCEID2;
break;
case DC_IRQ_SOURCE_HPD3:
	hpd_id = HPD_SOURCEID3;
break;
case DC_IRQ_SOURCE_HPD4:
	hpd_id = HPD_SOURCEID4;
break;
case DC_IRQ_SOURCE_HPD5:
	hpd_id = HPD_SOURCEID5;
break;
case DC_IRQ_SOURCE_HPD6:
	hpd_id = HPD_SOURCEID6;
break;
default:
	BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__
, 1426); do {} while (0); } while (0);
break;
}

dal_gpio_destroy_irq(&hpd);
}

return hpd_id;
1434}

1436static enum channel_id get_ddc_line(struct dc_link *link)
1437{
struct ddc *ddc;
enum channel_id channel;

channel = CHANNEL_ID_UNKNOWN;

ddc = dal_ddc_service_get_ddc_pin(link->ddc);

if (ddc) {
switch (dal_ddc_get_line(ddc)) {
case GPIO_DDC_LINE_DDC1:
	channel = CHANNEL_ID_DDC1;
	break;
case GPIO_DDC_LINE_DDC2:
	channel = CHANNEL_ID_DDC2;
	break;
case GPIO_DDC_LINE_DDC3:
	channel = CHANNEL_ID_DDC3;
	break;
case GPIO_DDC_LINE_DDC4:
	channel = CHANNEL_ID_DDC4;
	break;
case GPIO_DDC_LINE_DDC5:
	channel = CHANNEL_ID_DDC5;
	break;
case GPIO_DDC_LINE_DDC6:
	channel = CHANNEL_ID_DDC6;
	break;
case GPIO_DDC_LINE_DDC_VGA:
	channel = CHANNEL_ID_DDC_VGA;
	break;
case GPIO_DDC_LINE_I2C_PAD:
	channel = CHANNEL_ID_I2C_PAD;
	break;
default:
	BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__
, 1472); do {} while (0); } while (0);
	break;
}
}

return channel;
1478}

1480static enum transmitter translate_encoder_to_transmitter(struct graphics_object_id encoder)
1481{
switch (encoder.id) {
case ENCODER_ID_INTERNAL_UNIPHY:
switch (encoder.enum_id) {
case ENUM_ID_1:
	return TRANSMITTER_UNIPHY_A;
case ENUM_ID_2:
	return TRANSMITTER_UNIPHY_B;
default:
	return TRANSMITTER_UNKNOWN;
}
break;
case ENCODER_ID_INTERNAL_UNIPHY1:
switch (encoder.enum_id) {
case ENUM_ID_1:
	return TRANSMITTER_UNIPHY_C;
case ENUM_ID_2:
	return TRANSMITTER_UNIPHY_D;
default:
	return TRANSMITTER_UNKNOWN;
}
break;
case ENCODER_ID_INTERNAL_UNIPHY2:
switch (encoder.enum_id) {
case ENUM_ID_1:
	return TRANSMITTER_UNIPHY_E;
case ENUM_ID_2:
	return TRANSMITTER_UNIPHY_F;
default:
	return TRANSMITTER_UNKNOWN;
}
break;
case ENCODER_ID_INTERNAL_UNIPHY3:
switch (encoder.enum_id) {
case ENUM_ID_1:
	return TRANSMITTER_UNIPHY_G;
default:
	return TRANSMITTER_UNKNOWN;
}
break;
case ENCODER_ID_EXTERNAL_NUTMEG:
switch (encoder.enum_id) {
case ENUM_ID_1:
	return TRANSMITTER_NUTMEG_CRT;
default:
	return TRANSMITTER_UNKNOWN;
}
break;
case ENCODER_ID_EXTERNAL_TRAVIS:
switch (encoder.enum_id) {
case ENUM_ID_1:
	return TRANSMITTER_TRAVIS_CRT;
case ENUM_ID_2:
	return TRANSMITTER_TRAVIS_LCD;
default:
	return TRANSMITTER_UNKNOWN;
}
break;
default:
return TRANSMITTER_UNKNOWN;
}
1542}

1544static bool_Bool dc_link_construct_legacy(struct dc_link *link,
		     const struct link_init_data *init_params)
1546{
uint8_t i;
struct ddc_service_init_data ddc_service_init_data = { 0 };
struct dc_context *dc_ctx = init_params->ctx;
struct encoder_init_data enc_init_data = { 0 };
struct panel_cntl_init_data panel_cntl_init_data = { 0 };
struct integrated_info *info;
struct dc_bios *bios = init_params->dc->ctx->dc_bios;
const struct dc_vbios_funcs *bp_funcs = bios->funcs;
struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };

DC_LOGGER_INIT(dc_ctx->logger);

info = kzalloc(sizeof(*info), GFP_KERNEL(0x0001 | 0x0004));
if (!info)
goto create_fail;

link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;

link->link_status.dpcd_caps = &link->dpcd_caps;

link->dc = init_params->dc;
link->ctx = dc_ctx;
link->link_index = init_params->link_index;

memset(&link->preferred_training_settings, 0,__builtin_memset((&link->preferred_training_settings),
 (0), (sizeof(struct dc_link_training_overrides)))
      sizeof(struct dc_link_training_overrides))__builtin_memset((&link->preferred_training_settings),
 (0), (sizeof(struct dc_link_training_overrides)));
memset(&link->preferred_link_setting, 0,__builtin_memset((&link->preferred_link_setting), (0),
 (sizeof(struct dc_link_settings)))
      sizeof(struct dc_link_settings))__builtin_memset((&link->preferred_link_setting), (0),
 (sizeof(struct dc_link_settings)));

link->link_id =
bios->funcs->get_connector_id(bios, init_params->connector_index);

link->ep_type = DISPLAY_ENDPOINT_PHY;

DC_LOG_DC("BIOS object table - link_id: %d", link->link_id.id)___drm_dbg(((void *)0), DRM_UT_KMS, "BIOS object table - link_id: %d"
, link->link_id.id);

if (bios->funcs->get_disp_connector_caps_info) {
bios->funcs->get_disp_connector_caps_info(bios, link->link_id, &disp_connect_caps_info);
link->is_internal_display = disp_connect_caps_info.INTERNAL_DISPLAY;
DC_LOG_DC("BIOS object table - is_internal_display: %d", link->is_internal_display)___drm_dbg(((void *)0), DRM_UT_KMS, "BIOS object table - is_internal_display: %d"
, link->is_internal_display);
}

if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n"
, __func__, init_params->connector_index, link->link_id
.type, OBJECT_TYPE_CONNECTOR)
		     __func__, init_params->connector_index,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n"
, __func__, init_params->connector_index, link->link_id
.type, OBJECT_TYPE_CONNECTOR)
		     link->link_id.type, OBJECT_TYPE_CONNECTOR)___drm_dbg(((void *)0), DRM_UT_KMS, "%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n"
, __func__, init_params->connector_index, link->link_id
.type, OBJECT_TYPE_CONNECTOR);
goto create_fail;
}

if (link->dc->res_pool->funcs->link_init)
link->dc->res_pool->funcs->link_init(link);

link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
		      link->ctx->gpio_service);

if (link->hpd_gpio) {
dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
dal_gpio_unlock_pin(link->hpd_gpio);
link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);

DC_LOG_DC("BIOS object table - hpd_gpio id: %d", link->hpd_gpio->id)___drm_dbg(((void *)0), DRM_UT_KMS, "BIOS object table - hpd_gpio id: %d"
, link->hpd_gpio->id);
DC_LOG_DC("BIOS object table - hpd_gpio en: %d", link->hpd_gpio->en)___drm_dbg(((void *)0), DRM_UT_KMS, "BIOS object table - hpd_gpio en: %d"
, link->hpd_gpio->en);
}

switch (link->link_id.id) {
case CONNECTOR_ID_HDMI_TYPE_A:
link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;

break;
case CONNECTOR_ID_SINGLE_LINK_DVID:
case CONNECTOR_ID_SINGLE_LINK_DVII:
link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
break;
case CONNECTOR_ID_DUAL_LINK_DVID:
case CONNECTOR_ID_DUAL_LINK_DVII:
link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
break;
case CONNECTOR_ID_DISPLAY_PORT:
case CONNECTOR_ID_USBC:
link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;

if (link->hpd_gpio)
	link->irq_source_hpd_rx =
			dal_irq_get_rx_source(link->hpd_gpio);

break;
case CONNECTOR_ID_EDP:
link->connector_signal = SIGNAL_TYPE_EDP;

if (link->hpd_gpio) {
	if (!link->dc->config.allow_edp_hotplug_detection)
		link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;

	switch (link->dc->config.allow_edp_hotplug_detection) {
	case HPD_EN_FOR_ALL_EDP:
		link->irq_source_hpd_rx =
				dal_irq_get_rx_source(link->hpd_gpio);
		break;
	case HPD_EN_FOR_PRIMARY_EDP_ONLY:
		if (link->link_index == 0)
			link->irq_source_hpd_rx =
				dal_irq_get_rx_source(link->hpd_gpio);
		else
			link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
		break;
	case HPD_EN_FOR_SECONDARY_EDP_ONLY:
		if (link->link_index == 1)
			link->irq_source_hpd_rx =
				dal_irq_get_rx_source(link->hpd_gpio);
		else
			link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
		break;
	default:
		link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
		break;
	}
}

break;
case CONNECTOR_ID_LVDS:
link->connector_signal = SIGNAL_TYPE_LVDS;
break;
default:
DC_LOG_WARNING("Unsupported Connector type:%d!\n",printk("\0014" "[" "drm" "] " "Unsupported Connector type:%d!\n"
, link->link_id.id)
	       link->link_id.id)printk("\0014" "[" "drm" "] " "Unsupported Connector type:%d!\n"
, link->link_id.id);
goto create_fail;
}

/* TODO: #DAL3 Implement id to str function.*/
LINK_INFO("Connector[%d] description:"___drm_dbg(((void *)0), DRM_UT_KMS, "Connector[%d] description:"
 "signal %d\n", init_params->connector_index, link->connector_signal
)
  "signal %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "Connector[%d] description:"
 "signal %d\n", init_params->connector_index, link->connector_signal
)
  init_params->connector_index,___drm_dbg(((void *)0), DRM_UT_KMS, "Connector[%d] description:"
 "signal %d\n", init_params->connector_index, link->connector_signal
)
  link->connector_signal)___drm_dbg(((void *)0), DRM_UT_KMS, "Connector[%d] description:"
 "signal %d\n", init_params->connector_index, link->connector_signal
);

ddc_service_init_data.ctx = link->ctx;
ddc_service_init_data.id = link->link_id;
ddc_service_init_data.link = link;
link->ddc = dal_ddc_service_create(&ddc_service_init_data);

if (!link->ddc) {
DC_ERROR("Failed to create ddc_service!\n")do { (void)(dc_ctx); __drm_err("Failed to create ddc_service!\n"
); } while (0);
goto ddc_create_fail;
}

if (!link->ddc->ddc_pin) {
DC_ERROR("Failed to get I2C info for connector!\n")do { (void)(dc_ctx); __drm_err("Failed to get I2C info for connector!\n"
); } while (0);
goto ddc_create_fail;
}

link->ddc_hw_inst =
dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));


if (link->dc->res_pool->funcs->panel_cntl_create &&
(link->link_id.id == CONNECTOR_ID_EDP ||
	link->link_id.id == CONNECTOR_ID_LVDS)) {
panel_cntl_init_data.ctx = dc_ctx;
panel_cntl_init_data.inst =
	panel_cntl_init_data.ctx->dc_edp_id_count;
link->panel_cntl =
	link->dc->res_pool->funcs->panel_cntl_create(
						&panel_cntl_init_data);
panel_cntl_init_data.ctx->dc_edp_id_count++;

if (link->panel_cntl == NULL((void *)0)) {
	DC_ERROR("Failed to create link panel_cntl!\n")do { (void)(dc_ctx); __drm_err("Failed to create link panel_cntl!\n"
); } while (0);
	goto panel_cntl_create_fail;
}
}

enc_init_data.ctx = dc_ctx;
bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,
	      &enc_init_data.encoder);
enc_init_data.connector = link->link_id;
enc_init_data.channel = get_ddc_line(link);
enc_init_data.hpd_source = get_hpd_line(link);

link->hpd_src = enc_init_data.hpd_source;

enc_init_data.transmitter =
translate_encoder_to_transmitter(enc_init_data.encoder);
link->link_enc =
link->dc->res_pool->funcs->link_enc_create(dc_ctx, &enc_init_data);

if (!link->link_enc) {
DC_ERROR("Failed to create link encoder!\n")do { (void)(dc_ctx); __drm_err("Failed to create link encoder!\n"
); } while (0);
goto link_enc_create_fail;
}

DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link->link_enc->features.flags.bits.DP_IS_USB_C)___drm_dbg(((void *)0), DRM_UT_KMS, "BIOS object table - DP_IS_USB_C: %d"
, link->link_enc->features.flags.bits.DP_IS_USB_C);
DC_LOG_DC("BIOS object table - IS_DP2_CAPABLE: %d", link->link_enc->features.flags.bits.IS_DP2_CAPABLE)___drm_dbg(((void *)0), DRM_UT_KMS, "BIOS object table - IS_DP2_CAPABLE: %d"
, link->link_enc->features.flags.bits.IS_DP2_CAPABLE);

/* Update link encoder tracking variables. These are used for the dynamic
* assignment of link encoders to streams.
*/
link->eng_id = link->link_enc->preferred_engine;
link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc;
link->dc->res_pool->dig_link_enc_count++;

link->link_enc_hw_inst = link->link_enc->transmitter;

for (i = 0; i < 4; i++) {
if (bp_funcs->get_device_tag(dc_ctx->dc_bios,
			     link->link_id, i,
			     &link->device_tag) != BP_RESULT_OK) {
	DC_ERROR("Failed to find device tag!\n")do { (void)(dc_ctx); __drm_err("Failed to find device tag!\n"
); } while (0);
	goto device_tag_fail;
}

/* Look for device tag that matches connector signal,
 * CRT for rgb, LCD for other supported signal tyes
 */
if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios,
				      link->device_tag.dev_id))
	continue;
if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT &&
    link->connector_signal != SIGNAL_TYPE_RGB)
	continue;
if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD &&
    link->connector_signal == SIGNAL_TYPE_RGB)
	continue;

DC_LOG_DC("BIOS object table - device_tag.acpi_device: %d", link->device_tag.acpi_device)___drm_dbg(((void *)0), DRM_UT_KMS, "BIOS object table - device_tag.acpi_device: %d"
, link->device_tag.acpi_device);
DC_LOG_DC("BIOS object table - device_tag.dev_id.device_type: %d", link->device_tag.dev_id.device_type)___drm_dbg(((void *)0), DRM_UT_KMS, "BIOS object table - device_tag.dev_id.device_type: %d"
, link->device_tag.dev_id.device_type);
DC_LOG_DC("BIOS object table - device_tag.dev_id.enum_id: %d", link->device_tag.dev_id.enum_id)___drm_dbg(((void *)0), DRM_UT_KMS, "BIOS object table - device_tag.dev_id.enum_id: %d"
, link->device_tag.dev_id.enum_id);
break;
}

if (bios->integrated_info)
memcpy(info, bios->integrated_info, sizeof(*info))__builtin_memcpy((info), (bios->integrated_info), (sizeof(
*info)));

/* Look for channel mapping corresponding to connector and device tag */
for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH7; i++) {
struct external_display_path *path =
	&info->ext_disp_conn_info.path[i];

if (path->device_connector_id.enum_id == link->link_id.enum_id &&
    path->device_connector_id.id == link->link_id.id &&
    path->device_connector_id.type == link->link_id.type) {
	if (link->device_tag.acpi_device != 0 &&
	    path->device_acpi_enum == link->device_tag.acpi_device) {
		link->ddi_channel_mapping = path->channel_mapping;
		link->chip_caps = path->caps;
		DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw)___drm_dbg(((void *)0), DRM_UT_KMS, "BIOS object table - ddi_channel_mapping: 0x%04X"
, link->ddi_channel_mapping.raw);
		DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps)___drm_dbg(((void *)0), DRM_UT_KMS, "BIOS object table - chip_caps: %d"
, link->chip_caps);
	} else if (path->device_tag ==
		   link->device_tag.dev_id.raw_device_tag) {
		link->ddi_channel_mapping = path->channel_mapping;
		link->chip_caps = path->caps;
		DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw)___drm_dbg(((void *)0), DRM_UT_KMS, "BIOS object table - ddi_channel_mapping: 0x%04X"
, link->ddi_channel_mapping.raw);
		DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps)___drm_dbg(((void *)0), DRM_UT_KMS, "BIOS object table - chip_caps: %d"
, link->chip_caps);
	}

	if (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) {
		link->bios_forced_drive_settings.VOLTAGE_SWING =
				(info->ext_disp_conn_info.fixdpvoltageswing & 0x3);
		link->bios_forced_drive_settings.PRE_EMPHASIS =
				((info->ext_disp_conn_info.fixdpvoltageswing >> 2) & 0x3);
	}

	break;
}
}

if (bios->funcs->get_atom_dc_golden_table)
bios->funcs->get_atom_dc_golden_table(bios);

/*
* TODO check if GPIO programmed correctly
*
* If GPIO isn't programmed correctly HPD might not rise or drain
* fast enough, leading to bounces.
*/
program_hpd_filter(link);

link->psr_settings.psr_vtotal_control_support = false0;
link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;

DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__)___drm_dbg(((void *)0), DRM_UT_KMS, "BIOS object table - %s finished successfully.\n"
, __func__);
kfree(info);
return true1;
1829device_tag_fail:
link->link_enc->funcs->destroy(&link->link_enc);
1831link_enc_create_fail:
if (link->panel_cntl != NULL((void *)0))
link->panel_cntl->funcs->destroy(&link->panel_cntl);
1834panel_cntl_create_fail:
dal_ddc_service_destroy(&link->ddc);
1836ddc_create_fail:
1837create_fail:

if (link->hpd_gpio) {
dal_gpio_destroy_irq(&link->hpd_gpio);
link->hpd_gpio = NULL((void *)0);
}

DC_LOG_DC("BIOS object table - %s failed.\n", __func__)___drm_dbg(((void *)0), DRM_UT_KMS, "BIOS object table - %s failed.\n"
, __func__);
kfree(info);

return false0;
1848}

1850static bool_Bool dc_link_construct_dpia(struct dc_link *link,
		   const struct link_init_data *init_params)
1852{
struct ddc_service_init_data ddc_service_init_data = { 0 };
struct dc_context *dc_ctx = init_params->ctx;

DC_LOGGER_INIT(dc_ctx->logger);

/* Initialized irq source for hpd and hpd rx */
link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
link->link_status.dpcd_caps = &link->dpcd_caps;

link->dc = init_params->dc;
link->ctx = dc_ctx;
link->link_index = init_params->link_index;

memset(&link->preferred_training_settings, 0,__builtin_memset((&link->preferred_training_settings),
 (0), (sizeof(struct dc_link_training_overrides)))
      sizeof(struct dc_link_training_overrides))__builtin_memset((&link->preferred_training_settings),
 (0), (sizeof(struct dc_link_training_overrides)));
memset(&link->preferred_link_setting, 0,__builtin_memset((&link->preferred_link_setting), (0),
 (sizeof(struct dc_link_settings)))
      sizeof(struct dc_link_settings))__builtin_memset((&link->preferred_link_setting), (0),
 (sizeof(struct dc_link_settings)));

/* Dummy Init for linkid */
link->link_id.type = OBJECT_TYPE_CONNECTOR;
link->link_id.id = CONNECTOR_ID_DISPLAY_PORT;
link->link_id.enum_id = ENUM_ID_1 + init_params->connector_index;
link->is_internal_display = false0;
link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
LINK_INFO("Connector[%d] description:signal %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "Connector[%d] description:signal %d\n"
, init_params->connector_index, link->connector_signal)
  init_params->connector_index,___drm_dbg(((void *)0), DRM_UT_KMS, "Connector[%d] description:signal %d\n"
, init_params->connector_index, link->connector_signal)
  link->connector_signal)___drm_dbg(((void *)0), DRM_UT_KMS, "Connector[%d] description:signal %d\n"
, init_params->connector_index, link->connector_signal);

link->ep_type = DISPLAY_ENDPOINT_USB4_DPIA;
link->is_dig_mapping_flexible = true1;

/* TODO: Initialize link : funcs->link_init */

ddc_service_init_data.ctx = link->ctx;
ddc_service_init_data.id = link->link_id;
ddc_service_init_data.link = link;
/* Set indicator for dpia link so that ddc won't be created */
ddc_service_init_data.is_dpia_link = true1;

link->ddc = dal_ddc_service_create(&ddc_service_init_data);
if (!link->ddc) {
DC_ERROR("Failed to create ddc_service!\n")do { (void)(dc_ctx); __drm_err("Failed to create ddc_service!\n"
); } while (0);
goto ddc_create_fail;
}

/* Set dpia port index : 0 to number of dpia ports */
link->ddc_hw_inst = init_params->connector_index;

/* TODO: Create link encoder */

link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;

/* Some docks seem to NAK I2C writes to segment pointer with mot=0. */
link->wa_flags.dp_mot_reset_segment = true1;

return true1;

1911ddc_create_fail:
return false0;
1913}

1915static bool_Bool dc_link_construct(struct dc_link *link,
	      const struct link_init_data *init_params)
1917{
/* Handle dpia case */
if (init_params->is_dpia_link)
return dc_link_construct_dpia(link, init_params);
else
return dc_link_construct_legacy(link, init_params);
1923}
1924/*******************************************************************************
* Public functions
******************************************************************************/
1927struct dc_link *link_create(const struct link_init_data *init_params)
1928{
struct dc_link *link =
	kzalloc(sizeof(*link), GFP_KERNEL(0x0001 | 0x0004));

if (NULL((void *)0) == link)
goto alloc_fail;

if (false0 == dc_link_construct(link, init_params))
goto construct_fail;

return link;

1940construct_fail:
kfree(link);

1943alloc_fail:
return NULL((void *)0);
1945}

1947void link_destroy(struct dc_link **link)
1948{
dc_link_destruct(*link);
kfree(*link);
*link = NULL((void *)0);
1952}

1954static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1955{
struct dc_stream_state *stream = pipe_ctx->stream;

if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) {
struct dc_link *link = stream->link;
union down_spread_ctrl old_downspread;
union down_spread_ctrl new_downspread;

memset(&old_downspread, 0, sizeof(old_downspread))__builtin_memset((&old_downspread), (0), (sizeof(old_downspread
)));

core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL0x107,
		&old_downspread.raw, sizeof(old_downspread));

new_downspread.raw = old_downspread.raw;

new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
		(stream->ignore_msa_timing_param) ? 1 : 0;

if (new_downspread.raw != old_downspread.raw) {
	core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL0x107,
		&new_downspread.raw, sizeof(new_downspread));
}

} else {
dm_helpers_mst_enable_stream_features(stream);
}
1981}

1983static enum dc_status enable_link_dp(struct dc_state *state,
		     struct pipe_ctx *pipe_ctx)
1985{
struct dc_stream_state *stream = pipe_ctx->stream;
enum dc_status status;
bool_Bool skip_video_pattern;
struct dc_link *link = stream->link;
const struct dc_link_settings *link_settings =
	&pipe_ctx->link_config.dp_link_settings;
bool_Bool fec_enable;
int i;
bool_Bool apply_seamless_boot_optimization = false0;
uint32_t bl_oled_enable_delay = 50; // in ms
uint32_t post_oui_delay = 30; // 30ms
/* Reduce link bandwidth between failed link training attempts. */
bool_Bool do_fallback = false0;

// check for seamless boot
for (i = 0; i < state->stream_count; i++) {
if (state->streams[i]->apply_seamless_boot_optimization) {
	apply_seamless_boot_optimization = true1;
	break;
}
}

/* Train with fallback when enabling DPIA link. Conventional links are
* trained with fallback during sink detection.
*/
if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
do_fallback = true1;

/*
* Temporary w/a to get DP2.0 link rates to work with SST.
* TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved.
*/
if (dp_get_link_encoding_format(link_settings) == DP_128b_132b_ENCODING &&
	pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
	link->dc->debug.set_mst_en_for_sst) {
dp_enable_mst_on_sink(link, true1);
}

if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
/*in case it is not on*/
if (!link->dc->config.edp_no_power_sequencing)
	link->dc->hwss.edp_power_control(link, true1);
link->dc->hwss.edp_wait_for_hpd_ready(link, true1);
}

if (dp_get_link_encoding_format(link_settings) == DP_128b_132b_ENCODING) {
/* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */
} else {
pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
		link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
if (state->clk_mgr && !apply_seamless_boot_optimization)
	state->clk_mgr->funcs->update_clocks(state->clk_mgr,
			state, false0);
}

// during mode switch we do DP_SET_POWER off then on, and OUI is lost
dpcd_set_source_specific_data(link);
if (link->dpcd_sink_ext_caps.raw != 0) {
post_oui_delay += link->panel_config.pps.extra_post_OUI_ms;
drm_msleep(post_oui_delay)mdelay(post_oui_delay);
}

// similarly, mode switch can cause loss of cable ID
dpcd_write_cable_id_to_dprx(link);

skip_video_pattern = true1;

if (link_settings->link_rate == LINK_RATE_LOW)
skip_video_pattern = false0;

if (perform_link_training_with_retries(link_settings,
			       skip_video_pattern,
			       LINK_TRAINING_ATTEMPTS4,
			       pipe_ctx,
			       pipe_ctx->stream->signal,
			       do_fallback)) {
status = DC_OK;
} else {
status = DC_FAIL_DP_LINK_TRAINING;
}

if (link->preferred_training_settings.fec_enable)
fec_enable = *link->preferred_training_settings.fec_enable;
else
fec_enable = true1;

if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING)
dp_set_fec_enable(link, fec_enable);

// during mode set we do DP_SET_POWER off then on, aux writes are lost
if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
dc_link_set_default_brightness_aux(link); // TODO: use cached if known
if (link->dpcd_sink_ext_caps.bits.oled == 1)
	drm_msleep(bl_oled_enable_delay)mdelay(bl_oled_enable_delay);
dc_link_backlight_enable_aux(link, true1);
}

return status;
2086}

2088static enum dc_status enable_link_edp(
struct dc_state *state,
struct pipe_ctx *pipe_ctx)
2091{
return enable_link_dp(state, pipe_ctx);
2093}

2095static enum dc_status enable_link_dp_mst(
struct dc_state *state,
struct pipe_ctx *pipe_ctx)
2098{
struct dc_link *link = pipe_ctx->stream->link;
unsigned char mstm_cntl;

/* sink signal type after MST branch is MST. Multiple MST sinks
* share one link. Link DP PHY is enable or training only once.
*/
if (link->link_status.link_active)
return DC_OK;

/* clear payload table */
core_link_read_dpcd(link, DP_MSTM_CTRL0x111, &mstm_cntl, 1);
if (mstm_cntl & DP_MST_EN(1 << 0))
dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);

/* to make sure the pending down rep can be processed
* before enabling the link
*/
dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);

/* set the sink to MST mode before enabling the link */
dp_enable_mst_on_sink(link, true1);

return enable_link_dp(state, pipe_ctx);
2122}

2124void dc_link_blank_all_dp_displays(struct dc *dc)
2125{
unsigned int i;
uint8_t dpcd_power_state = '\0';
enum dc_status status = DC_ERROR_UNEXPECTED;

for (i = 0; i < dc->link_count; i++) {
if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) ||
	(dc->links[i]->priv == NULL((void *)0)) || (dc->links[i]->local_sink == NULL((void *)0)))
	continue;

/* DP 2.0 spec requires that we read LTTPR caps first */
dp_retrieve_lttpr_cap(dc->links[i]);
/* if any of the displays are lit up turn them off */
status = core_link_read_dpcd(dc->links[i], DP_SET_POWER0x600,
					&dpcd_power_state, sizeof(dpcd_power_state));

if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0)
	dc_link_blank_dp_stream(dc->links[i], true1);
}

2145}

2147void dc_link_blank_all_edp_displays(struct dc *dc)
2148{
unsigned int i;
uint8_t dpcd_power_state = '\0';
enum dc_status status = DC_ERROR_UNEXPECTED;

for (i = 0; i < dc->link_count; i++) {
if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) ||
	(!dc->links[i]->edp_sink_present))
	continue;

/* if any of the displays are lit up turn them off */
status = core_link_read_dpcd(dc->links[i], DP_SET_POWER0x600,
					&dpcd_power_state, sizeof(dpcd_power_state));

if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0)
	dc_link_blank_dp_stream(dc->links[i], true1);
}
2165}

2167void dc_link_blank_dp_stream(struct dc_link *link, bool_Bool hw_init)
2168{
unsigned int j;
struct dc  *dc = link->ctx->dc;
enum amd_signal_type signal = link->connector_signal;

if ((signal == SIGNAL_TYPE_EDP) ||
(signal == SIGNAL_TYPE_DISPLAY_PORT)) {
if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
	link->link_enc->funcs->get_dig_frontend &&
	link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
	unsigned int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc);

	if (fe != ENGINE_ID_UNKNOWN)
		for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
			if (fe == dc->res_pool->stream_enc[j]->id) {
				dc->res_pool->stream_enc[j]->funcs->dp_blank(link,
							dc->res_pool->stream_enc[j]);
				break;
			}
		}
}

if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init)
	dp_receiver_power_ctrl(link, false0);
}
2193}

2195static bool_Bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
enum engine_id eng_id,
struct ext_hdmi_settings *settings)
2198{
bool_Bool result = false0;
int i = 0;
struct integrated_info *integrated_info =
	pipe_ctx->stream->ctx->dc_bios->integrated_info;

if (integrated_info == NULL((void *)0))
return false0;

/*
* Get retimer settings from sbios for passing SI eye test for DCE11
* The setting values are varied based on board revision and port id
* Therefore the setting values of each ports is passed by sbios.
*/

// Check if current bios contains ext Hdmi settings
if (integrated_info->gpu_cap_info & 0x20) {
switch (eng_id) {
case ENGINE_ID_DIGA:
	settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
	settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
	settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
	memmove(settings->reg_settings,__builtin_memmove((settings->reg_settings), (integrated_info
->dp0_ext_hdmi_reg_settings), (sizeof(integrated_info->
dp0_ext_hdmi_reg_settings)))
			integrated_info->dp0_ext_hdmi_reg_settings,__builtin_memmove((settings->reg_settings), (integrated_info
->dp0_ext_hdmi_reg_settings), (sizeof(integrated_info->
dp0_ext_hdmi_reg_settings)))
			sizeof(integrated_info->dp0_ext_hdmi_reg_settings))__builtin_memmove((settings->reg_settings), (integrated_info
->dp0_ext_hdmi_reg_settings), (sizeof(integrated_info->
dp0_ext_hdmi_reg_settings)));
	memmove(settings->reg_settings_6g,__builtin_memmove((settings->reg_settings_6g), (integrated_info
->dp0_ext_hdmi_6g_reg_settings), (sizeof(integrated_info->
dp0_ext_hdmi_6g_reg_settings)))
			integrated_info->dp0_ext_hdmi_6g_reg_settings,__builtin_memmove((settings->reg_settings_6g), (integrated_info
->dp0_ext_hdmi_6g_reg_settings), (sizeof(integrated_info->
dp0_ext_hdmi_6g_reg_settings)))
			sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings))__builtin_memmove((settings->reg_settings_6g), (integrated_info
->dp0_ext_hdmi_6g_reg_settings), (sizeof(integrated_info->
dp0_ext_hdmi_6g_reg_settings)));
	result = true1;
	break;
case ENGINE_ID_DIGB:
	settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
	settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
	settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
	memmove(settings->reg_settings,__builtin_memmove((settings->reg_settings), (integrated_info
->dp1_ext_hdmi_reg_settings), (sizeof(integrated_info->
dp1_ext_hdmi_reg_settings)))
			integrated_info->dp1_ext_hdmi_reg_settings,__builtin_memmove((settings->reg_settings), (integrated_info
->dp1_ext_hdmi_reg_settings), (sizeof(integrated_info->
dp1_ext_hdmi_reg_settings)))
			sizeof(integrated_info->dp1_ext_hdmi_reg_settings))__builtin_memmove((settings->reg_settings), (integrated_info
->dp1_ext_hdmi_reg_settings), (sizeof(integrated_info->
dp1_ext_hdmi_reg_settings)));
	memmove(settings->reg_settings_6g,__builtin_memmove((settings->reg_settings_6g), (integrated_info
->dp1_ext_hdmi_6g_reg_settings), (sizeof(integrated_info->
dp1_ext_hdmi_6g_reg_settings)))
			integrated_info->dp1_ext_hdmi_6g_reg_settings,__builtin_memmove((settings->reg_settings_6g), (integrated_info
->dp1_ext_hdmi_6g_reg_settings), (sizeof(integrated_info->
dp1_ext_hdmi_6g_reg_settings)))
			sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings))__builtin_memmove((settings->reg_settings_6g), (integrated_info
->dp1_ext_hdmi_6g_reg_settings), (sizeof(integrated_info->
dp1_ext_hdmi_6g_reg_settings)));
	result = true1;
	break;
case ENGINE_ID_DIGC:
	settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
	settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
	settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
	memmove(settings->reg_settings,__builtin_memmove((settings->reg_settings), (integrated_info
->dp2_ext_hdmi_reg_settings), (sizeof(integrated_info->
dp2_ext_hdmi_reg_settings)))
			integrated_info->dp2_ext_hdmi_reg_settings,__builtin_memmove((settings->reg_settings), (integrated_info
->dp2_ext_hdmi_reg_settings), (sizeof(integrated_info->
dp2_ext_hdmi_reg_settings)))
			sizeof(integrated_info->dp2_ext_hdmi_reg_settings))__builtin_memmove((settings->reg_settings), (integrated_info
->dp2_ext_hdmi_reg_settings), (sizeof(integrated_info->
dp2_ext_hdmi_reg_settings)));
	memmove(settings->reg_settings_6g,__builtin_memmove((settings->reg_settings_6g), (integrated_info
->dp2_ext_hdmi_6g_reg_settings), (sizeof(integrated_info->
dp2_ext_hdmi_6g_reg_settings)))
			integrated_info->dp2_ext_hdmi_6g_reg_settings,__builtin_memmove((settings->reg_settings_6g), (integrated_info
->dp2_ext_hdmi_6g_reg_settings), (sizeof(integrated_info->
dp2_ext_hdmi_6g_reg_settings)))
			sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings))__builtin_memmove((settings->reg_settings_6g), (integrated_info
->dp2_ext_hdmi_6g_reg_settings), (sizeof(integrated_info->
dp2_ext_hdmi_6g_reg_settings)));
	result = true1;
	break;
case ENGINE_ID_DIGD:
	settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
	settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
	settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
	memmove(settings->reg_settings,__builtin_memmove((settings->reg_settings), (integrated_info
->dp3_ext_hdmi_reg_settings), (sizeof(integrated_info->
dp3_ext_hdmi_reg_settings)))
			integrated_info->dp3_ext_hdmi_reg_settings,__builtin_memmove((settings->reg_settings), (integrated_info
->dp3_ext_hdmi_reg_settings), (sizeof(integrated_info->
dp3_ext_hdmi_reg_settings)))
			sizeof(integrated_info->dp3_ext_hdmi_reg_settings))__builtin_memmove((settings->reg_settings), (integrated_info
->dp3_ext_hdmi_reg_settings), (sizeof(integrated_info->
dp3_ext_hdmi_reg_settings)));
	memmove(settings->reg_settings_6g,__builtin_memmove((settings->reg_settings_6g), (integrated_info
->dp3_ext_hdmi_6g_reg_settings), (sizeof(integrated_info->
dp3_ext_hdmi_6g_reg_settings)))
			integrated_info->dp3_ext_hdmi_6g_reg_settings,__builtin_memmove((settings->reg_settings_6g), (integrated_info
->dp3_ext_hdmi_6g_reg_settings), (sizeof(integrated_info->
dp3_ext_hdmi_6g_reg_settings)))
			sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings))__builtin_memmove((settings->reg_settings_6g), (integrated_info
->dp3_ext_hdmi_6g_reg_settings), (sizeof(integrated_info->
dp3_ext_hdmi_6g_reg_settings)));
	result = true1;
	break;
default:
	break;
}

if (result == true1) {
	// Validate settings from bios integrated info table
	if (settings->slv_addr == 0)
		return false0;
	if (settings->reg_num > 9)
		return false0;
	if (settings->reg_num_6g > 3)
		return false0;

	for (i = 0; i < settings->reg_num; i++) {
		if (settings->reg_settings[i].i2c_reg_index > 0x20)
			return false0;
	}

	for (i = 0; i < settings->reg_num_6g; i++) {
		if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
			return false0;
	}
}
}

return result;
2290}

2292static bool_Bool i2c_write(struct pipe_ctx *pipe_ctx,
uint8_t address, uint8_t *buffer, uint32_t length)
2294{
struct i2c_command cmd = {0};
struct i2c_payload payload = {0};

memset(&payload, 0, sizeof(payload))__builtin_memset((&payload), (0), (sizeof(payload)));
memset(&cmd, 0, sizeof(cmd))__builtin_memset((&cmd), (0), (sizeof(cmd)));

cmd.number_of_payloads = 1;
cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;

payload.address = address;
payload.data = buffer;
payload.length = length;
payload.write = true1;
cmd.payloads = &payload;

if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
	pipe_ctx->stream->link, &cmd))
return true1;

return false0;
2316}

2318static void write_i2c_retimer_setting(
struct pipe_ctx *pipe_ctx,
bool_Bool is_vga_mode,
bool_Bool is_over_340mhz,
struct ext_hdmi_settings *settings)
2323{
uint8_t slave_address = (settings->slv_addr >> 1);
uint8_t buffer[2];
const uint8_t apply_rx_tx_change = 0x4;
uint8_t offset = 0xA;
uint8_t value = 0;
int i = 0;
bool_Bool i2c_success = false0;
DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

memset(&buffer, 0, sizeof(buffer))__builtin_memset((&buffer), (0), (sizeof(buffer)));

/* Start Ext-Hdmi programming*/

for (i = 0; i < settings->reg_num; i++) {
/* Apply 3G settings */
if (settings->reg_settings[i].i2c_reg_index <= 0x20) {

	buffer[0] = settings->reg_settings[i].i2c_reg_index;
	buffer[1] = settings->reg_settings[i].i2c_reg_val;
	i2c_success = i2c_write(pipe_ctx, slave_address,
				buffer, sizeof(buffer));
	RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_address = 0x%x,				offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
		offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_address = 0x%x,				offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
		slave_address, buffer[0], buffer[1], i2c_success?1:0)___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_address = 0x%x,				offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0);

	if (!i2c_success)
		goto i2c_write_fail;

	/* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
	 * needs to be set to 1 on every 0xA-0xC write.
	 */
	if (settings->reg_settings[i].i2c_reg_index == 0xA ||
		settings->reg_settings[i].i2c_reg_index == 0xB ||
		settings->reg_settings[i].i2c_reg_index == 0xC) {

		/* Query current value from offset 0xA */
		if (settings->reg_settings[i].i2c_reg_index == 0xA)
			value = settings->reg_settings[i].i2c_reg_val;
		else {
			i2c_success =
				dal_ddc_service_query_ddc_data(
				pipe_ctx->stream->link->ddc,
				slave_address, &offset, 1, &value, 1);
			if (!i2c_success)
				goto i2c_write_fail;
		}

		buffer[0] = offset;
		/* Set APPLY_RX_TX_CHANGE bit to 1 */
		buffer[1] = value | apply_rx_tx_change;
		i2c_success = i2c_write(pipe_ctx, slave_address,
				buffer, sizeof(buffer));
		RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_address = 0x%x,					offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
			offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_address = 0x%x,					offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
			slave_address, buffer[0], buffer[1], i2c_success?1:0)___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_address = 0x%x,					offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0);
		if (!i2c_success)
			goto i2c_write_fail;
	}
}
}

/* Apply 3G settings */
if (is_over_340mhz) {
for (i = 0; i < settings->reg_num_6g; i++) {
	/* Apply 3G settings */
	if (settings->reg_settings[i].i2c_reg_index <= 0x20) {

		buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
		buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
		i2c_success = i2c_write(pipe_ctx, slave_address,
					buffer, sizeof(buffer));
		RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\___drm_dbg(((void *)0), DRM_UT_KMS, "above 340Mhz: retimer write to slave_address = 0x%x,					offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
			offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "above 340Mhz: retimer write to slave_address = 0x%x,					offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
			slave_address, buffer[0], buffer[1], i2c_success?1:0)___drm_dbg(((void *)0), DRM_UT_KMS, "above 340Mhz: retimer write to slave_address = 0x%x,					offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0);

		if (!i2c_success)
			goto i2c_write_fail;

		/* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
		 * needs to be set to 1 on every 0xA-0xC write.
		 */
		if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
			settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
			settings->reg_settings_6g[i].i2c_reg_index == 0xC) {

			/* Query current value from offset 0xA */
			if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
				value = settings->reg_settings_6g[i].i2c_reg_val;
			else {
				i2c_success =
						dal_ddc_service_query_ddc_data(
						pipe_ctx->stream->link->ddc,
						slave_address, &offset, 1, &value, 1);
				if (!i2c_success)
					goto i2c_write_fail;
			}

			buffer[0] = offset;
			/* Set APPLY_RX_TX_CHANGE bit to 1 */
			buffer[1] = value | apply_rx_tx_change;
			i2c_success = i2c_write(pipe_ctx, slave_address,
					buffer, sizeof(buffer));
			RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_address = 0x%x,						offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
				offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_address = 0x%x,						offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
				slave_address, buffer[0], buffer[1], i2c_success?1:0)___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_address = 0x%x,						offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0);
			if (!i2c_success)
				goto i2c_write_fail;
		}
	}
}
}

if (is_vga_mode) {
/* Program additional settings if using 640x480 resolution */

/* Write offset 0xFF to 0x01 */
buffer[0] = 0xff;
buffer[1] = 0x01;
i2c_success = i2c_write(pipe_ctx, slave_address,
		buffer, sizeof(buffer));
RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_address = 0x%x,				offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
		offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_address = 0x%x,				offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
		slave_address, buffer[0], buffer[1], i2c_success?1:0)___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_address = 0x%x,				offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0);
if (!i2c_success)
	goto i2c_write_fail;

/* Write offset 0x00 to 0x23 */
buffer[0] = 0x00;
buffer[1] = 0x23;
i2c_success = i2c_write(pipe_ctx, slave_address,
		buffer, sizeof(buffer));
RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_address = 0x%x,			offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
	offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_address = 0x%x,			offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
	slave_address, buffer[0], buffer[1], i2c_success?1:0)___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_address = 0x%x,			offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0);
if (!i2c_success)
	goto i2c_write_fail;

/* Write offset 0xff to 0x00 */
buffer[0] = 0xff;
buffer[1] = 0x00;
i2c_success = i2c_write(pipe_ctx, slave_address,
		buffer, sizeof(buffer));
RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_address = 0x%x,			offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
	offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_address = 0x%x,			offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
	slave_address, buffer[0], buffer[1], i2c_success?1:0)___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_address = 0x%x,			offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0);
if (!i2c_success)
	goto i2c_write_fail;

}

return;

2476i2c_write_fail:
DC_LOG_DEBUG("Set retimer failed")___drm_dbg(((void *)0), DRM_UT_KMS, "Set retimer failed");
2478}

2480static void write_i2c_default_retimer_setting(
struct pipe_ctx *pipe_ctx,
bool_Bool is_vga_mode,
bool_Bool is_over_340mhz)
2484{
uint8_t slave_address = (0xBA >> 1);
uint8_t buffer[2];
bool_Bool i2c_success = false0;
DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

memset(&buffer, 0, sizeof(buffer))__builtin_memset((&buffer), (0), (sizeof(buffer)));

/* Program Slave Address for tuning single integrity */
/* Write offset 0x0A to 0x13 */
buffer[0] = 0x0A;
buffer[1] = 0x13;
i2c_success = i2c_write(pipe_ctx, slave_address,
	buffer, sizeof(buffer));
RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\___drm_dbg(((void *)0), DRM_UT_KMS, "retimer writes default setting to slave_address = 0x%x,		offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "retimer writes default setting to slave_address = 0x%x,		offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
slave_address, buffer[0], buffer[1], i2c_success?1:0)___drm_dbg(((void *)0), DRM_UT_KMS, "retimer writes default setting to slave_address = 0x%x,		offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0);
if (!i2c_success)
goto i2c_write_fail;

/* Write offset 0x0A to 0x17 */
buffer[0] = 0x0A;
buffer[1] = 0x17;
i2c_success = i2c_write(pipe_ctx, slave_address,
	buffer, sizeof(buffer));
RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_addr = 0x%x,		offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_addr = 0x%x,		offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
slave_address, buffer[0], buffer[1], i2c_success?1:0)___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_addr = 0x%x,		offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0);
if (!i2c_success)
goto i2c_write_fail;

/* Write offset 0x0B to 0xDA or 0xD8 */
buffer[0] = 0x0B;
buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
i2c_success = i2c_write(pipe_ctx, slave_address,
	buffer, sizeof(buffer));
RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_addr = 0x%x,		offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_addr = 0x%x,		offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
slave_address, buffer[0], buffer[1], i2c_success?1:0)___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_addr = 0x%x,		offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0);
if (!i2c_success)
goto i2c_write_fail;

/* Write offset 0x0A to 0x17 */
buffer[0] = 0x0A;
buffer[1] = 0x17;
i2c_success = i2c_write(pipe_ctx, slave_address,
	buffer, sizeof(buffer));
RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_addr = 0x%x,		offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_addr = 0x%x,		offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
slave_address, buffer[0], buffer[1], i2c_success?1:0)___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_addr = 0x%x,		offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0);
if (!i2c_success)
goto i2c_write_fail;

/* Write offset 0x0C to 0x1D or 0x91 */
buffer[0] = 0x0C;
buffer[1] = is_over_340mhz ? 0x1D : 0x91;
i2c_success = i2c_write(pipe_ctx, slave_address,
	buffer, sizeof(buffer));
RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_addr = 0x%x,		offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_addr = 0x%x,		offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
slave_address, buffer[0], buffer[1], i2c_success?1:0)___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_addr = 0x%x,		offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0);
if (!i2c_success)
goto i2c_write_fail;

/* Write offset 0x0A to 0x17 */
buffer[0] = 0x0A;
buffer[1] = 0x17;
i2c_success = i2c_write(pipe_ctx, slave_address,
	buffer, sizeof(buffer));
RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_addr = 0x%x,		offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_addr = 0x%x,		offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
slave_address, buffer[0], buffer[1], i2c_success?1:0)___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_addr = 0x%x,		offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0);
if (!i2c_success)
goto i2c_write_fail;


if (is_vga_mode) {
/* Program additional settings if using 640x480 resolution */

/* Write offset 0xFF to 0x01 */
buffer[0] = 0xff;
buffer[1] = 0x01;
i2c_success = i2c_write(pipe_ctx, slave_address,
		buffer, sizeof(buffer));
RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_addr = 0x%x,			offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
	offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_addr = 0x%x,			offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
	slave_address, buffer[0], buffer[1], i2c_success?1:0)___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_addr = 0x%x,			offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0);
if (!i2c_success)
	goto i2c_write_fail;

/* Write offset 0x00 to 0x23 */
buffer[0] = 0x00;
buffer[1] = 0x23;
i2c_success = i2c_write(pipe_ctx, slave_address,
		buffer, sizeof(buffer));
RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_addr = 0x%x,			offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
	offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_addr = 0x%x,			offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
	slave_address, buffer[0], buffer[1], i2c_success?1:0)___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write to slave_addr = 0x%x,			offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0);
if (!i2c_success)
	goto i2c_write_fail;

/* Write offset 0xff to 0x00 */
buffer[0] = 0xff;
buffer[1] = 0x00;
i2c_success = i2c_write(pipe_ctx, slave_address,
		buffer, sizeof(buffer));
RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write default setting to slave_addr = 0x%x,			offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
	offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write default setting to slave_addr = 0x%x,			offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0)
	slave_address, buffer[0], buffer[1], i2c_success?1:0)___drm_dbg(((void *)0), DRM_UT_KMS, "retimer write default setting to slave_addr = 0x%x,			offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n"
, slave_address, buffer[0], buffer[1], i2c_success?1:0);
if (!i2c_success)
	goto i2c_write_fail;
}

return;

2599i2c_write_fail:
DC_LOG_DEBUG("Set default retimer failed")___drm_dbg(((void *)0), DRM_UT_KMS, "Set default retimer failed"
);
2601}

2603static void write_i2c_redriver_setting(
struct pipe_ctx *pipe_ctx,
bool_Bool is_over_340mhz)
2606{
uint8_t slave_address = (0xF0 >> 1);
uint8_t buffer[16];
bool_Bool i2c_success = false0;
DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

memset(&buffer, 0, sizeof(buffer))__builtin_memset((&buffer), (0), (sizeof(buffer)));

// Program Slave Address for tuning single integrity
buffer[3] = 0x4E;
buffer[4] = 0x4E;
buffer[5] = 0x4E;
buffer[6] = is_over_340mhz ? 0x4E : 0x4A;

i2c_success = i2c_write(pipe_ctx, slave_address,
			buffer, sizeof(buffer));
RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\___drm_dbg(((void *)0), DRM_UT_KMS, "redriver write 0 to all 16 reg offset expect following:\n		\t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,		offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,		i2c_success = %d\n"
, slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success
?1:0)
\t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\___drm_dbg(((void *)0), DRM_UT_KMS, "redriver write 0 to all 16 reg offset expect following:\n		\t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,		offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,		i2c_success = %d\n"
, slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success
?1:0)
offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\___drm_dbg(((void *)0), DRM_UT_KMS, "redriver write 0 to all 16 reg offset expect following:\n		\t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,		offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,		i2c_success = %d\n"
, slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success
?1:0)
i2c_success = %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "redriver write 0 to all 16 reg offset expect following:\n		\t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,		offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,		i2c_success = %d\n"
, slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success
?1:0)
slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0)___drm_dbg(((void *)0), DRM_UT_KMS, "redriver write 0 to all 16 reg offset expect following:\n		\t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,		offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,		i2c_success = %d\n"
, slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success
?1:0);

if (!i2c_success)
DC_LOG_DEBUG("Set redriver failed")___drm_dbg(((void *)0), DRM_UT_KMS, "Set redriver failed");
2630}

2632static void disable_link(struct dc_link *link, const struct link_resource *link_res,
enum amd_signal_type signal)
2634{
/*
* TODO: implement call for dp_set_hw_test_pattern
* it is needed for compliance testing
*/

/* Here we need to specify that encoder output settings
* need to be calculated as for the set mode,
* it will lead to querying dynamic link capabilities
* which should be done before enable output
*/

if (dc_is_dp_signal(signal)) {
/* SST DP, eDP */
struct dc_link_settings link_settings = link->cur_link_settings;
if (dc_is_dp_sst_signal(signal))
	dp_disable_link_phy(link, link_res, signal);
else
	dp_disable_link_phy_mst(link, link_res, signal);

if (dc_is_dp_sst_signal(signal) ||
		link->mst_stream_alloc_table.stream_count == 0) {
	if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING) {
		dp_set_fec_enable(link, false0);
		dp_set_fec_ready(link, link_res, false0);
	}
}
} else if (signal != SIGNAL_TYPE_VIRTUAL) {
link->dc->hwss.disable_link_output(link, link_res, signal);
}

if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
/* MST disable link only when no stream use the link */
if (link->mst_stream_alloc_table.stream_count <= 0)
	link->link_status.link_active = false0;
} else {
link->link_status.link_active = false0;
}
2672}

2674static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2675{
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc_link *link = stream->link;
enum dc_color_depth display_color_depth;
enum engine_id eng_id;
struct ext_hdmi_settings settings = {0};
bool_Bool is_over_340mhz = false0;
bool_Bool is_vga_mode = (stream->timing.h_addressable == 640)
	&& (stream->timing.v_addressable == 480);
struct dc *dc = pipe_ctx->stream->ctx->dc;

if (stream->phy_pix_clk == 0)
stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
if (stream->phy_pix_clk > 340000)
is_over_340mhz = true1;

if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
		EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
	/* DP159, Retimer settings */
	eng_id = pipe_ctx->stream_res.stream_enc->id;

	if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
		write_i2c_retimer_setting(pipe_ctx,
				is_vga_mode, is_over_340mhz, &settings);
	} else {
		write_i2c_default_retimer_setting(pipe_ctx,
				is_vga_mode, is_over_340mhz);
	}
} else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
	/* PI3EQX1204, Redriver settings */
	write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
}
}

if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
dal_ddc_service_write_scdc_data(
	stream->link->ddc,
	stream->phy_pix_clk,
	stream->timing.flags.LTE_340MCSC_SCRAMBLE);

memset(&stream->link->cur_link_settings, 0,__builtin_memset((&stream->link->cur_link_settings)
, (0), (sizeof(struct dc_link_settings)))
	sizeof(struct dc_link_settings))__builtin_memset((&stream->link->cur_link_settings)
, (0), (sizeof(struct dc_link_settings)));

display_color_depth = stream->timing.display_color_depth;
if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
display_color_depth = COLOR_DEPTH_888;

dc->hwss.enable_tmds_link_output(
	link,
	&pipe_ctx->link_res,
	pipe_ctx->stream->signal,
	pipe_ctx->clock_source->id,
	display_color_depth,
	stream->phy_pix_clk);

if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
dal_ddc_service_read_scdc_data(link->ddc);
2734}

2736static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2737{
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc_link *link = stream->link;
struct dc *dc = stream->ctx->dc;

if (stream->phy_pix_clk == 0)
stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;

memset(&stream->link->cur_link_settings, 0,__builtin_memset((&stream->link->cur_link_settings)
, (0), (sizeof(struct dc_link_settings)))
	sizeof(struct dc_link_settings))__builtin_memset((&stream->link->cur_link_settings)
, (0), (sizeof(struct dc_link_settings)));
dc->hwss.enable_lvds_link_output(
	link,
	&pipe_ctx->link_res,
	pipe_ctx->clock_source->id,
	stream->phy_pix_clk);

2753}

2755bool_Bool dc_power_alpm_dpcd_enable(struct dc_link *link, bool_Bool enable)
2756{
bool_Bool ret = false0;
union dpcd_alpm_configuration alpm_config;

if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
memset(&alpm_config, 0, sizeof(alpm_config))__builtin_memset((&alpm_config), (0), (sizeof(alpm_config
)));

alpm_config.bits.ENABLE = (enable ? true1 : false0);
ret = dm_helpers_dp_write_dpcd(link->ctx, link,
		DP_RECEIVER_ALPM_CONFIG0x116, &alpm_config.raw,
		sizeof(alpm_config.raw));
}
return ret;
2769}

2771/****************************enable_link***********************************/
2772static enum dc_status enable_link(
struct dc_state *state,
struct pipe_ctx *pipe_ctx)
2775{
enum dc_status status = DC_ERROR_UNEXPECTED;
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc_link *link = stream->link;

/* There's some scenarios where driver is unloaded with display
* still enabled. When driver is reloaded, it may cause a display
* to not light up if there is a mismatch between old and new
* link settings. Need to call disable first before enabling at
* new link settings.
*/
if (link->link_status.link_active) {
disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
}

switch (pipe_ctx->stream->signal) {
case SIGNAL_TYPE_DISPLAY_PORT:
status = enable_link_dp(state, pipe_ctx);
break;
case SIGNAL_TYPE_EDP:
status = enable_link_edp(state, pipe_ctx);
break;
case SIGNAL_TYPE_DISPLAY_PORT_MST:
status = enable_link_dp_mst(state, pipe_ctx);
drm_msleep(200)mdelay(200);
break;
case SIGNAL_TYPE_DVI_SINGLE_LINK:
case SIGNAL_TYPE_DVI_DUAL_LINK:
case SIGNAL_TYPE_HDMI_TYPE_A:
enable_link_hdmi(pipe_ctx);
status = DC_OK;
break;
case SIGNAL_TYPE_LVDS:
enable_link_lvds(pipe_ctx);
status = DC_OK;
break;
case SIGNAL_TYPE_VIRTUAL:
status = DC_OK;
break;
default:
break;
}

if (status == DC_OK)
pipe_ctx->stream->link->link_status.link_active = true1;

return status;
2822}

2824static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2825{

uint32_t pxl_clk = timing->pix_clk_100hz;

if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
pxl_clk /= 2;
else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
pxl_clk = pxl_clk * 2 / 3;

if (timing->display_color_depth == COLOR_DEPTH_101010)
pxl_clk = pxl_clk * 10 / 8;
else if (timing->display_color_depth == COLOR_DEPTH_121212)
pxl_clk = pxl_clk * 12 / 8;

return pxl_clk;
2840}

2842static bool_Bool dp_active_dongle_validate_timing(
const struct dc_crtc_timing *timing,
const struct dpcd_caps *dpcd_caps)
2845{
const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;

switch (dpcd_caps->dongle_type) {
case DISPLAY_DONGLE_DP_VGA_CONVERTER:
case DISPLAY_DONGLE_DP_DVI_CONVERTER:
case DISPLAY_DONGLE_DP_DVI_DONGLE:
if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
	return true1;
else
	return false0;
default:
break;
}

if (dpcd_caps->dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER &&
	dongle_caps->extendedCapValid == true1) {
/* Check Pixel Encoding */
switch (timing->pixel_encoding) {
case PIXEL_ENCODING_RGB:
case PIXEL_ENCODING_YCBCR444:
	break;
case PIXEL_ENCODING_YCBCR422:
	if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
		return false0;
	break;
case PIXEL_ENCODING_YCBCR420:
	if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
		return false0;
	break;
default:
	/* Invalid Pixel Encoding*/
	return false0;
}

switch (timing->display_color_depth) {
case COLOR_DEPTH_666:
case COLOR_DEPTH_888:
	/*888 and 666 should always be supported*/
	break;
case COLOR_DEPTH_101010:
	if (dongle_caps->dp_hdmi_max_bpc < 10)
		return false0;
	break;
case COLOR_DEPTH_121212:
	if (dongle_caps->dp_hdmi_max_bpc < 12)
		return false0;
	break;
case COLOR_DEPTH_141414:
case COLOR_DEPTH_161616:
default:
	/* These color depths are currently not supported */
	return false0;
}

/* Check 3D format */
switch (timing->timing_3d_format) {
case TIMING_3D_FORMAT_NONE:
case TIMING_3D_FORMAT_FRAME_ALTERNATE:
	/*Only frame alternate 3D is supported on active dongle*/
	break;
default:
	/*other 3D formats are not supported due to bad infoframe translation */
	return false0;
}

2911#if defined(CONFIG_DRM_AMD_DC_DCN1)
if (dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps > 0) { // DP to HDMI FRL converter
	struct dc_crtc_timing outputTiming = *timing;

	if (timing->flags.DSC && !timing->dsc_cfg.is_frl)
		/* DP input has DSC, HDMI FRL output doesn't have DSC, remove DSC from output timing */
		outputTiming.flags.DSC = 0;
	if (dc_bandwidth_in_kbps_from_timing(&outputTiming) > dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps)
		return false0;
} else { // DP to HDMI TMDS converter
	if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
		return false0;
}
2924#else
if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
	return false0;
2927#endif
}

if (dpcd_caps->channel_coding_cap.bits.DP_128b_132b_SUPPORTED == 0 &&
	dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT == 0 &&
	dongle_caps->dfp_cap_ext.supported) {

if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000))
	return false0;

if (dongle_caps->dfp_cap_ext.max_video_h_active_width < timing->h_addressable)
	return false0;

if (dongle_caps->dfp_cap_ext.max_video_v_active_height < timing->v_addressable)
	return false0;

if (timing->pixel_encoding == PIXEL_ENCODING_RGB) {
	if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
		return false0;
	if (timing->display_color_depth == COLOR_DEPTH_666 &&
			!dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_6bpc)
		return false0;
	else if (timing->display_color_depth == COLOR_DEPTH_888 &&
			!dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_8bpc)
		return false0;
	else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
			!dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_10bpc)
		return false0;
	else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
			!dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_12bpc)
		return false0;
	else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
			!dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_16bpc)
		return false0;
} else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
	if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
		return false0;
	if (timing->display_color_depth == COLOR_DEPTH_888 &&
			!dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_8bpc)
		return false0;
	else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
			!dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_10bpc)
		return false0;
	else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
			!dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_12bpc)
		return false0;
	else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
			!dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_16bpc)
		return false0;
} else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
	if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
		return false0;
	if (timing->display_color_depth == COLOR_DEPTH_888 &&
			!dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_8bpc)
		return false0;
	else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
			!dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_10bpc)
		return false0;
	else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
			!dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_12bpc)
		return false0;
	else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
			!dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_16bpc)
		return false0;
} else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
	if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
		return false0;
	if (timing->display_color_depth == COLOR_DEPTH_888 &&
			!dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_8bpc)
		return false0;
	else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
			!dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_10bpc)
		return false0;
	else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
			!dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_12bpc)
		return false0;
	else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
			!dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_16bpc)
		return false0;
}
}

return true1;
3010}

3012enum dc_status dc_link_validate_mode_timing(
const struct dc_stream_state *stream,
struct dc_link *link,
const struct dc_crtc_timing *timing)
3016{
uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
struct dpcd_caps *dpcd_caps = &link->dpcd_caps;

/* A hack to avoid failing any modes for EDID override feature on
* topology change such as lower quality cable for DP or different dongle
*/
if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL)
return DC_OK;

/* Passive Dongle */
if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
return DC_EXCEED_DONGLE_CAP;

/* Active Dongle*/
if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
return DC_EXCEED_DONGLE_CAP;

switch (stream->signal) {
case SIGNAL_TYPE_EDP:
case SIGNAL_TYPE_DISPLAY_PORT:
if (!dp_validate_mode_timing(
		link,
		timing))
	return DC_NO_DP_LINK_BANDWIDTH;
break;

default:
break;
}

return DC_OK;
3048}

3050static struct abm *get_abm_from_stream_res(const struct dc_link *link)
3051{
int i;
struct dc *dc = NULL((void *)0);
struct abm *abm = NULL((void *)0);

if (!link || !link->ctx)
return NULL((void *)0);

dc = link->ctx->dc;

for (i = 0; i < MAX_PIPES6; i++) {
struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
struct dc_stream_state *stream = pipe_ctx.stream;

if (stream && stream->link == link) {
	abm = pipe_ctx.stream_res.abm;
	break;
}
}
return abm;
3071}

3073int dc_link_get_backlight_level(const struct dc_link *link)
3074{
struct abm *abm = get_abm_from_stream_res(link);
struct panel_cntl *panel_cntl = link->panel_cntl;
struct dc  *dc = link->ctx->dc;
struct dmcu *dmcu = dc->res_pool->dmcu;
bool_Bool fw_set_brightness = true1;

if (dmcu)
fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);

if (!fw_set_brightness && panel_cntl->funcs->get_current_backlight)
return panel_cntl->funcs->get_current_backlight(panel_cntl);
else if (abm != NULL((void *)0) && abm->funcs->get_current_backlight != NULL((void *)0))
return (int) abm->funcs->get_current_backlight(abm);
else
return DC_ERROR_UNEXPECTED;
3090}

3092int dc_link_get_target_backlight_pwm(const struct dc_link *link)
3093{
struct abm *abm = get_abm_from_stream_res(link);

if (abm == NULL((void *)0) || abm->funcs->get_target_backlight == NULL((void *)0))
return DC_ERROR_UNEXPECTED;

return (int) abm->funcs->get_target_backlight(abm);
3100}

3102static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
3103{
int i;
struct dc *dc = link->ctx->dc;
struct pipe_ctx *pipe_ctx = NULL((void *)0);

for (i = 0; i < MAX_PIPES6; i++) {
if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
	if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
		pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
		break;
	}
}
}

return pipe_ctx;
3118}

3120bool_Bool dc_link_set_backlight_level(const struct dc_link *link,
uint32_t backlight_pwm_u16_16,
uint32_t frame_ramp)
3123{
struct dc  *dc = link->ctx->dc;

DC_LOGGER_INIT(link->ctx->logger);
DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",___drm_dbg(((void *)0), DRM_UT_KMS, "New Backlight level: %d (0x%X)\n"
, backlight_pwm_u16_16, backlight_pwm_u16_16)
	backlight_pwm_u16_16, backlight_pwm_u16_16)___drm_dbg(((void *)0), DRM_UT_KMS, "New Backlight level: %d (0x%X)\n"
, backlight_pwm_u16_16, backlight_pwm_u16_16);

if (dc_is_embedded_signal(link->connector_signal)) {
struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);

if (pipe_ctx) {
	/* Disable brightness ramping when the display is blanked
	 * as it can hang the DMCU
	 */
	if (pipe_ctx->plane_state == NULL((void *)0))
		frame_ramp = 0;
} else {
	return false0;
}

dc->hwss.set_backlight_level(
		pipe_ctx,
		backlight_pwm_u16_16,
		frame_ramp);
}
return true1;
3149}

3151bool_Bool dc_link_set_psr_allow_active(struct dc_link *link, const bool_Bool *allow_active,
bool_Bool wait, bool_Bool force_static, const unsigned int *power_opts)
3153{
struct dc  *dc = link->ctx->dc;
struct dmcu *dmcu = dc->res_pool->dmcu;
struct dmub_psr *psr = dc->res_pool->psr;
unsigned int panel_inst;

if (psr == NULL((void *)0) && force_static)
return false0;

if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
return false0;

if ((allow_active != NULL((void *)0)) && (*allow_active == true1) && (link->type == dc_connection_none)) {
// Don't enter PSR if panel is not connected
return false0;
}

/* Set power optimization flag */
if (power_opts && link->psr_settings.psr_power_opt != *power_opts) {
link->psr_settings.psr_power_opt = *power_opts;

if (psr != NULL((void *)0) && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt)
	psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, panel_inst);
}

if (psr != NULL((void *)0) && link->psr_settings.psr_feature_enabled &&
	force_static && psr->funcs->psr_force_static)
psr->funcs->psr_force_static(psr, panel_inst);

/* Enable or Disable PSR */
if (allow_active && link->psr_settings.psr_allow_active != *allow_active) {
link->psr_settings.psr_allow_active = *allow_active;

if (!link->psr_settings.psr_allow_active)
	dc_z10_restore(dc);

if (psr != NULL((void *)0) && link->psr_settings.psr_feature_enabled) {
	psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);
} else if ((dmcu != NULL((void *)0) && dmcu->funcs->is_dmcu_initialized(dmcu)) &&
	link->psr_settings.psr_feature_enabled)
	dmcu->funcs->set_psr_enable(dmcu, link->psr_settings.psr_allow_active, wait);
else
	return false0;
}

return true1;
3199}

3201bool_Bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
3202{
struct dc  *dc = link->ctx->dc;
struct dmcu *dmcu = dc->res_pool->dmcu;
struct dmub_psr *psr = dc->res_pool->psr;
unsigned int panel_inst;

if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
return false0;

if (psr != NULL((void *)0) && link->psr_settings.psr_feature_enabled)
psr->funcs->psr_get_state(psr, state, panel_inst);
else if (dmcu != NULL((void *)0) && link->psr_settings.psr_feature_enabled)
dmcu->funcs->get_psr_state(dmcu, state);

return true1;
3217}

3219static inline enum physical_phy_id
3220transmitter_to_phy_id(enum transmitter transmitter_value)
3221{
switch (transmitter_value) {
case TRANSMITTER_UNIPHY_A:
return PHYLD_0;
case TRANSMITTER_UNIPHY_B:
return PHYLD_1;
case TRANSMITTER_UNIPHY_C:
return PHYLD_2;
case TRANSMITTER_UNIPHY_D:
return PHYLD_3;
case TRANSMITTER_UNIPHY_E:
return PHYLD_4;
case TRANSMITTER_UNIPHY_F:
return PHYLD_5;
case TRANSMITTER_NUTMEG_CRT:
return PHYLD_6;
case TRANSMITTER_TRAVIS_CRT:
return PHYLD_7;
case TRANSMITTER_TRAVIS_LCD:
return PHYLD_8;
case TRANSMITTER_UNIPHY_G:
return PHYLD_9;
case TRANSMITTER_COUNT:
return PHYLD_COUNT;
case TRANSMITTER_UNKNOWN:
return PHYLD_UNKNOWN;
default:
WARN_ONCE(1, "Unknown transmitter value %d\n",({ static int __warned; int __ret = !!(1); if (__ret &&
 !__warned) { printf("Unknown transmitter value %d\n", transmitter_value
); __warned = 1; } __builtin_expect(!!(__ret), 0); })
	  transmitter_value)({ static int __warned; int __ret = !!(1); if (__ret &&
 !__warned) { printf("Unknown transmitter value %d\n", transmitter_value
); __warned = 1; } __builtin_expect(!!(__ret), 0); });
return PHYLD_UNKNOWN;
}
3252}

3254bool_Bool dc_link_setup_psr(struct dc_link *link,
const struct dc_stream_state *stream, struct psr_config *psr_config,
struct psr_context *psr_context)
3257{
struct dc *dc;
struct dmcu *dmcu;
struct dmub_psr *psr;
int i;
unsigned int panel_inst;
/* updateSinkPsrDpcdConfig*/
union dpcd_psr_configuration psr_configuration;
union dpcd_sink_active_vtotal_control_mode vtotal_control = {0};

psr_context->controllerId = CONTROLLER_ID_UNDEFINED;

if (!link)
return false0;

dc = link->ctx->dc;
dmcu = dc->res_pool->dmcu;
psr = dc->res_pool->psr;

if (!dmcu && !psr)
return false0;

if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
return false0;


memset(&psr_configuration, 0, sizeof(psr_configuration))__builtin_memset((&psr_configuration), (0), (sizeof(psr_configuration
)));

psr_configuration.bits.ENABLE                    = 1;
psr_configuration.bits.CRC_VERIFICATION          = 1;
psr_configuration.bits.FRAME_CAPTURE_INDICATION  =
	psr_config->psr_frame_capture_indication_req;

/* Check for PSR v2*/
if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
/* For PSR v2 selective update.
 * Indicates whether sink should start capturing
 * immediately following active scan line,
 * or starting with the 2nd active scan line.
 */
psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
/*For PSR v2, determines whether Sink should generate
 * IRQ_HPD when CRC mismatch is detected.
 */
psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
/* For PSR v2, set the bit when the Source device will
 * be enabling PSR2 operation.
 */
psr_configuration.bits.ENABLE_PSR2    = 1;
/* For PSR v2, the Sink device must be able to receive
 * SU region updates early in the frame time.
 */
psr_configuration.bits.EARLY_TRANSPORT_ENABLE    = 1;
}

dm_helpers_dp_write_dpcd(
link->ctx,
link,
368,
&psr_configuration.raw,
sizeof(psr_configuration.raw));

if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
dc_power_alpm_dpcd_enable(link, true1);
psr_context->su_granularity_required =
	psr_config->su_granularity_required;
psr_context->su_y_granularity =
	psr_config->su_y_granularity;
psr_context->line_time_in_us =
	psr_config->line_time_in_us;

if (link->psr_settings.psr_vtotal_control_support) {
	psr_context->rate_control_caps = psr_config->rate_control_caps;
	vtotal_control.bits.ENABLE = true1;
	core_link_write_dpcd(link, DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE0x375,
					&vtotal_control.raw, sizeof(vtotal_control.raw));
}
}

psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
psr_context->transmitterId = link->link_enc->transmitter;
psr_context->engineId = link->link_enc->preferred_engine;

for (i = 0; i < MAX_PIPES6; i++) {
if (dc->current_state->res_ctx.pipe_ctx[i].stream
		== stream) {
	/* dmcu -1 for all controller id values,
	 * therefore +1 here
	 */
	psr_context->controllerId =
		dc->current_state->res_ctx.
		pipe_ctx[i].stream_res.tg->inst + 1;
	break;
}
}

/* Hardcoded for now.  Can be Pcie or Uniphy (or Unknown)*/
psr_context->phyType = PHY_TYPE_UNIPHY;
/*PhyId is associated with the transmitter id*/
psr_context->smuPhyId =
transmitter_to_phy_id(link->link_enc->transmitter);

psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
			timing.pix_clk_100hz * 100),
			stream->timing.v_total),
			stream->timing.h_total);

psr_context->psrSupportedDisplayConfig = true1;
psr_context->psrExitLinkTrainingRequired =
psr_config->psr_exit_link_training_required;
psr_context->sdpTransmitLineNumDeadline =
psr_config->psr_sdp_transmit_line_num_deadline;
psr_context->psrFrameCaptureIndicationReq =
psr_config->psr_frame_capture_indication_req;

psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */

psr_context->numberOfControllers =
	link->dc->res_pool->timing_generator_count;

psr_context->rfb_update_auto_en = true1;

/* 2 frames before enter PSR. */
psr_context->timehyst_frames = 2;
/* half a frame
* (units in 100 lines, i.e. a value of 1 represents 100 lines)
*/
psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
psr_context->aux_repeats = 10;

psr_context->psr_level.u32all = 0;

/*skip power down the single pipe since it blocks the cstate*/
3391#if defined(CONFIG_DRM_AMD_DC_DCN1)
if (link->ctx->asic_id.chip_family >= FAMILY_RV142) {
switch(link->ctx->asic_id.chip_family) {
case FAMILY_YELLOW_CARP146:
case AMDGPU_FAMILY_GC_10_3_6149:
case AMDGPU_FAMILY_GC_11_0_1148:
	if (dc->debug.disable_z10 || dc->debug.psr_skip_crtc_disable)
		psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true1;
	break;
default:
	psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true1;
	break;
}
}
3405#else
if (link->ctx->asic_id.chip_family >= FAMILY_RV142)
psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true1;
3408#endif

/* SMU will perform additional powerdown sequence.
* For unsupported ASICs, set psr_level flag to skip PSR
*  static screen notification to SMU.
*  (Always set for DAL2, did not check ASIC)
*/
psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;

/* Complete PSR entry before aborting to prevent intermittent
* freezes on certain eDPs
*/
psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;

/* enable ALPM */
psr_context->psr_level.bits.DISABLE_ALPM = 0;
psr_context->psr_level.bits.ALPM_DEFAULT_PD_MODE = 1;

/* Controls additional delay after remote frame capture before
* continuing power down, default = 0
*/
psr_context->frame_delay = 0;

if (psr) {
link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
	link, psr_context, panel_inst);
link->psr_settings.psr_power_opt = 0;
link->psr_settings.psr_allow_active = 0;
}
else
link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);

/* psr_enabled == 0 indicates setup_psr did not succeed, but this
* should not happen since firmware should be running at this point
*/
if (link->psr_settings.psr_feature_enabled == 0)
ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret
 && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link.c"
, 3445); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
 {} while (0); } while (0);

return true1;

3449}

3451void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
3452{
struct dc  *dc = link->ctx->dc;
struct dmub_psr *psr = dc->res_pool->psr;
unsigned int panel_inst;

if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
return;

/* PSR residency measurements only supported on DMCUB */
if (psr != NULL((void *)0) && link->psr_settings.psr_feature_enabled)
psr->funcs->psr_get_residency(psr, residency, panel_inst);
else
*residency = 0;
3465}

3467bool_Bool dc_link_set_sink_vtotal_in_psr_active(const struct dc_link *link, uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
3468{
struct dc *dc = link->ctx->dc;
struct dmub_psr *psr = dc->res_pool->psr;

if (psr == NULL((void *)0) || !link->psr_settings.psr_feature_enabled || !link->psr_settings.psr_vtotal_control_support)
return false0;

psr->funcs->psr_set_sink_vtotal_in_psr_active(psr, psr_vtotal_idle, psr_vtotal_su);

return true1;
3478}

3480const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
3481{
return &link->link_status;
3483}

3485void core_link_resume(struct dc_link *link)
3486{
if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
program_hpd_filter(link);
3489}

3491static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
3492{
struct fixed31_32 mbytes_per_sec;
uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
	&stream->link->cur_link_settings);
link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */

mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);

return dc_fixpt_div_int(mbytes_per_sec, 54);
3501}

3503static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)
3504{
struct fixed31_32 peak_kbps;
uint32_t numerator = 0;
uint32_t denominator = 1;

/*
* margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
* The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
* common multiplier to render an integer PBN for all link rate/lane
* counts combinations
* calculate
* peak_kbps *= (1006/1000)
* peak_kbps *= (64/54)
* peak_kbps *= 8    convert to bytes
*/

numerator = 64 * PEAK_FACTOR_X1000;
denominator = 54 * 8 * 1000 * 1000;
kbps *= numerator;
peak_kbps = dc_fixpt_from_fraction(kbps, denominator);

return peak_kbps;
3526}

3528static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
3529{
uint64_t kbps;

kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
return get_pbn_from_bw_in_kbps(kbps);
3534}

3536static void update_mst_stream_alloc_table(
struct dc_link *link,
struct stream_encoder *stream_enc,
struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc?
const struct dc_dp_mst_stream_allocation_table *proposed_table)
3541{
struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 };
struct link_mst_stream_allocation *dc_alloc;

int i;
int j;

/* if DRM proposed_table has more than one new payload */
ASSERT(proposed_table->stream_count -do { if (({ static int __warned; int __ret = !!(!(proposed_table
->stream_count - link->mst_stream_alloc_table.stream_count
 < 2)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(proposed_table->stream_count - link->mst_stream_alloc_table.stream_count < 2)"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link.c", 3550
); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while
 (0); } while (0)
	link->mst_stream_alloc_table.stream_count < 2)do { if (({ static int __warned; int __ret = !!(!(proposed_table
->stream_count - link->mst_stream_alloc_table.stream_count
 < 2)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(proposed_table->stream_count - link->mst_stream_alloc_table.stream_count < 2)"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link.c", 3550
); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while
 (0); } while (0);

/* copy proposed_table to link, add stream encoder */
for (i = 0; i < proposed_table->stream_count; i++) {

for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
	dc_alloc =
	&link->mst_stream_alloc_table.stream_allocations[j];

	if (dc_alloc->vcp_id ==
		proposed_table->stream_allocations[i].vcp_id) {

		work_table[i] = *dc_alloc;
		work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count;
		break; /* exit j loop */
	}
}

/* new vcp_id */
if (j == link->mst_stream_alloc_table.stream_count) {
	work_table[i].vcp_id =
		proposed_table->stream_allocations[i].vcp_id;
	work_table[i].slot_count =
		proposed_table->stream_allocations[i].slot_count;
	work_table[i].stream_enc = stream_enc;
	work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc;
}
}

/* update link->mst_stream_alloc_table with work_table */
link->mst_stream_alloc_table.stream_count =
	proposed_table->stream_count;
for (i = 0; i < MAX_CONTROLLER_NUM; i++)
link->mst_stream_alloc_table.stream_allocations[i] =
		work_table[i];
3585}

3587static void remove_stream_from_alloc_table(
struct dc_link *link,
struct stream_encoder *dio_stream_enc,
struct hpo_dp_stream_encoder *hpo_dp_stream_enc)
3591{
int i = 0;
struct link_mst_stream_allocation_table *table =
	&link->mst_stream_alloc_table;

if (hpo_dp_stream_enc) {
for (; i < table->stream_count; i++)
	if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc)
		break;
} else {
for (; i < table->stream_count; i++)
	if (dio_stream_enc == table->stream_allocations[i].stream_enc)
		break;
}

if (i < table->stream_count) {
i++;
for (; i < table->stream_count; i++)
	table->stream_allocations[i-1] = table->stream_allocations[i];
memset(&table->stream_allocations[table->stream_count-1], 0,__builtin_memset((&table->stream_allocations[table->
stream_count-1]), (0), (sizeof(struct link_mst_stream_allocation
)))
		sizeof(struct link_mst_stream_allocation))__builtin_memset((&table->stream_allocations[table->
stream_count-1]), (0), (sizeof(struct link_mst_stream_allocation
)));
table->stream_count--;
}
3614}

3616static void dc_log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp)
3617{
const uint32_t VCP_Y_PRECISION = 1000;
uint64_t vcp_x, vcp_y;

// Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision
avg_time_slots_per_mtp = dc_fixpt_add(
	avg_time_slots_per_mtp, dc_fixpt_from_fraction(1, 2 * VCP_Y_PRECISION));

vcp_x = dc_fixpt_floor(avg_time_slots_per_mtp);
vcp_y = dc_fixpt_floor(
	dc_fixpt_mul_int(
		dc_fixpt_sub_int(avg_time_slots_per_mtp, dc_fixpt_floor(avg_time_slots_per_mtp)),
		VCP_Y_PRECISION));

if (link->type == dc_connection_mst_branch)
DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream "___drm_dbg(((void *)0), DRM_UT_KMS, "MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream "
 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION)
		"X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION)___drm_dbg(((void *)0), DRM_UT_KMS, "MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream "
 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
else
DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream "___drm_dbg(((void *)0), DRM_UT_KMS, "SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream "
 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION)
		"X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION)___drm_dbg(((void *)0), DRM_UT_KMS, "SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream "
 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
3637}

3639/*
* Payload allocation/deallocation for SST introduced in DP2.0
*/
3642static enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx,
				 bool_Bool allocate)
3644{
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc_link *link = stream->link;
struct link_mst_stream_allocation_table proposed_table = {0};
struct fixed31_32 avg_time_slots_per_mtp;
const struct dc_link_settings empty_link_settings = {0};
const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
DC_LOGGER_INIT(link->ctx->logger);

/* slot X.Y for SST payload deallocate */
if (!allocate) {
avg_time_slots_per_mtp = dc_fixpt_from_int(0);

dc_log_vcp_x_y(link, avg_time_slots_per_mtp);

if (link_hwss->ext.set_throttled_vcp_size)
	link_hwss->ext.set_throttled_vcp_size(pipe_ctx,
			avg_time_slots_per_mtp);
if (link_hwss->ext.set_hblank_min_symbol_width)
	link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
			&empty_link_settings,
			avg_time_slots_per_mtp);
}

/* calculate VC payload and update branch with new payload allocation table*/
if (!dpcd_write_128b_132b_sst_payload_allocation_table(
	stream,
	link,
	&proposed_table,
	allocate)) {
DC_LOG_ERROR("SST Update Payload: Failed to update "__drm_err("SST Update Payload: Failed to update " "allocation table for "
 "pipe idx: %d\n", pipe_ctx->pipe_idx)
				"allocation table for "__drm_err("SST Update Payload: Failed to update " "allocation table for "
 "pipe idx: %d\n", pipe_ctx->pipe_idx)
				"pipe idx: %d\n",__drm_err("SST Update Payload: Failed to update " "allocation table for "
 "pipe idx: %d\n", pipe_ctx->pipe_idx)
				pipe_ctx->pipe_idx)__drm_err("SST Update Payload: Failed to update " "allocation table for "
 "pipe idx: %d\n", pipe_ctx->pipe_idx);
return DC_FAIL_DP_PAYLOAD_ALLOCATION;
}

proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;

ASSERT(proposed_table.stream_count == 1)do { if (({ static int __warned; int __ret = !!(!(proposed_table
.stream_count == 1)); if (__ret && !__warned) { printf
("WARNING %s failed at %s:%d\n", "!(proposed_table.stream_count == 1)"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link.c", 3683
); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while
 (0); } while (0);

//TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id
DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p      "___drm_dbg(((void *)0), DRM_UT_KMS, "SST Update Payload: hpo_dp_stream_enc: %p      "
 "vcp_id: %d      " "slot_count: %d\n", (void *) proposed_table
.stream_allocations[0].hpo_dp_stream_enc, proposed_table.stream_allocations
[0].vcp_id, proposed_table.stream_allocations[0].slot_count)
"vcp_id: %d      "___drm_dbg(((void *)0), DRM_UT_KMS, "SST Update Payload: hpo_dp_stream_enc: %p      "
 "vcp_id: %d      " "slot_count: %d\n", (void *) proposed_table
.stream_allocations[0].hpo_dp_stream_enc, proposed_table.stream_allocations
[0].vcp_id, proposed_table.stream_allocations[0].slot_count)
"slot_count: %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "SST Update Payload: hpo_dp_stream_enc: %p      "
 "vcp_id: %d      " "slot_count: %d\n", (void *) proposed_table
.stream_allocations[0].hpo_dp_stream_enc, proposed_table.stream_allocations
[0].vcp_id, proposed_table.stream_allocations[0].slot_count)
(void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc,___drm_dbg(((void *)0), DRM_UT_KMS, "SST Update Payload: hpo_dp_stream_enc: %p      "
 "vcp_id: %d      " "slot_count: %d\n", (void *) proposed_table
.stream_allocations[0].hpo_dp_stream_enc, proposed_table.stream_allocations
[0].vcp_id, proposed_table.stream_allocations[0].slot_count)
proposed_table.stream_allocations[0].vcp_id,___drm_dbg(((void *)0), DRM_UT_KMS, "SST Update Payload: hpo_dp_stream_enc: %p      "
 "vcp_id: %d      " "slot_count: %d\n", (void *) proposed_table
.stream_allocations[0].hpo_dp_stream_enc, proposed_table.stream_allocations
[0].vcp_id, proposed_table.stream_allocations[0].slot_count)
proposed_table.stream_allocations[0].slot_count)___drm_dbg(((void *)0), DRM_UT_KMS, "SST Update Payload: hpo_dp_stream_enc: %p      "
 "vcp_id: %d      " "slot_count: %d\n", (void *) proposed_table
.stream_allocations[0].hpo_dp_stream_enc, proposed_table.stream_allocations
[0].vcp_id, proposed_table.stream_allocations[0].slot_count);

/* program DP source TX for payload */
link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
	&proposed_table);

/* poll for ACT handled */
if (!dpcd_poll_for_allocation_change_trigger(link)) {
// Failures will result in blackscreen and errors logged
BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__
, 3700); do {} while (0); } while (0);
}

/* slot X.Y for SST payload allocate */
if (allocate && dp_get_link_encoding_format(&link->cur_link_settings) ==
	DP_128b_132b_ENCODING) {
avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, link);

dc_log_vcp_x_y(link, avg_time_slots_per_mtp);

if (link_hwss->ext.set_throttled_vcp_size)
	link_hwss->ext.set_throttled_vcp_size(pipe_ctx,
			avg_time_slots_per_mtp);
if (link_hwss->ext.set_hblank_min_symbol_width)
	link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
			&link->cur_link_settings,
			avg_time_slots_per_mtp);
}

/* Always return DC_OK.
* If part of sequence fails, log failure(s) and show blackscreen
*/
return DC_OK;
3723}

3725/* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
* because stream_encoder is not exposed to dm
*/
3728enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
3729{
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc_link *link = stream->link;
struct dc_dp_mst_stream_allocation_table proposed_table = {0};
struct fixed31_32 avg_time_slots_per_mtp;
struct fixed31_32 pbn;
struct fixed31_32 pbn_per_slot;
int i;
enum act_return_status ret;
const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
DC_LOGGER_INIT(link->ctx->logger);

/* enable_link_dp_mst already check link->enabled_stream_count
* and stream is in link->stream[]. This is called during set mode,
* stream_enc is available.
*/

/* get calculate VC payload for stream: stream_alloc */
if (dm_helpers_dp_mst_write_payload_allocation_table(
stream->ctx,
stream,
&proposed_table,
true1))
update_mst_stream_alloc_table(
			link,
			pipe_ctx->stream_res.stream_enc,
			pipe_ctx->stream_res.hpo_dp_stream_enc,
			&proposed_table);
else
DC_LOG_WARNING("Failed to update"printk("\0014" "[" "drm" "] " "Failed to update" "MST allocation table for"
 "pipe idx:%d\n", pipe_ctx->pipe_idx)
		"MST allocation table for"printk("\0014" "[" "drm" "] " "Failed to update" "MST allocation table for"
 "pipe idx:%d\n", pipe_ctx->pipe_idx)
		"pipe idx:%d\n",printk("\0014" "[" "drm" "] " "Failed to update" "MST allocation table for"
 "pipe idx:%d\n", pipe_ctx->pipe_idx)
		pipe_ctx->pipe_idx)printk("\0014" "[" "drm" "] " "Failed to update" "MST allocation table for"
 "pipe idx:%d\n", pipe_ctx->pipe_idx);

DC_LOG_MST("%s  "___drm_dbg(((void *)0), DRM_UT_KMS, "%s  " "stream_count: %d: \n "
, __func__, link->mst_stream_alloc_table.stream_count)
	"stream_count: %d: \n ",___drm_dbg(((void *)0), DRM_UT_KMS, "%s  " "stream_count: %d: \n "
, __func__, link->mst_stream_alloc_table.stream_count)
	__func__,___drm_dbg(((void *)0), DRM_UT_KMS, "%s  " "stream_count: %d: \n "
, __func__, link->mst_stream_alloc_table.stream_count)
	link->mst_stream_alloc_table.stream_count)___drm_dbg(((void *)0), DRM_UT_KMS, "%s  " "stream_count: %d: \n "
, __func__, link->mst_stream_alloc_table.stream_count);

for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
DC_LOG_MST("stream_enc[%d]: %p      "___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
"stream[%d].hpo_dp_stream_enc: %p      "___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
"stream[%d].vcp_id: %d      "___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
"stream[%d].slot_count: %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
i,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
(void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
i,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
(void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
i,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
link->mst_stream_alloc_table.stream_allocations[i].vcp_id,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
i,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
link->mst_stream_alloc_table.stream_allocations[i].slot_count)___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count);
}

ASSERT(proposed_table.stream_count > 0)do { if (({ static int __warned; int __ret = !!(!(proposed_table
.stream_count > 0)); if (__ret && !__warned) { printf
("WARNING %s failed at %s:%d\n", "!(proposed_table.stream_count > 0)"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link.c", 3783
); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while
 (0); } while (0);

/* program DP source TX for payload */
if (link_hwss->ext.update_stream_allocation_table == NULL((void *)0) ||
	dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
DC_LOG_ERROR("Failure: unknown encoding format\n")__drm_err("Failure: unknown encoding format\n");
return DC_ERROR_UNEXPECTED;
}

link_hwss->ext.update_stream_allocation_table(link,
	&pipe_ctx->link_res,
	&link->mst_stream_alloc_table);

/* send down message */
ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
	stream->ctx,
	stream);

if (ret != ACT_LINK_LOST) {
dm_helpers_dp_mst_send_payload_allocation(
		stream->ctx,
		stream,
		true1);
}

/* slot X.Y for only current stream */
pbn_per_slot = get_pbn_per_slot(stream);
if (pbn_per_slot.value == 0) {
DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n")__drm_err("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n"
);
return DC_UNSUPPORTED_VALUE;
}
pbn = get_pbn_from_timing(pipe_ctx);
avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);

dc_log_vcp_x_y(link, avg_time_slots_per_mtp);

if (link_hwss->ext.set_throttled_vcp_size)
link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
if (link_hwss->ext.set_hblank_min_symbol_width)
link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
		&link->cur_link_settings,
		avg_time_slots_per_mtp);

return DC_OK;

3828}

3830enum dc_status dc_link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
3831{
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc_link *link = stream->link;
struct fixed31_32 avg_time_slots_per_mtp;
struct fixed31_32 pbn;
struct fixed31_32 pbn_per_slot;
struct dc_dp_mst_stream_allocation_table proposed_table = {0};
uint8_t i;
const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
DC_LOGGER_INIT(link->ctx->logger);

/* decrease throttled vcp size */
pbn_per_slot = get_pbn_per_slot(stream);
pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);

if (link_hwss->ext.set_throttled_vcp_size)
link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
if (link_hwss->ext.set_hblank_min_symbol_width)
link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
		&link->cur_link_settings,
		avg_time_slots_per_mtp);

/* send ALLOCATE_PAYLOAD sideband message with updated pbn */
dm_helpers_dp_mst_send_payload_allocation(
	stream->ctx,
	stream,
	true1);

/* notify immediate branch device table update */
if (dm_helpers_dp_mst_write_payload_allocation_table(
	stream->ctx,
	stream,
	&proposed_table,
	true1)) {
/* update mst stream allocation table software state */
update_mst_stream_alloc_table(
		link,
		pipe_ctx->stream_res.stream_enc,
		pipe_ctx->stream_res.hpo_dp_stream_enc,
		&proposed_table);
} else {
DC_LOG_WARNING("Failed to update"printk("\0014" "[" "drm" "] " "Failed to update" "MST allocation table for"
 "pipe idx:%d\n", pipe_ctx->pipe_idx)
		"MST allocation table for"printk("\0014" "[" "drm" "] " "Failed to update" "MST allocation table for"
 "pipe idx:%d\n", pipe_ctx->pipe_idx)
		"pipe idx:%d\n",printk("\0014" "[" "drm" "] " "Failed to update" "MST allocation table for"
 "pipe idx:%d\n", pipe_ctx->pipe_idx)
		pipe_ctx->pipe_idx)printk("\0014" "[" "drm" "] " "Failed to update" "MST allocation table for"
 "pipe idx:%d\n", pipe_ctx->pipe_idx);
}

DC_LOG_MST("%s  "___drm_dbg(((void *)0), DRM_UT_KMS, "%s  " "stream_count: %d: \n "
, __func__, link->mst_stream_alloc_table.stream_count)
	"stream_count: %d: \n ",___drm_dbg(((void *)0), DRM_UT_KMS, "%s  " "stream_count: %d: \n "
, __func__, link->mst_stream_alloc_table.stream_count)
	__func__,___drm_dbg(((void *)0), DRM_UT_KMS, "%s  " "stream_count: %d: \n "
, __func__, link->mst_stream_alloc_table.stream_count)
	link->mst_stream_alloc_table.stream_count)___drm_dbg(((void *)0), DRM_UT_KMS, "%s  " "stream_count: %d: \n "
, __func__, link->mst_stream_alloc_table.stream_count);

for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
DC_LOG_MST("stream_enc[%d]: %p      "___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
		"stream[%d].hpo_dp_stream_enc: %p      "___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
		"stream[%d].vcp_id: %d      "___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
		"stream[%d].slot_count: %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
		i,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
		(void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
		i,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
		(void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
		i,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
		link->mst_stream_alloc_table.stream_allocations[i].vcp_id,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
		i,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
		link->mst_stream_alloc_table.stream_allocations[i].slot_count)___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count);
}

ASSERT(proposed_table.stream_count > 0)do { if (({ static int __warned; int __ret = !!(!(proposed_table
.stream_count > 0)); if (__ret && !__warned) { printf
("WARNING %s failed at %s:%d\n", "!(proposed_table.stream_count > 0)"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link.c", 3899
); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while
 (0); } while (0);

/* update mst stream allocation table hardware state */
if (link_hwss->ext.update_stream_allocation_table == NULL((void *)0) ||
	dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
DC_LOG_ERROR("Failure: unknown encoding format\n")__drm_err("Failure: unknown encoding format\n");
return DC_ERROR_UNEXPECTED;
}

link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
	&link->mst_stream_alloc_table);

/* poll for immediate branch device ACT handled */
dm_helpers_dp_mst_poll_for_allocation_change_trigger(
	stream->ctx,
	stream);

return DC_OK;
3917}

3919enum dc_status dc_link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
3920{
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc_link *link = stream->link;
struct fixed31_32 avg_time_slots_per_mtp;
struct fixed31_32 pbn;
struct fixed31_32 pbn_per_slot;
struct dc_dp_mst_stream_allocation_table proposed_table = {0};
uint8_t i;
enum act_return_status ret;
const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
DC_LOGGER_INIT(link->ctx->logger);

/* notify immediate branch device table update */
if (dm_helpers_dp_mst_write_payload_allocation_table(
		stream->ctx,
		stream,
		&proposed_table,
		true1)) {
/* update mst stream allocation table software state */
update_mst_stream_alloc_table(
		link,
		pipe_ctx->stream_res.stream_enc,
		pipe_ctx->stream_res.hpo_dp_stream_enc,
		&proposed_table);
}

DC_LOG_MST("%s  "___drm_dbg(((void *)0), DRM_UT_KMS, "%s  " "stream_count: %d: \n "
, __func__, link->mst_stream_alloc_table.stream_count)
	"stream_count: %d: \n ",___drm_dbg(((void *)0), DRM_UT_KMS, "%s  " "stream_count: %d: \n "
, __func__, link->mst_stream_alloc_table.stream_count)
	__func__,___drm_dbg(((void *)0), DRM_UT_KMS, "%s  " "stream_count: %d: \n "
, __func__, link->mst_stream_alloc_table.stream_count)
	link->mst_stream_alloc_table.stream_count)___drm_dbg(((void *)0), DRM_UT_KMS, "%s  " "stream_count: %d: \n "
, __func__, link->mst_stream_alloc_table.stream_count);

for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
DC_LOG_MST("stream_enc[%d]: %p      "___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
		"stream[%d].hpo_dp_stream_enc: %p      "___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
		"stream[%d].vcp_id: %d      "___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
		"stream[%d].slot_count: %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
		i,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
		(void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
		i,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
		(void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
		i,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
		link->mst_stream_alloc_table.stream_allocations[i].vcp_id,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
		i,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
		link->mst_stream_alloc_table.stream_allocations[i].slot_count)___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count);
}

ASSERT(proposed_table.stream_count > 0)do { if (({ static int __warned; int __ret = !!(!(proposed_table
.stream_count > 0)); if (__ret && !__warned) { printf
("WARNING %s failed at %s:%d\n", "!(proposed_table.stream_count > 0)"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link.c", 3966
); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while
 (0); } while (0);

/* update mst stream allocation table hardware state */
if (link_hwss->ext.update_stream_allocation_table == NULL((void *)0) ||
	dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
DC_LOG_ERROR("Failure: unknown encoding format\n")__drm_err("Failure: unknown encoding format\n");
return DC_ERROR_UNEXPECTED;
}

link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
	&link->mst_stream_alloc_table);

/* poll for immediate branch device ACT handled */
ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
	stream->ctx,
	stream);

if (ret != ACT_LINK_LOST) {
/* send ALLOCATE_PAYLOAD sideband message with updated pbn */
dm_helpers_dp_mst_send_payload_allocation(
		stream->ctx,
		stream,
		true1);
}

/* increase throttled vcp size */
pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
pbn_per_slot = get_pbn_per_slot(stream);
avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);

if (link_hwss->ext.set_throttled_vcp_size)
link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
if (link_hwss->ext.set_hblank_min_symbol_width)
link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
		&link->cur_link_settings,
		avg_time_slots_per_mtp);

return DC_OK;
4004}

4006static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
4007{
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc_link *link = stream->link;
struct dc_dp_mst_stream_allocation_table proposed_table = {0};
struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
int i;
bool_Bool mst_mode = (link->type == dc_connection_mst_branch);
/* adjust for drm changes*/
bool_Bool update_drm_mst_state = true1;
const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
const struct dc_link_settings empty_link_settings = {0};
DC_LOGGER_INIT(link->ctx->logger);


/* deallocate_mst_payload is called before disable link. When mode or
* disable/enable monitor, new stream is created which is not in link
* stream[] yet. For this, payload is not allocated yet, so de-alloc
* should not done. For new mode set, map_resources will get engine
* for new stream, so stream_enc->id should be validated until here.
*/

/* slot X.Y */
if (link_hwss->ext.set_throttled_vcp_size)
link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
if (link_hwss->ext.set_hblank_min_symbol_width)
link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
		&empty_link_settings,
		avg_time_slots_per_mtp);

if (mst_mode || update_drm_mst_state) {
/* when link is in mst mode, reply on mst manager to remove
 * payload
 */
if (dm_helpers_dp_mst_write_payload_allocation_table(
		stream->ctx,
		stream,
		&proposed_table,
		false0))

	update_mst_stream_alloc_table(
			link,
			pipe_ctx->stream_res.stream_enc,
			pipe_ctx->stream_res.hpo_dp_stream_enc,
			&proposed_table);
else
	DC_LOG_WARNING("Failed to update"printk("\0014" "[" "drm" "] " "Failed to update" "MST allocation table for"
 "pipe idx:%d\n", pipe_ctx->pipe_idx)
			"MST allocation table for"printk("\0014" "[" "drm" "] " "Failed to update" "MST allocation table for"
 "pipe idx:%d\n", pipe_ctx->pipe_idx)
			"pipe idx:%d\n",printk("\0014" "[" "drm" "] " "Failed to update" "MST allocation table for"
 "pipe idx:%d\n", pipe_ctx->pipe_idx)
			pipe_ctx->pipe_idx)printk("\0014" "[" "drm" "] " "Failed to update" "MST allocation table for"
 "pipe idx:%d\n", pipe_ctx->pipe_idx);
} else {
/* when link is no longer in mst mode (mst hub unplugged),
 * remove payload with default dc logic
 */
remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc,
		pipe_ctx->stream_res.hpo_dp_stream_enc);
}

DC_LOG_MST("%s"___drm_dbg(((void *)0), DRM_UT_KMS, "%s" "stream_count: %d: "
, __func__, link->mst_stream_alloc_table.stream_count)
	"stream_count: %d: ",___drm_dbg(((void *)0), DRM_UT_KMS, "%s" "stream_count: %d: "
, __func__, link->mst_stream_alloc_table.stream_count)
	__func__,___drm_dbg(((void *)0), DRM_UT_KMS, "%s" "stream_count: %d: "
, __func__, link->mst_stream_alloc_table.stream_count)
	link->mst_stream_alloc_table.stream_count)___drm_dbg(((void *)0), DRM_UT_KMS, "%s" "stream_count: %d: "
, __func__, link->mst_stream_alloc_table.stream_count);

for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
DC_LOG_MST("stream_enc[%d]: %p      "___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
"stream[%d].hpo_dp_stream_enc: %p      "___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
"stream[%d].vcp_id: %d      "___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
"stream[%d].slot_count: %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
i,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
(void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
i,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
(void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
i,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
link->mst_stream_alloc_table.stream_allocations[i].vcp_id,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
i,___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count)
link->mst_stream_alloc_table.stream_allocations[i].slot_count)___drm_dbg(((void *)0), DRM_UT_KMS, "stream_enc[%d]: %p      "
 "stream[%d].hpo_dp_stream_enc: %p      " "stream[%d].vcp_id: %d      "
 "stream[%d].slot_count: %d\n", i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].stream_enc, i, (void *) link->mst_stream_alloc_table
.stream_allocations[i].hpo_dp_stream_enc, i, link->mst_stream_alloc_table
.stream_allocations[i].vcp_id, i, link->mst_stream_alloc_table
.stream_allocations[i].slot_count);
}

/* update mst stream allocation table hardware state */
if (link_hwss->ext.update_stream_allocation_table == NULL((void *)0) ||
	dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
DC_LOG_DEBUG("Unknown encoding format\n")___drm_dbg(((void *)0), DRM_UT_KMS, "Unknown encoding format\n"
);
return DC_ERROR_UNEXPECTED;
}

link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
	&link->mst_stream_alloc_table);

if (mst_mode) {
dm_helpers_dp_mst_poll_for_allocation_change_trigger(
	stream->ctx,
	stream);

if (!update_drm_mst_state)
	dm_helpers_dp_mst_send_payload_allocation(
		stream->ctx,
		stream,
		false0);
}

if (update_drm_mst_state)
dm_helpers_dp_mst_send_payload_allocation(
	stream->ctx,
	stream,
	false0);

return DC_OK;
4113}


4116#if defined(CONFIG_DRM_AMD_DC_HDCP)
4117static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool_Bool dpms_off)
4118{
struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
struct link_encoder *link_enc = NULL((void *)0);
struct cp_psp_stream_config config = {0};
enum dp_panel_mode panel_mode =
	dp_get_panel_mode(pipe_ctx->stream->link);

if (cp_psp == NULL((void *)0) || cp_psp->funcs.update_stream_config == NULL((void *)0))
return;

link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
ASSERT(link_enc)do { if (({ static int __warned; int __ret = !!(!(link_enc));
 if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(link_enc)", "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link.c"
, 4129); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
 {} while (0); } while (0);
if (link_enc == NULL((void *)0))
return;

/* otg instance */
config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;

/* dig front end */
config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;

/* stream encoder index */
config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;
if (is_dp_128b_132b_signal(pipe_ctx))
config.stream_enc_idx =
		pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0;

/* dig back end */
config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;

/* link encoder index */
config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
if (is_dp_128b_132b_signal(pipe_ctx))
config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst;

/* dio output index is dpia index for DPIA endpoint & dcio index by default */
if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1;
else
config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;


/* phy index */
config.phy_idx = resource_transmitter_to_phy_idx(
	pipe_ctx->stream->link->dc, link_enc->transmitter);
if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
/* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */
config.phy_idx = 0;

/* stream properties */
config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0;
config.mst_enabled = (pipe_ctx->stream->signal ==
	SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0;
config.dp2_enabled = is_dp_128b_132b_signal(pipe_ctx) ? 1 : 0;
config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ?
	1 : 0;
config.dpms_off = dpms_off;

/* dm stream context */
config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;

cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
4180}
4181#endif

4183static void fpga_dp_hpo_enable_link_and_stream(struct dc_state *state, struct pipe_ctx *pipe_ctx)
4184{
struct dc *dc = pipe_ctx->stream->ctx->dc;
struct dc_stream_state *stream = pipe_ctx->stream;
struct link_mst_stream_allocation_table proposed_table = {0};
struct fixed31_32 avg_time_slots_per_mtp;
uint8_t req_slot_count = 0;
uint8_t vc_id = 1; /// VC ID always 1 for SST
struct dc_link_settings link_settings = pipe_ctx->link_config.dp_link_settings;
const struct link_hwss *link_hwss = get_link_hwss(stream->link, &pipe_ctx->link_res);
DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

stream->link->cur_link_settings = link_settings;

if (link_hwss->ext.enable_dp_link_output)
link_hwss->ext.enable_dp_link_output(stream->link, &pipe_ctx->link_res,
		stream->signal, pipe_ctx->clock_source->id,
		&link_settings);

4202#ifdef DIAGS_BUILD
/* Workaround for FPGA HPO capture DP link data:
* HPO capture will set link to active mode
* This workaround is required to get a capture from start of frame
*/
if (!dc->debug.fpga_hpo_capture_en) {
struct encoder_set_dp_phy_pattern_param params = {0};
params.dp_phy_pattern = DP_TEST_PATTERN_VIDEO_MODE;

/* Set link active */
stream->link->hpo_dp_link_enc->funcs->set_link_test_pattern(
		stream->link->hpo_dp_link_enc,
		&params);
}
4216#endif

/* Enable DP_STREAM_ENC */
dc->hwss.enable_stream(pipe_ctx);

/* Set DPS PPS SDP (AKA "info frames") */
if (pipe_ctx->stream->timing.flags.DSC) {
dp_set_dsc_pps_sdp(pipe_ctx, true1, true1);
}

/* Allocate Payload */
if ((stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) && (state->stream_count > 1)) {
// MST case
uint8_t i;

proposed_table.stream_count = state->stream_count;
for (i = 0; i < state->stream_count; i++) {
	avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(state->streams[i], state->streams[i]->link);
	req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
	proposed_table.stream_allocations[i].slot_count = req_slot_count;
	proposed_table.stream_allocations[i].vcp_id = i+1;
	/* NOTE: This makes assumption that pipe_ctx index is same as stream index */
	proposed_table.stream_allocations[i].hpo_dp_stream_enc = state->res_ctx.pipe_ctx[i].stream_res.hpo_dp_stream_enc;
}
} else {
// SST case
avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, stream->link);
req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
proposed_table.stream_count = 1; /// Always 1 stream for SST
proposed_table.stream_allocations[0].slot_count = req_slot_count;
proposed_table.stream_allocations[0].vcp_id = vc_id;
proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
}

link_hwss->ext.update_stream_allocation_table(stream->link,
	&pipe_ctx->link_res,
	&proposed_table);

if (link_hwss->ext.set_throttled_vcp_size)
link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);

dc->hwss.unblank_stream(pipe_ctx, &stream->link->cur_link_settings);
4258}

4260void core_link_enable_stream(
struct dc_state *state,
struct pipe_ctx *pipe_ctx)
4263{
struct dc *dc = pipe_ctx->stream->ctx->dc;
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc_link *link = stream->sink->link;
enum dc_status status;
struct link_encoder *link_enc;
enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

if (is_dp_128b_132b_signal(pipe_ctx))
vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;

DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

if (pipe_ctx->stream->sink) {
if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
	pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
	DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,___drm_dbg(((void *)0), DRM_UT_KMS, "%s pipe_ctx dispname=%s signal=%x\n"
, __func__, pipe_ctx->stream->sink->edid_caps.display_name
, pipe_ctx->stream->signal)
	pipe_ctx->stream->sink->edid_caps.display_name,___drm_dbg(((void *)0), DRM_UT_KMS, "%s pipe_ctx dispname=%s signal=%x\n"
, __func__, pipe_ctx->stream->sink->edid_caps.display_name
, pipe_ctx->stream->signal)
	pipe_ctx->stream->signal)___drm_dbg(((void *)0), DRM_UT_KMS, "%s pipe_ctx dispname=%s signal=%x\n"
, __func__, pipe_ctx->stream->sink->edid_caps.display_name
, pipe_ctx->stream->signal);
}
}

if (!IS_DIAG_DC(dc->ctx->dce_environment)((dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) || (
dc->ctx->dce_environment == DCE_ENV_DIAG)) &&
	dc_is_virtual_signal(pipe_ctx->stream->signal))
return;

link_enc = link_enc_cfg_get_link_enc(link);
ASSERT(link_enc)do { if (({ static int __warned; int __ret = !!(!(link_enc));
 if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(link_enc)", "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link.c"
, 4292); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
 {} while (0); } while (0);

if (!dc_is_virtual_signal(pipe_ctx->stream->signal)
	&& !is_dp_128b_132b_signal(pipe_ctx)) {
if (link_enc)
	link_enc->funcs->setup(
		link_enc,
		pipe_ctx->stream->signal);
}

pipe_ctx->stream->link->link_state_valid = true1;

if (pipe_ctx->stream_res.tg->funcs->set_out_mux) {
if (is_dp_128b_132b_signal(pipe_ctx))
	otg_out_dest = OUT_MUX_HPO_DP;
else
	otg_out_dest = OUT_MUX_DIO;
pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
}

link_hwss->setup_stream_attribute(pipe_ctx);

if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)(dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS)) {
bool_Bool apply_edp_fast_boot_optimization =
	pipe_ctx->stream->apply_edp_fast_boot_optimization;

pipe_ctx->stream->apply_edp_fast_boot_optimization = false0;

// Enable VPG before building infoframe
if (vpg && vpg->funcs->vpg_poweron)
	vpg->funcs->vpg_poweron(vpg);

resource_build_info_frame(pipe_ctx);
dc->hwss.update_info_frame(pipe_ctx);

if (dc_is_dp_signal(pipe_ctx->stream->signal))
	dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);

/* Do not touch link on seamless boot optimization. */
if (pipe_ctx->stream->apply_seamless_boot_optimization) {
	pipe_ctx->stream->dpms_off = false0;

	/* Still enable stream features & audio on seamless boot for DP external displays */
	if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
		enable_stream_features(pipe_ctx);
		if (pipe_ctx->stream_res.audio != NULL((void *)0)) {
			pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
			dc->hwss.enable_audio_stream(pipe_ctx);
		}
	}

4343#if defined(CONFIG_DRM_AMD_DC_HDCP)
	update_psp_stream_config(pipe_ctx, false0);
4345#endif
	return;
}

/* eDP lit up by bios already, no need to enable again. */
if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
			apply_edp_fast_boot_optimization &&
			!pipe_ctx->stream->timing.flags.DSC &&
			!pipe_ctx->next_odm_pipe) {
	pipe_ctx->stream->dpms_off = false0;
4355#if defined(CONFIG_DRM_AMD_DC_HDCP)
	update_psp_stream_config(pipe_ctx, false0);
4357#endif
	return;
}

if (pipe_ctx->stream->dpms_off)
	return;

/* Have to setup DSC before DIG FE and BE are connected (which happens before the
 * link training). This is to make sure the bandwidth sent to DIG BE won't be
 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
 * will be automatically set at a later time when the video is enabled
 * (DP_VID_STREAM_EN = 1).
 */
if (pipe_ctx->stream->timing.flags.DSC) {
	if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
		dc_is_virtual_signal(pipe_ctx->stream->signal))
	dp_set_dsc_enable(pipe_ctx, true1);

}

status = enable_link(state, pipe_ctx);

if (status != DC_OK) {
	DC_LOG_WARNING("enabling link %u failed: %d\n",printk("\0014" "[" "drm" "] " "enabling link %u failed: %d\n"
, pipe_ctx->stream->link->link_index, status)
	pipe_ctx->stream->link->link_index,printk("\0014" "[" "drm" "] " "enabling link %u failed: %d\n"
, pipe_ctx->stream->link->link_index, status)
	status)printk("\0014" "[" "drm" "] " "enabling link %u failed: %d\n"
, pipe_ctx->stream->link->link_index, status);

	/* Abort stream enable *unless* the failure was due to
	 * DP link training - some DP monitors will recover and
	 * show the stream anyway. But MST displays can't proceed
	 * without link training.
	 */
	if (status != DC_FAIL_DP_LINK_TRAINING ||
			pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
		if (false0 == stream->link->link_status.link_active)
			disable_link(stream->link, &pipe_ctx->link_res,
					pipe_ctx->stream->signal);
		BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__
, 4394); do {} while (0); } while (0);
		return;
	}
}

/* turn off otg test pattern if enable */
if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
	pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
			CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
			COLOR_DEPTH_UNDEFINED);

/* This second call is needed to reconfigure the DIG
 * as a workaround for the incorrect value being applied
 * from transmitter control.
 */
if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) ||
		is_dp_128b_132b_signal(pipe_ctx)))
	if (link_enc)
		link_enc->funcs->setup(
			link_enc,
			pipe_ctx->stream->signal);

dc->hwss.enable_stream(pipe_ctx);

/* Set DPS PPS SDP (AKA "info frames") */
if (pipe_ctx->stream->timing.flags.DSC) {
	if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
			dc_is_virtual_signal(pipe_ctx->stream->signal)) {
		dp_set_dsc_on_rx(pipe_ctx, true1);
		dp_set_dsc_pps_sdp(pipe_ctx, true1, true1);
	}
}

if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
	dc_link_allocate_mst_payload(pipe_ctx);
else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
		is_dp_128b_132b_signal(pipe_ctx))
	dc_link_update_sst_payload(pipe_ctx, true1);

dc->hwss.unblank_stream(pipe_ctx,
	&pipe_ctx->stream->link->cur_link_settings);

if (stream->sink_patches.delay_ignore_msa > 0)
	drm_msleep(stream->sink_patches.delay_ignore_msa)mdelay(stream->sink_patches.delay_ignore_msa);

if (dc_is_dp_signal(pipe_ctx->stream->signal))
	enable_stream_features(pipe_ctx);
4441#if defined(CONFIG_DRM_AMD_DC_HDCP)
update_psp_stream_config(pipe_ctx, false0);
4443#endif

dc->hwss.enable_audio_stream(pipe_ctx);

} else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
if (is_dp_128b_132b_signal(pipe_ctx))
	fpga_dp_hpo_enable_link_and_stream(state, pipe_ctx);
if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
		dc_is_virtual_signal(pipe_ctx->stream->signal))
	dp_set_dsc_enable(pipe_ctx, true1);
}

if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
core_link_set_avmute(pipe_ctx, false0);
}
4458}

4460void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
4461{
struct dc  *dc = pipe_ctx->stream->ctx->dc;
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc_link *link = stream->sink->link;
struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;

if (is_dp_128b_132b_signal(pipe_ctx))
1
Assuming the condition is false→
2
←
Taking false branch→
vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;

DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

if (pipe_ctx->stream->sink) {
3
←
Assuming field 'sink' is null→
if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
	pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
	DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,___drm_dbg(((void *)0), DRM_UT_KMS, "%s pipe_ctx dispname=%s signal=%x\n"
, __func__, pipe_ctx->stream->sink->edid_caps.display_name
, pipe_ctx->stream->signal)
	pipe_ctx->stream->sink->edid_caps.display_name,___drm_dbg(((void *)0), DRM_UT_KMS, "%s pipe_ctx dispname=%s signal=%x\n"
, __func__, pipe_ctx->stream->sink->edid_caps.display_name
, pipe_ctx->stream->signal)
	pipe_ctx->stream->signal)___drm_dbg(((void *)0), DRM_UT_KMS, "%s pipe_ctx dispname=%s signal=%x\n"
, __func__, pipe_ctx->stream->sink->edid_caps.display_name
, pipe_ctx->stream->signal);
}
}

if (!IS_DIAG_DC(dc->ctx->dce_environment)((dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) || (
dc->ctx->dce_environment == DCE_ENV_DIAG)) &&
4
←
Taking false branch→
5
←
Assuming field 'dce_environment' is equal to DCE_ENV_FPGA_MAXIMUS→
	dc_is_virtual_signal(pipe_ctx->stream->signal))
return;

if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {
6
←
Dereference of null pointer
if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
	core_link_set_avmute(pipe_ctx, true1);
}

dc->hwss.disable_audio_stream(pipe_ctx);

4492#if defined(CONFIG_DRM_AMD_DC_HDCP)
update_psp_stream_config(pipe_ctx, true1);
4494#endif
dc->hwss.blank_stream(pipe_ctx);

if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
deallocate_mst_payload(pipe_ctx);
else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
	is_dp_128b_132b_signal(pipe_ctx))
dc_link_update_sst_payload(pipe_ctx, false0);

if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
struct ext_hdmi_settings settings = {0};
enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;

unsigned short masked_chip_caps = link->chip_caps &
		EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
//Need to inform that sink is going to use legacy HDMI mode.
dal_ddc_service_write_scdc_data(
	link->ddc,
	165000,//vbios only handles 165Mhz.
	false0);
if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
	/* DP159, Retimer settings */
	if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
		write_i2c_retimer_setting(pipe_ctx,
				false0, false0, &settings);
	else
		write_i2c_default_retimer_setting(pipe_ctx,
				false0, false0);
} else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
	/* PI3EQX1204, Redriver settings */
	write_i2c_redriver_setting(pipe_ctx, false0);
}
}

if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
	!is_dp_128b_132b_signal(pipe_ctx)) {

/* In DP1.x SST mode, our encoder will go to TPS1
 * when link is on but stream is off.
 * Disabling link before stream will avoid exposing TPS1 pattern
 * during the disable sequence as it will confuse some receivers
 * state machine.
 * In DP2 or MST mode, our encoder will stay video active
 */
disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
dc->hwss.disable_stream(pipe_ctx);
} else {
dc->hwss.disable_stream(pipe_ctx);
disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
}

if (pipe_ctx->stream->timing.flags.DSC) {
if (dc_is_dp_signal(pipe_ctx->stream->signal))
	dp_set_dsc_enable(pipe_ctx, false0);
}
if (is_dp_128b_132b_signal(pipe_ctx)) {
if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
	pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO);
}

if (vpg && vpg->funcs->vpg_powerdown)
vpg->funcs->vpg_powerdown(vpg);
4556}

4558void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool_Bool enable)
4559{
struct dc  *dc = pipe_ctx->stream->ctx->dc;

if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
return;

dc->hwss.set_avmute(pipe_ctx, enable);
4566}

4568/**
*  dc_link_enable_hpd_filter:
*     If enable is true, programs HPD filter on associated HPD line using
*     delay_on_disconnect/delay_on_connect values dependent on
*     link->connector_signal
*
*     If enable is false, programs HPD filter on associated HPD line with no
*     delays on connect or disconnect
*
*  @link:   pointer to the dc link
*  @enable: boolean specifying whether to enable hbd
*/
4580void dc_link_enable_hpd_filter(struct dc_link *link, bool_Bool enable)
4581{
struct gpio *hpd;

if (enable) {
link->is_hpd_filter_disabled = false0;
program_hpd_filter(link);
} else {
link->is_hpd_filter_disabled = true1;
/* Obtain HPD handle */
hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);

if (!hpd)
	return;

/* Setup HPD filtering */
if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
	struct gpio_hpd_config config;

	config.delay_on_connect = 0;
	config.delay_on_disconnect = 0;

	dal_irq_setup_hpd_filter(hpd, &config);

	dal_gpio_close(hpd);
} else {
	ASSERT_CRITICAL(false)do { if (({ int __ret = !!(!(0)); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link.c"
, 4606); __builtin_expect(!!(__ret), 0); })) do {} while (0);
 } while (0);
}
/* Release HPD handle */
dal_gpio_destroy_irq(&hpd);
}
4611}

4613void dc_link_set_drive_settings(struct dc *dc,
		struct link_training_settings *lt_settings,
		const struct dc_link *link)
4616{

int i;
struct link_resource link_res;

for (i = 0; i < dc->link_count; i++)
if (dc->links[i] == link)
	break;

if (i >= dc->link_count)
ASSERT_CRITICAL(false)do { if (({ int __ret = !!(!(0)); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link.c"
, 4626); __builtin_expect(!!(__ret), 0); })) do {} while (0);
 } while (0);

dc_link_get_cur_link_res(link, &link_res);
dc_link_dp_set_drive_settings(dc->links[i], &link_res, lt_settings);
4630}

4632void dc_link_set_preferred_link_settings(struct dc *dc,
			 struct dc_link_settings *link_setting,
			 struct dc_link *link)
4635{
int i;
struct pipe_ctx *pipe;
struct dc_stream_state *link_stream;
struct dc_link_settings store_settings = *link_setting;

link->preferred_link_setting = store_settings;

/* Retrain with preferred link settings only relevant for
* DP signal type
* Check for non-DP signal or if passive dongle present
*/
if (!dc_is_dp_signal(link->connector_signal) ||
link->dongle_max_pix_clk > 0)
return;

for (i = 0; i < MAX_PIPES6; i++) {
pipe = &dc->current_state->res_ctx.pipe_ctx[i];
if (pipe->stream && pipe->stream->link) {
	if (pipe->stream->link == link) {
		link_stream = pipe->stream;
		break;
	}
}
}

/* Stream not found */
if (i == MAX_PIPES6)
return;

/* Cannot retrain link if backend is off */
if (link_stream->dpms_off)
return;

if (decide_link_settings(link_stream, &store_settings))
dp_retrain_link_dp_test(link, &store_settings, false0);
4671}

4673void dc_link_set_preferred_training_settings(struct dc *dc,
				 struct dc_link_settings *link_setting,
				 struct dc_link_training_overrides *lt_overrides,
				 struct dc_link *link,
				 bool_Bool skip_immediate_retrain)
4678{
if (lt_overrides != NULL((void *)0))
link->preferred_training_settings = *lt_overrides;
else
memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings))__builtin_memset((&link->preferred_training_settings),
 (0), (sizeof(link->preferred_training_settings)));

if (link_setting != NULL((void *)0)) {
link->preferred_link_setting = *link_setting;
if (dp_get_link_encoding_format(link_setting) == DP_128b_132b_ENCODING)
	/* TODO: add dc update for acquiring link res  */
	skip_immediate_retrain = true1;
} else {
link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
}

/* Retrain now, or wait until next stream update to apply */
if (skip_immediate_retrain == false0)
dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
4697}

4699void dc_link_enable_hpd(const struct dc_link *link)
4700{
dc_link_dp_enable_hpd(link);
4702}

4704void dc_link_disable_hpd(const struct dc_link *link)
4705{
dc_link_dp_disable_hpd(link);
4707}

4709void dc_link_set_test_pattern(struct dc_link *link,
	      enum dp_test_pattern test_pattern,
	      enum dp_test_pattern_color_space test_pattern_color_space,
	      const struct link_training_settings *p_link_settings,
	      const unsigned char *p_custom_pattern,
	      unsigned int cust_pattern_size)
4715{
if (link != NULL((void *)0))
dc_link_dp_set_test_pattern(
	link,
	test_pattern,
	test_pattern_color_space,
	p_link_settings,
	p_custom_pattern,
	cust_pattern_size);
4724}

4726uint32_t dc_link_bandwidth_kbps(
const struct dc_link *link,
const struct dc_link_settings *link_setting)
4729{
uint32_t total_data_bw_efficiency_x10000 = 0;
uint32_t link_rate_per_lane_kbps = 0;

switch (dp_get_link_encoding_format(link_setting)) {
case DP_8b_10b_ENCODING:
/* For 8b/10b encoding:
 * link rate is defined in the unit of LINK_RATE_REF_FREQ_IN_KHZ per DP byte per lane.
 * data bandwidth efficiency is 80% with additional 3% overhead if FEC is supported.
 */
link_rate_per_lane_kbps = link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000;
if (dc_link_should_enable_fec(link)) {
	total_data_bw_efficiency_x10000 /= 100;
	total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100;
}
break;
case DP_128b_132b_ENCODING:
/* For 128b/132b encoding:
 * link rate is defined in the unit of 10mbps per lane.
 * total data bandwidth efficiency is always 96.71%.
 */
link_rate_per_lane_kbps = link_setting->link_rate * 10000;
total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000;
break;
default:
break;
}

/* overall effective link bandwidth = link rate per lane * lane count * total data bandwidth efficiency */
return link_rate_per_lane_kbps * link_setting->lane_count / 10000 * total_data_bw_efficiency_x10000;
4760}

4762const struct dc_link_settings *dc_link_get_link_cap(
const struct dc_link *link)
4764{
if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
	link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
return &link->preferred_link_setting;
return &link->verified_link_cap;
4769}

4771void dc_link_overwrite_extended_receiver_cap(
struct dc_link *link)
4773{
dp_overwrite_extended_receiver_cap(link);
4775}

4777bool_Bool dc_link_is_fec_supported(const struct dc_link *link)
4778{
/* TODO - use asic cap instead of link_enc->features
* we no longer know which link enc to use for this link before commit
*/
struct link_encoder *link_enc = NULL((void *)0);

link_enc = link_enc_cfg_get_link_enc(link);
ASSERT(link_enc)do { if (({ static int __warned; int __ret = !!(!(link_enc));
 if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(link_enc)", "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link.c"
, 4785); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
 {} while (0); } while (0);

return (dc_is_dp_signal(link->connector_signal) && link_enc &&
	link_enc->features.fec_supported &&
	link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
	!IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment)(link->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS));
4791}

4793bool_Bool dc_link_should_enable_fec(const struct dc_link *link)
4794{
bool_Bool force_disable = false0;

if (link->fec_state == dc_link_fec_enabled)
force_disable = false0;
else if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
	link->local_sink &&
	link->local_sink->edid_caps.panel_patch.disable_fec)
force_disable = true1;
else if (link->connector_signal == SIGNAL_TYPE_EDP
	&& (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.
	 dsc_support.DSC_SUPPORT == false0
		|| link->panel_config.dsc.disable_dsc_edp
		|| !link->dc->caps.edp_dsc_support))
force_disable = true1;

return !force_disable && dc_link_is_fec_supported(link);
4811}

4813uint32_t dc_bandwidth_in_kbps_from_timing(
const struct dc_crtc_timing *timing)
4815{
uint32_t bits_per_channel = 0;
uint32_t kbps;

4819#if defined(CONFIG_DRM_AMD_DC_DCN1)
if (timing->flags.DSC)
return dc_dsc_stream_bandwidth_in_kbps(timing,
		timing->dsc_cfg.bits_per_pixel,
		timing->dsc_cfg.num_slices_h,
		timing->dsc_cfg.is_dp);
4825#endif /* CONFIG_DRM_AMD_DC_DCN */

switch (timing->display_color_depth) {
case COLOR_DEPTH_666:
bits_per_channel = 6;
break;
case COLOR_DEPTH_888:
bits_per_channel = 8;
break;
case COLOR_DEPTH_101010:
bits_per_channel = 10;
break;
case COLOR_DEPTH_121212:
bits_per_channel = 12;
break;
case COLOR_DEPTH_141414:
bits_per_channel = 14;
break;
case COLOR_DEPTH_161616:
bits_per_channel = 16;
break;
default:
ASSERT(bits_per_channel != 0)do { if (({ static int __warned; int __ret = !!(!(bits_per_channel
 != 0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(bits_per_channel != 0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/core/dc_link.c"
, 4847); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
 {} while (0); } while (0);
bits_per_channel = 8;
break;
}

kbps = timing->pix_clk_100hz / 10;
kbps *= bits_per_channel;

if (timing->flags.Y_ONLY != 1) {
/*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
kbps *= 3;
if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
	kbps /= 2;
else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
	kbps = kbps * 2 / 3;
}

return kbps;

4866}

4868void dc_link_get_cur_link_res(const struct dc_link *link,
struct link_resource *link_res)
4870{
int i;
struct pipe_ctx *pipe = NULL((void *)0);

memset(link_res, 0, sizeof(*link_res))__builtin_memset((link_res), (0), (sizeof(*link_res)));

for (i = 0; i < MAX_PIPES6; i++) {
pipe = &link->dc->current_state->res_ctx.pipe_ctx[i];
if (pipe->stream && pipe->stream->link && pipe->top_pipe == NULL((void *)0)) {
	if (pipe->stream->link == link) {
		*link_res = pipe->link_res;
		break;
	}
}
}

4886}

4888/**
* dc_get_cur_link_res_map() - take a snapshot of current link resource allocation state
* @dc: pointer to dc of the dm calling this
* @map: a dc link resource snapshot defined internally to dc.
*
* DM needs to capture a snapshot of current link resource allocation mapping
* and store it in its persistent storage.
*
* Some of the link resource is using first come first serve policy.
* The allocation mapping depends on original hotplug order. This information
* is lost after driver is loaded next time. The snapshot is used in order to
* restore link resource to its previous state so user will get consistent
* link capability allocation across reboot.
*
* Return: none (void function)
*
*/
4905void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map)
4906{
struct dc_link *link;
uint32_t i;
uint32_t hpo_dp_recycle_map = 0;

*map = 0;

if (dc->caps.dp_hpo) {
for (i = 0; i < dc->caps.max_links; i++) {
	link = dc->links[i];
	if (link->link_status.link_active &&
			dp_get_link_encoding_format(&link->reported_link_cap) == DP_128b_132b_ENCODING &&
			dp_get_link_encoding_format(&link->cur_link_settings) != DP_128b_132b_ENCODING)
		/* hpo dp link encoder is considered as recycled, when RX reports 128b/132b encoding capability
		 * but current link doesn't use it.
		 */
		hpo_dp_recycle_map |= (1 << i);
}
*map |= (hpo_dp_recycle_map << LINK_RES_HPO_DP_REC_MAP__SHIFT0);
}
4926}

4928/**
* dc_restore_link_res_map() - restore link resource allocation state from a snapshot
* @dc: pointer to dc of the dm calling this
* @map: a dc link resource snapshot defined internally to dc.
*
* DM needs to call this function after initial link detection on boot and
* before first commit streams to restore link resource allocation state
* from previous boot session.
*
* Some of the link resource is using first come first serve policy.
* The allocation mapping depends on original hotplug order. This information
* is lost after driver is loaded next time. The snapshot is used in order to
* restore link resource to its previous state so user will get consistent
* link capability allocation across reboot.
*
* Return: none (void function)
*
*/
4946void dc_restore_link_res_map(const struct dc *dc, uint32_t *map)
4947{
struct dc_link *link;
uint32_t i;
unsigned int available_hpo_dp_count;
uint32_t hpo_dp_recycle_map = (*map & LINK_RES_HPO_DP_REC_MAP__MASK0xFFFF)
	>> LINK_RES_HPO_DP_REC_MAP__SHIFT0;

if (dc->caps.dp_hpo) {
available_hpo_dp_count = dc->res_pool->hpo_dp_link_enc_count;
/* remove excess 128b/132b encoding support for not recycled links */
for (i = 0; i < dc->caps.max_links; i++) {
	if ((hpo_dp_recycle_map & (1 << i)) == 0) {
		link = dc->links[i];
		if (link->type != dc_connection_none &&
				dp_get_link_encoding_format(&link->verified_link_cap) == DP_128b_132b_ENCODING) {
			if (available_hpo_dp_count > 0)
				available_hpo_dp_count--;
			else
				/* remove 128b/132b encoding capability by limiting verified link rate to HBR3 */
				link->verified_link_cap.link_rate = LINK_RATE_HIGH3;
		}
	}
}
/* remove excess 128b/132b encoding support for recycled links */
for (i = 0; i < dc->caps.max_links; i++) {
	if ((hpo_dp_recycle_map & (1 << i)) != 0) {
		link = dc->links[i];
		if (link->type != dc_connection_none &&
				dp_get_link_encoding_format(&link->verified_link_cap) == DP_128b_132b_ENCODING) {
			if (available_hpo_dp_count > 0)
				available_hpo_dp_count--;
			else
				/* remove 128b/132b encoding capability by limiting verified link rate to HBR3 */
				link->verified_link_cap.link_rate = LINK_RATE_HIGH3;
		}
	}
}
}
4985}