Bug Summary

File:dev/pci/drm/amd/amdgpu/sdma_v5_0.c
Warning:line 1163, column 9
Array subscript is undefined

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name sdma_v5_0.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/delay.h>
25#include <linux/firmware.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28
29#include "amdgpu.h"
30#include "amdgpu_ucode.h"
31#include "amdgpu_trace.h"
32
33#include "gc/gc_10_1_0_offset.h"
34#include "gc/gc_10_1_0_sh_mask.h"
35#include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
36#include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
37
38#include "soc15_common.h"
39#include "soc15.h"
40#include "navi10_sdma_pkt_open.h"
41#include "nbio_v2_3.h"
42#include "sdma_common.h"
43#include "sdma_v5_0.h"
44
45MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
46MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
47
48MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
49MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
50
51MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
52MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
53
54MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma.bin");
55MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma1.bin");
56
57#define SDMA1_REG_OFFSET0x600 0x600
58#define SDMA0_HYP_DEC_REG_START0x5880 0x5880
59#define SDMA0_HYP_DEC_REG_END0x5893 0x5893
60#define SDMA1_HYP_DEC_REG_OFFSET0x20 0x20
61
62static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
63static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
64static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
65static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
66
67static const struct soc15_reg_golden golden_settings_sdma_5[] = {
68 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107){ GC_HWIP, 0, 0, 0x001d, 0xffbf1f0f, 0x03ab0107 },
69 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0087, 0xfffffff7, 0x00403000 },
70 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x00e7, 0xfffffff7, 0x00403000 },
71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0147, 0xfffffff7, 0x00403000 },
72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x01a7, 0xfffffff7, 0x00403000 },
73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0207, 0xfffffff7, 0x00403000 },
74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0267, 0xfffffff7, 0x00403000 },
75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x02c7, 0xfffffff7, 0x00403000 },
76 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0327, 0xfffffff7, 0x00403000 },
77 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0387, 0xfffffff7, 0x00403000 },
78 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x03e7, 0xfffffff7, 0x00403000 },
79 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00){ GC_HWIP, 0, 0, 0x0048, 0x00ffffff, 0x000c5c00 },
80 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107){ GC_HWIP, 0, 0, 0x061d, 0xffbf1f0f, 0x03ab0107 },
81 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0687, 0xfffffff7, 0x00403000 },
82 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x06e7, 0xfffffff7, 0x00403000 },
83 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0747, 0xfffffff7, 0x00403000 },
84 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x07a7, 0xfffffff7, 0x00403000 },
85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0807, 0xfffffff7, 0x00403000 },
86 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0867, 0xfffffff7, 0x00403000 },
87 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x08c7, 0xfffffff7, 0x00403000 },
88 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0927, 0xfffffff7, 0x00403000 },
89 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0987, 0xfffffff7, 0x00403000 },
90 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x09e7, 0xfffffff7, 0x00403000 },
91 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00){ GC_HWIP, 0, 0, 0x0648, 0x00ffffff, 0x000c5c00 }
92};
93
94static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0087, 0xfffffff7, 0x00403000 },
96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x00e7, 0xfffffff7, 0x00403000 },
97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0147, 0xfffffff7, 0x00403000 },
98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x01a7, 0xfffffff7, 0x00403000 },
99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0207, 0xfffffff7, 0x00403000 },
100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0267, 0xfffffff7, 0x00403000 },
101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x02c7, 0xfffffff7, 0x00403000 },
102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0327, 0xfffffff7, 0x00403000 },
103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0387, 0xfffffff7, 0x00403000 },
104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x03e7, 0xfffffff7, 0x00403000 },
105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0687, 0xfffffff7, 0x00403000 },
106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x06e7, 0xfffffff7, 0x00403000 },
107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0747, 0xfffffff7, 0x00403000 },
108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x07a7, 0xfffffff7, 0x00403000 },
109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0807, 0xfffffff7, 0x00403000 },
110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0867, 0xfffffff7, 0x00403000 },
111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x08c7, 0xfffffff7, 0x00403000 },
112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0927, 0xfffffff7, 0x00403000 },
113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0987, 0xfffffff7, 0x00403000 },
114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x09e7, 0xfffffff7, 0x00403000 },
115};
116
117static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000){ GC_HWIP, 0, 0, 0x0267, 0x0000fff0, 0x00403000 },
119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000){ GC_HWIP, 0, 0, 0x0867, 0x0000fff0, 0x00403000 },
120};
121
122static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0267, 0xfffffff7, 0x00403000 },
124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0867, 0xfffffff7, 0x00403000 },
125};
126
127static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0267, 0xfffffff7, 0x00403000 },
129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044){ GC_HWIP, 0, 0, 0x001e, 0x001877ff, 0x00000044 },
130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044){ GC_HWIP, 0, 0, 0x001f, 0x001877ff, 0x00000044 },
131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044){ GC_HWIP, 0, 0, 0x061e, 0x001877ff, 0x00000044 },
132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044){ GC_HWIP, 0, 0, 0x061f, 0x001877ff, 0x00000044 },
133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0867, 0xfffffff7, 0x00403000 },
134};
135
136static const struct soc15_reg_golden golden_settings_sdma_cyan_skillfish[] = {
137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107){ GC_HWIP, 0, 0, 0x001d, 0xffbf1f0f, 0x03ab0107 },
138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044){ GC_HWIP, 0, 0, 0x001e, 0x001877ff, 0x00000044 },
139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044){ GC_HWIP, 0, 0, 0x001f, 0x001877ff, 0x00000044 },
140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0087, 0xfffffff7, 0x00403000 },
141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x00e7, 0xfffffff7, 0x00403000 },
142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0147, 0xfffffff7, 0x00403000 },
143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x01a7, 0xfffffff7, 0x00403000 },
144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0207, 0xfffffff7, 0x00403000 },
145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0267, 0xfffffff7, 0x00403000 },
146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x02c7, 0xfffffff7, 0x00403000 },
147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0327, 0xfffffff7, 0x00403000 },
148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0387, 0xfffffff7, 0x00403000 },
149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x03e7, 0xfffffff7, 0x00403000 },
150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x007fffff, 0x004c5c00){ GC_HWIP, 0, 0, 0x0048, 0x007fffff, 0x004c5c00 },
151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107){ GC_HWIP, 0, 0, 0x061d, 0xffbf1f0f, 0x03ab0107 },
152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044){ GC_HWIP, 0, 0, 0x061e, 0x001877ff, 0x00000044 },
153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044){ GC_HWIP, 0, 0, 0x061f, 0x001877ff, 0x00000044 },
154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0687, 0xfffffff7, 0x00403000 },
155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x06e7, 0xfffffff7, 0x00403000 },
156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0747, 0xfffffff7, 0x00403000 },
157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x07a7, 0xfffffff7, 0x00403000 },
158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0807, 0xfffffff7, 0x00403000 },
159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0867, 0xfffffff7, 0x00403000 },
160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x08c7, 0xfffffff7, 0x00403000 },
161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0927, 0xfffffff7, 0x00403000 },
162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x0987, 0xfffffff7, 0x00403000 },
163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000){ GC_HWIP, 0, 0, 0x09e7, 0xfffffff7, 0x00403000 },
164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x007fffff, 0x004c5c00){ GC_HWIP, 0, 0, 0x0648, 0x007fffff, 0x004c5c00 }
165};
166
167static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
168{
169 u32 base;
170
171 if (internal_offset >= SDMA0_HYP_DEC_REG_START0x5880 &&
172 internal_offset <= SDMA0_HYP_DEC_REG_END0x5893) {
173 base = adev->reg_offset[GC_HWIP][0][1];
174 if (instance == 1)
175 internal_offset += SDMA1_HYP_DEC_REG_OFFSET0x20;
176 } else {
177 base = adev->reg_offset[GC_HWIP][0][0];
178 if (instance == 1)
179 internal_offset += SDMA1_REG_OFFSET0x600;
180 }
181
182 return base + internal_offset;
183}
184
185static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
186{
187 switch (adev->ip_versions[SDMA0_HWIP][0]) {
188 case IP_VERSION(5, 0, 0)(((5) << 16) | ((0) << 8) | (0)):
189 soc15_program_register_sequence(adev,
190 golden_settings_sdma_5,
191 (const u32)ARRAY_SIZE(golden_settings_sdma_5)(sizeof((golden_settings_sdma_5)) / sizeof((golden_settings_sdma_5
)[0])));
192 soc15_program_register_sequence(adev,
193 golden_settings_sdma_nv10,
194 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10)(sizeof((golden_settings_sdma_nv10)) / sizeof((golden_settings_sdma_nv10
)[0])));
195 break;
196 case IP_VERSION(5, 0, 2)(((5) << 16) | ((0) << 8) | (2)):
197 soc15_program_register_sequence(adev,
198 golden_settings_sdma_5,
199 (const u32)ARRAY_SIZE(golden_settings_sdma_5)(sizeof((golden_settings_sdma_5)) / sizeof((golden_settings_sdma_5
)[0])));
200 soc15_program_register_sequence(adev,
201 golden_settings_sdma_nv14,
202 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14)(sizeof((golden_settings_sdma_nv14)) / sizeof((golden_settings_sdma_nv14
)[0])));
203 break;
204 case IP_VERSION(5, 0, 5)(((5) << 16) | ((0) << 8) | (5)):
205 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
206 soc15_program_register_sequence(adev,
207 golden_settings_sdma_5_sriov,
208 (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov)(sizeof((golden_settings_sdma_5_sriov)) / sizeof((golden_settings_sdma_5_sriov
)[0])));
209 else
210 soc15_program_register_sequence(adev,
211 golden_settings_sdma_5,
212 (const u32)ARRAY_SIZE(golden_settings_sdma_5)(sizeof((golden_settings_sdma_5)) / sizeof((golden_settings_sdma_5
)[0])));
213 soc15_program_register_sequence(adev,
214 golden_settings_sdma_nv12,
215 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12)(sizeof((golden_settings_sdma_nv12)) / sizeof((golden_settings_sdma_nv12
)[0])));
216 break;
217 case IP_VERSION(5, 0, 1)(((5) << 16) | ((0) << 8) | (1)):
218 soc15_program_register_sequence(adev,
219 golden_settings_sdma_cyan_skillfish,
220 (const u32)ARRAY_SIZE(golden_settings_sdma_cyan_skillfish)(sizeof((golden_settings_sdma_cyan_skillfish)) / sizeof((golden_settings_sdma_cyan_skillfish
)[0])));
221 break;
222 default:
223 break;
224 }
225}
226
227/**
228 * sdma_v5_0_init_microcode - load ucode images from disk
229 *
230 * @adev: amdgpu_device pointer
231 *
232 * Use the firmware interface to load the ucode images into
233 * the driver (not loaded into hw).
234 * Returns 0 on success, error on failure.
235 */
236
237// emulation only, won't work on real chip
238// navi10 real chip need to use PSP to load firmware
239static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
240{
241 const char *chip_name;
242 char fw_name[40];
243 int ret, i;
244
245 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 0, 5)(((5) << 16) | ((0) << 8) | (5))))
246 return 0;
247
248 DRM_DEBUG("\n")___drm_dbg(((void *)0), DRM_UT_CORE, "\n");
249
250 switch (adev->ip_versions[SDMA0_HWIP][0]) {
251 case IP_VERSION(5, 0, 0)(((5) << 16) | ((0) << 8) | (0)):
252 chip_name = "navi10";
253 break;
254 case IP_VERSION(5, 0, 2)(((5) << 16) | ((0) << 8) | (2)):
255 chip_name = "navi14";
256 break;
257 case IP_VERSION(5, 0, 5)(((5) << 16) | ((0) << 8) | (5)):
258 chip_name = "navi12";
259 break;
260 case IP_VERSION(5, 0, 1)(((5) << 16) | ((0) << 8) | (1)):
261 chip_name = "cyan_skillfish2";
262 break;
263 default:
264 BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c"
, 264); } while (0);
265 }
266
267 for (i = 0; i < adev->sdma.num_instances; i++) {
268 if (i == 0)
269 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
270 else
271 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
272 ret = amdgpu_sdma_init_microcode(adev, fw_name, i, false0);
273 if (ret)
274 return ret;
275 }
276
277 return ret;
278}
279
280static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)
281{
282 unsigned ret;
283
284 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)(((9) & 0x000000FF) << 0));
285 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)((u32)(ring->cond_exe_gpu_addr)));
286 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)((u32)(((ring->cond_exe_gpu_addr) >> 16) >> 16
)));
287 amdgpu_ring_write(ring, 1);
288 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
289 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
290
291 return ret;
292}
293
294static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
295 unsigned offset)
296{
297 unsigned cur;
298
299 BUG_ON(offset > ring->buf_mask)((!(offset > ring->buf_mask)) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c", 299, "!(offset > ring->buf_mask)"
));
300 BUG_ON(ring->ring[offset] != 0x55aa55aa)((!(ring->ring[offset] != 0x55aa55aa)) ? (void)0 : __assert
("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c"
, 300, "!(ring->ring[offset] != 0x55aa55aa)"));
301
302 cur = (ring->wptr - 1) & ring->buf_mask;
303 if (cur > offset)
304 ring->ring[offset] = cur - offset;
305 else
306 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
307}
308
309/**
310 * sdma_v5_0_ring_get_rptr - get the current read pointer
311 *
312 * @ring: amdgpu ring pointer
313 *
314 * Get the current rptr from the hardware (NAVI10+).
315 */
316static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
317{
318 u64 *rptr;
319
320 /* XXX check if swapping is necessary on BE */
321 rptr = (u64 *)ring->rptr_cpu_addr;
322
323 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr)___drm_dbg(((void *)0), DRM_UT_CORE, "rptr before shift == 0x%016llx\n"
, *rptr);
324 return ((*rptr) >> 2);
325}
326
327/**
328 * sdma_v5_0_ring_get_wptr - get the current write pointer
329 *
330 * @ring: amdgpu ring pointer
331 *
332 * Get the current wptr from the hardware (NAVI10+).
333 */
334static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
335{
336 struct amdgpu_device *adev = ring->adev;
337 u64 wptr;
338
339 if (ring->use_doorbell) {
340 /* XXX check if swapping is necessary on BE */
341 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr))({ typeof(*((u64 *)ring->wptr_cpu_addr)) __tmp = *(volatile
typeof(*((u64 *)ring->wptr_cpu_addr)) *)&(*((u64 *)ring
->wptr_cpu_addr)); membar_datadep_consumer(); __tmp; });
342 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr)___drm_dbg(((void *)0), DRM_UT_CORE, "wptr/doorbell before shift == 0x%016llx\n"
, wptr);
343 } else {
344 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, sdma_v5_0_get_reg_offset(adev, ring
->me, 0x0086), 0, GC_HWIP) : amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset
(adev, ring->me, 0x0086)), 0));
345 wptr = wptr << 32;
346 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, sdma_v5_0_get_reg_offset(adev, ring
->me, 0x0085), 0, GC_HWIP) : amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset
(adev, ring->me, 0x0085)), 0));
347 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr)___drm_dbg(((void *)0), DRM_UT_CORE, "wptr before shift [%i] wptr == 0x%016llx\n"
, ring->me, wptr);
348 }
349
350 return wptr >> 2;
351}
352
353/**
354 * sdma_v5_0_ring_set_wptr - commit the write pointer
355 *
356 * @ring: amdgpu ring pointer
357 *
358 * Write the wptr back to the hardware (NAVI10+).
359 */
360static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
361{
362 struct amdgpu_device *adev = ring->adev;
363 uint32_t *wptr_saved;
364 uint32_t *is_queue_unmap;
365 uint64_t aggregated_db_index;
366 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA2].mqd_size;
367
368 DRM_DEBUG("Setting write pointer\n")___drm_dbg(((void *)0), DRM_UT_CORE, "Setting write pointer\n"
);
369 if (ring->is_mes_queue) {
370 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
371 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
372 sizeof(uint32_t));
373 aggregated_db_index =
374 amdgpu_mes_get_aggregated_doorbell_index(adev,
375 AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
376
377 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,({ typeof(*((atomic64_t *)ring->wptr_cpu_addr)) __tmp = ((
ring->wptr << 2)); *(volatile typeof(*((atomic64_t *
)ring->wptr_cpu_addr)) *)&(*((atomic64_t *)ring->wptr_cpu_addr
)) = __tmp; __tmp; })
378 ring->wptr << 2)({ typeof(*((atomic64_t *)ring->wptr_cpu_addr)) __tmp = ((
ring->wptr << 2)); *(volatile typeof(*((atomic64_t *
)ring->wptr_cpu_addr)) *)&(*((atomic64_t *)ring->wptr_cpu_addr
)) = __tmp; __tmp; });
379 *wptr_saved = ring->wptr << 2;
380 if (*is_queue_unmap) {
381 WDOORBELL64(aggregated_db_index, ring->wptr << 2)amdgpu_mm_wdoorbell64(adev, (aggregated_db_index), (ring->
wptr << 2));
382 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",___drm_dbg(((void *)0), DRM_UT_CORE, "calling WDOORBELL64(0x%08x, 0x%016llx)\n"
, ring->doorbell_index, ring->wptr << 2)
383 ring->doorbell_index, ring->wptr << 2)___drm_dbg(((void *)0), DRM_UT_CORE, "calling WDOORBELL64(0x%08x, 0x%016llx)\n"
, ring->doorbell_index, ring->wptr << 2);
384 WDOORBELL64(ring->doorbell_index, ring->wptr << 2)amdgpu_mm_wdoorbell64(adev, (ring->doorbell_index), (ring->
wptr << 2));
385 } else {
386 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",___drm_dbg(((void *)0), DRM_UT_CORE, "calling WDOORBELL64(0x%08x, 0x%016llx)\n"
, ring->doorbell_index, ring->wptr << 2)
387 ring->doorbell_index, ring->wptr << 2)___drm_dbg(((void *)0), DRM_UT_CORE, "calling WDOORBELL64(0x%08x, 0x%016llx)\n"
, ring->doorbell_index, ring->wptr << 2);
388 WDOORBELL64(ring->doorbell_index, ring->wptr << 2)amdgpu_mm_wdoorbell64(adev, (ring->doorbell_index), (ring->
wptr << 2));
389
390 if (*is_queue_unmap)
391 WDOORBELL64(aggregated_db_index,amdgpu_mm_wdoorbell64(adev, (aggregated_db_index), (ring->
wptr << 2))
392 ring->wptr << 2)amdgpu_mm_wdoorbell64(adev, (aggregated_db_index), (ring->
wptr << 2));
393 }
394 } else {
395 if (ring->use_doorbell) {
396 DRM_DEBUG("Using doorbell -- "___drm_dbg(((void *)0), DRM_UT_CORE, "Using doorbell -- " "wptr_offs == 0x%08x "
"lower_32_bits(ring->wptr) << 2 == 0x%08x " "upper_32_bits(ring->wptr) << 2 == 0x%08x\n"
, ring->wptr_offs, ((u32)(ring->wptr << 2)), ((u32
)(((ring->wptr << 2) >> 16) >> 16)))
397 "wptr_offs == 0x%08x "___drm_dbg(((void *)0), DRM_UT_CORE, "Using doorbell -- " "wptr_offs == 0x%08x "
"lower_32_bits(ring->wptr) << 2 == 0x%08x " "upper_32_bits(ring->wptr) << 2 == 0x%08x\n"
, ring->wptr_offs, ((u32)(ring->wptr << 2)), ((u32
)(((ring->wptr << 2) >> 16) >> 16)))
398 "lower_32_bits(ring->wptr) << 2 == 0x%08x "___drm_dbg(((void *)0), DRM_UT_CORE, "Using doorbell -- " "wptr_offs == 0x%08x "
"lower_32_bits(ring->wptr) << 2 == 0x%08x " "upper_32_bits(ring->wptr) << 2 == 0x%08x\n"
, ring->wptr_offs, ((u32)(ring->wptr << 2)), ((u32
)(((ring->wptr << 2) >> 16) >> 16)))
399 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",___drm_dbg(((void *)0), DRM_UT_CORE, "Using doorbell -- " "wptr_offs == 0x%08x "
"lower_32_bits(ring->wptr) << 2 == 0x%08x " "upper_32_bits(ring->wptr) << 2 == 0x%08x\n"
, ring->wptr_offs, ((u32)(ring->wptr << 2)), ((u32
)(((ring->wptr << 2) >> 16) >> 16)))
400 ring->wptr_offs,___drm_dbg(((void *)0), DRM_UT_CORE, "Using doorbell -- " "wptr_offs == 0x%08x "
"lower_32_bits(ring->wptr) << 2 == 0x%08x " "upper_32_bits(ring->wptr) << 2 == 0x%08x\n"
, ring->wptr_offs, ((u32)(ring->wptr << 2)), ((u32
)(((ring->wptr << 2) >> 16) >> 16)))
401 lower_32_bits(ring->wptr << 2),___drm_dbg(((void *)0), DRM_UT_CORE, "Using doorbell -- " "wptr_offs == 0x%08x "
"lower_32_bits(ring->wptr) << 2 == 0x%08x " "upper_32_bits(ring->wptr) << 2 == 0x%08x\n"
, ring->wptr_offs, ((u32)(ring->wptr << 2)), ((u32
)(((ring->wptr << 2) >> 16) >> 16)))
402 upper_32_bits(ring->wptr << 2))___drm_dbg(((void *)0), DRM_UT_CORE, "Using doorbell -- " "wptr_offs == 0x%08x "
"lower_32_bits(ring->wptr) << 2 == 0x%08x " "upper_32_bits(ring->wptr) << 2 == 0x%08x\n"
, ring->wptr_offs, ((u32)(ring->wptr << 2)), ((u32
)(((ring->wptr << 2) >> 16) >> 16)));
403 /* XXX check if swapping is necessary on BE */
404 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,({ typeof(*((atomic64_t *)ring->wptr_cpu_addr)) __tmp = ((
ring->wptr << 2)); *(volatile typeof(*((atomic64_t *
)ring->wptr_cpu_addr)) *)&(*((atomic64_t *)ring->wptr_cpu_addr
)) = __tmp; __tmp; })
405 ring->wptr << 2)({ typeof(*((atomic64_t *)ring->wptr_cpu_addr)) __tmp = ((
ring->wptr << 2)); *(volatile typeof(*((atomic64_t *
)ring->wptr_cpu_addr)) *)&(*((atomic64_t *)ring->wptr_cpu_addr
)) = __tmp; __tmp; });
406 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",___drm_dbg(((void *)0), DRM_UT_CORE, "calling WDOORBELL64(0x%08x, 0x%016llx)\n"
, ring->doorbell_index, ring->wptr << 2)
407 ring->doorbell_index, ring->wptr << 2)___drm_dbg(((void *)0), DRM_UT_CORE, "calling WDOORBELL64(0x%08x, 0x%016llx)\n"
, ring->doorbell_index, ring->wptr << 2);
408 WDOORBELL64(ring->doorbell_index, ring->wptr << 2)amdgpu_mm_wdoorbell64(adev, (ring->doorbell_index), (ring->
wptr << 2));
409 } else {
410 DRM_DEBUG("Not using doorbell -- "___drm_dbg(((void *)0), DRM_UT_CORE, "Not using doorbell -- "
"mmSDMA%i_GFX_RB_WPTR == 0x%08x " "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n"
, ring->me, ((u32)(ring->wptr << 2)), ring->me
, ((u32)(((ring->wptr << 2) >> 16) >> 16
)))
411 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "___drm_dbg(((void *)0), DRM_UT_CORE, "Not using doorbell -- "
"mmSDMA%i_GFX_RB_WPTR == 0x%08x " "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n"
, ring->me, ((u32)(ring->wptr << 2)), ring->me
, ((u32)(((ring->wptr << 2) >> 16) >> 16
)))
412 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",___drm_dbg(((void *)0), DRM_UT_CORE, "Not using doorbell -- "
"mmSDMA%i_GFX_RB_WPTR == 0x%08x " "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n"
, ring->me, ((u32)(ring->wptr << 2)), ring->me
, ((u32)(((ring->wptr << 2) >> 16) >> 16
)))
413 ring->me,___drm_dbg(((void *)0), DRM_UT_CORE, "Not using doorbell -- "
"mmSDMA%i_GFX_RB_WPTR == 0x%08x " "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n"
, ring->me, ((u32)(ring->wptr << 2)), ring->me
, ((u32)(((ring->wptr << 2) >> 16) >> 16
)))
414 lower_32_bits(ring->wptr << 2),___drm_dbg(((void *)0), DRM_UT_CORE, "Not using doorbell -- "
"mmSDMA%i_GFX_RB_WPTR == 0x%08x " "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n"
, ring->me, ((u32)(ring->wptr << 2)), ring->me
, ((u32)(((ring->wptr << 2) >> 16) >> 16
)))
415 ring->me,___drm_dbg(((void *)0), DRM_UT_CORE, "Not using doorbell -- "
"mmSDMA%i_GFX_RB_WPTR == 0x%08x " "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n"
, ring->me, ((u32)(ring->wptr << 2)), ring->me
, ((u32)(((ring->wptr << 2) >> 16) >> 16
)))
416 upper_32_bits(ring->wptr << 2))___drm_dbg(((void *)0), DRM_UT_CORE, "Not using doorbell -- "
"mmSDMA%i_GFX_RB_WPTR == 0x%08x " "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n"
, ring->me, ((u32)(ring->wptr << 2)), ring->me
, ((u32)(((ring->wptr << 2) >> 16) >> 16
)));
417 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, ring
->me, 0x0085), ((u32)(ring->wptr << 2)), 0, GC_HWIP
) : amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset(adev, ring
->me, 0x0085)), (((u32)(ring->wptr << 2))), 0))
418 ring->me, mmSDMA0_GFX_RB_WPTR),((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, ring
->me, 0x0085), ((u32)(ring->wptr << 2)), 0, GC_HWIP
) : amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset(adev, ring
->me, 0x0085)), (((u32)(ring->wptr << 2))), 0))
419 lower_32_bits(ring->wptr << 2))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, ring
->me, 0x0085), ((u32)(ring->wptr << 2)), 0, GC_HWIP
) : amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset(adev, ring
->me, 0x0085)), (((u32)(ring->wptr << 2))), 0));
420 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, ring
->me, 0x0086), ((u32)(((ring->wptr << 2) >>
16) >> 16)), 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset
(adev, ring->me, 0x0086)), (((u32)(((ring->wptr <<
2) >> 16) >> 16))), 0))
421 ring->me, mmSDMA0_GFX_RB_WPTR_HI),((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, ring
->me, 0x0086), ((u32)(((ring->wptr << 2) >>
16) >> 16)), 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset
(adev, ring->me, 0x0086)), (((u32)(((ring->wptr <<
2) >> 16) >> 16))), 0))
422 upper_32_bits(ring->wptr << 2))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, ring
->me, 0x0086), ((u32)(((ring->wptr << 2) >>
16) >> 16)), 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset
(adev, ring->me, 0x0086)), (((u32)(((ring->wptr <<
2) >> 16) >> 16))), 0));
423 }
424 }
425}
426
427static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
428{
429 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
430 int i;
431
432 for (i = 0; i < count; i++)
433 if (sdma && sdma->burst_nop && (i == 0))
434 amdgpu_ring_write(ring, ring->funcs->nop |
435 SDMA_PKT_NOP_HEADER_COUNT(count - 1)(((count - 1) & 0x00003FFF) << 16));
436 else
437 amdgpu_ring_write(ring, ring->funcs->nop);
438}
439
440/**
441 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
442 *
443 * @ring: amdgpu ring pointer
444 * @job: job to retrieve vmid from
445 * @ib: IB object to schedule
446 * @flags: unused
447 *
448 * Schedule an IB in the DMA ring (NAVI10).
449 */
450static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
451 struct amdgpu_job *job,
452 struct amdgpu_ib *ib,
453 uint32_t flags)
454{
455 unsigned vmid = AMDGPU_JOB_GET_VMID(job)((job) ? (job)->vmid : 0);
456 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
457
458 /* An IB packet must end on a 8 DW boundary--the next dword
459 * must be on a 8-dword boundary. Our IB packet below is 6
460 * dwords long, thus add x number of NOPs, such that, in
461 * modular arithmetic,
462 * wptr + 6 + x = 8k, k >= 0, which in C is,
463 * (wptr + 6 + x) % 8 = 0.
464 * The expression below, is a solution of x.
465 */
466 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)((u32)(ring->wptr))) & 7);
467
468 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT)(((4) & 0x000000FF) << 0) |
469 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)(((vmid & 0xf) & 0x0000000F) << 16));
470 /* base must be 32 byte aligned */
471 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)((u32)(ib->gpu_addr)) & 0xffffffe0);
472 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)((u32)(((ib->gpu_addr) >> 16) >> 16)));
473 amdgpu_ring_write(ring, ib->length_dw);
474 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)((u32)(csa_mc_addr)));
475 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)((u32)(((csa_mc_addr) >> 16) >> 16)));
476}
477
478/**
479 * sdma_v5_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
480 *
481 * @ring: amdgpu ring pointer
482 *
483 * flush the IB by graphics cache rinse.
484 */
485static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
486{
487 uint32_t gcr_cntl = SDMA_GCR_GL2_INV(1 << 14) | SDMA_GCR_GL2_WB(1 << 15) | SDMA_GCR_GLM_INV(1 << 5) |
488 SDMA_GCR_GL1_INV(1 << 9) | SDMA_GCR_GLV_INV(1 << 8) | SDMA_GCR_GLK_INV(1 << 7) |
489 SDMA_GCR_GLI_INV(1)(((1) & 0x3) << 0);
490
491 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
492 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)(((17) & 0x000000FF) << 0));
493 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)(((0) & 0x01FFFFFF) << 7));
494 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl)(((gcr_cntl) & 0x0000FFFF) << 16) |
495 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)(((0) & 0x0000FFFF) << 0));
496 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0)(((0) & 0x01FFFFFF) << 7) |
497 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)(((gcr_cntl >> 16) & 0x00000007) << 0));
498 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0)(((0) & 0x0000FFFF) << 0) |
499 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)(((0) & 0x0000000F) << 24));
500}
501
502/**
503 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
504 *
505 * @ring: amdgpu ring pointer
506 *
507 * Emit an hdp flush packet on the requested DMA ring.
508 */
509static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
510{
511 struct amdgpu_device *adev = ring->adev;
512 u32 ref_and_mask = 0;
513 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
514
515 if (ring->me == 0)
516 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
517 else
518 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
519
520 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM)(((8) & 0x000000FF) << 0) |
521 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1)(((1) & 0x00000001) << 26) |
522 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)(((3) & 0x00000007) << 28)); /* == */
523 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
524 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
525 amdgpu_ring_write(ring, ref_and_mask); /* reference */
526 amdgpu_ring_write(ring, ref_and_mask); /* mask */
527 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff)(((0xfff) & 0x00000FFF) << 16) |
528 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)(((10) & 0x0000FFFF) << 0)); /* retry count, poll interval */
529}
530
531/**
532 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
533 *
534 * @ring: amdgpu ring pointer
535 * @addr: address
536 * @seq: sequence number
537 * @flags: fence related flags
538 *
539 * Add a DMA fence packet to the ring to write
540 * the fence seq number and DMA trap packet to generate
541 * an interrupt if needed (NAVI10).
542 */
543static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
544 unsigned flags)
545{
546 bool_Bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT(1 << 0);
547 /* write the fence */
548 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)(((5) & 0x000000FF) << 0) |
549 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)(((0x3) & 0x00000007) << 16)); /* Ucached(UC) */
550 /* zero in first two bits */
551 BUG_ON(addr & 0x3)((!(addr & 0x3)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c"
, 551, "!(addr & 0x3)"));
552 amdgpu_ring_write(ring, lower_32_bits(addr)((u32)(addr)));
553 amdgpu_ring_write(ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)));
554 amdgpu_ring_write(ring, lower_32_bits(seq)((u32)(seq)));
555
556 /* optionally write high bits as well */
557 if (write64bit) {
558 addr += 4;
559 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)(((5) & 0x000000FF) << 0) |
560 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)(((0x3) & 0x00000007) << 16));
561 /* zero in first two bits */
562 BUG_ON(addr & 0x3)((!(addr & 0x3)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c"
, 562, "!(addr & 0x3)"));
563 amdgpu_ring_write(ring, lower_32_bits(addr)((u32)(addr)));
564 amdgpu_ring_write(ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)));
565 amdgpu_ring_write(ring, upper_32_bits(seq)((u32)(((seq) >> 16) >> 16)));
566 }
567
568 if (flags & AMDGPU_FENCE_FLAG_INT(1 << 1)) {
569 uint32_t ctx = ring->is_mes_queue ?
570 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG0x1000000u) : 0;
571 /* generate an interrupt */
572 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)(((6) & 0x000000FF) << 0));
573 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx)(((ctx) & 0x0FFFFFFF) << 0));
574 }
575}
576
577
578/**
579 * sdma_v5_0_gfx_stop - stop the gfx async dma engines
580 *
581 * @adev: amdgpu_device pointer
582 *
583 * Stop the gfx async dma ring buffers (NAVI10).
584 */
585static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
586{
587 u32 rb_cntl, ib_cntl;
588 int i;
589
590 amdgpu_sdma_unset_buffer_funcs_helper(adev);
591
592 for (i = 0; i < adev->sdma.num_instances; i++) {
593 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x0080), 0, GC_HWIP) : amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x0080)), 0));
594 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0)(((rb_cntl) & ~0x00000001L) | (0x00000001L & ((0) <<
0x0)));
595 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x0080), rb_cntl, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x0080)), (rb_cntl), 0));
596 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x008a), 0, GC_HWIP) : amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x008a)), 0));
597 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0)(((ib_cntl) & ~0x00000001L) | (0x00000001L & ((0) <<
0x0)));
598 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x008a), ib_cntl, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x008a)), (ib_cntl), 0));
599 }
600}
601
602/**
603 * sdma_v5_0_rlc_stop - stop the compute async dma engines
604 *
605 * @adev: amdgpu_device pointer
606 *
607 * Stop the compute async dma queues (NAVI10).
608 */
609static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
610{
611 /* XXX todo */
612}
613
614/**
615 * sdma_v5_0_ctx_switch_enable - stop the async dma engines context switch
616 *
617 * @adev: amdgpu_device pointer
618 * @enable: enable/disable the DMA MEs context switch.
619 *
620 * Halt or unhalt the async dma engines context switch (NAVI10).
621 */
622static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool_Bool enable)
623{
624 u32 f32_cntl = 0, phase_quantum = 0;
625 int i;
626
627 if (amdgpu_sdma_phase_quantum) {
628 unsigned value = amdgpu_sdma_phase_quantum;
629 unsigned unit = 0;
630
631 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK0x00FFFF00L >>
632 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT0x8)) {
633 value = (value + 1) >> 1;
634 unit++;
635 }
636 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK0x0000000FL >>
637 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT0x0)) {
638 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK0x00FFFF00L >>
639 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT0x8);
640 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK0x0000000FL >>
641 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT0x0);
642 WARN_ONCE(1,({ static int __warned; int __ret = !!(1); if (__ret &&
!__warned) { printf("clamping sdma_phase_quantum to %uK clock cycles\n"
, value << unit); __warned = 1; } __builtin_expect(!!(__ret
), 0); })
643 "clamping sdma_phase_quantum to %uK clock cycles\n",({ static int __warned; int __ret = !!(1); if (__ret &&
!__warned) { printf("clamping sdma_phase_quantum to %uK clock cycles\n"
, value << unit); __warned = 1; } __builtin_expect(!!(__ret
), 0); })
644 value << unit)({ static int __warned; int __ret = !!(1); if (__ret &&
!__warned) { printf("clamping sdma_phase_quantum to %uK clock cycles\n"
, value << unit); __warned = 1; } __builtin_expect(!!(__ret
), 0); });
645 }
646 phase_quantum =
647 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT0x8 |
648 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT0x0;
649 }
650
651 for (i = 0; i < adev->sdma.num_instances; i++) {
652 if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
653 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL))amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x001c
)), 0);
654 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,(((f32_cntl) & ~0x00040000L) | (0x00040000L & ((enable
? 1 : 0) << 0x12)))
655 AUTO_CTXSW_ENABLE, enable ? 1 : 0)(((f32_cntl) & ~0x00040000L) | (0x00040000L & ((enable
? 1 : 0) << 0x12)));
656 }
657
658 if (enable && amdgpu_sdma_phase_quantum) {
659 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x002c), phase_quantum, 0, GC_HWIP) : amdgpu_device_wreg(adev
, (sdma_v5_0_get_reg_offset(adev, i, 0x002c)), (phase_quantum
), 0))
660 phase_quantum)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x002c), phase_quantum, 0, GC_HWIP) : amdgpu_device_wreg(adev
, (sdma_v5_0_get_reg_offset(adev, i, 0x002c)), (phase_quantum
), 0));
661 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x002d), phase_quantum, 0, GC_HWIP) : amdgpu_device_wreg(adev
, (sdma_v5_0_get_reg_offset(adev, i, 0x002d)), (phase_quantum
), 0))
662 phase_quantum)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x002d), phase_quantum, 0, GC_HWIP) : amdgpu_device_wreg(adev
, (sdma_v5_0_get_reg_offset(adev, i, 0x002d)), (phase_quantum
), 0));
663 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x004f), phase_quantum, 0, GC_HWIP) : amdgpu_device_wreg(adev
, (sdma_v5_0_get_reg_offset(adev, i, 0x004f)), (phase_quantum
), 0))
664 phase_quantum)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x004f), phase_quantum, 0, GC_HWIP) : amdgpu_device_wreg(adev
, (sdma_v5_0_get_reg_offset(adev, i, 0x004f)), (phase_quantum
), 0));
665 }
666 if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
667 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl)amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x001c
)), (f32_cntl), 0);
668 }
669
670}
671
672/**
673 * sdma_v5_0_enable - stop the async dma engines
674 *
675 * @adev: amdgpu_device pointer
676 * @enable: enable/disable the DMA MEs.
677 *
678 * Halt or unhalt the async dma engines (NAVI10).
679 */
680static void sdma_v5_0_enable(struct amdgpu_device *adev, bool_Bool enable)
681{
682 u32 f32_cntl;
683 int i;
684
685 if (!enable) {
686 sdma_v5_0_gfx_stop(adev);
687 sdma_v5_0_rlc_stop(adev);
688 }
689
690 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
691 return;
692
693 for (i = 0; i < adev->sdma.num_instances; i++) {
694 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL))amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x002a
)), 0);
695 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1)(((f32_cntl) & ~0x00000001L) | (0x00000001L & ((enable
? 0 : 1) << 0x0)));
696 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl)amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x002a
)), (f32_cntl), 0);
697 }
698}
699
700/**
701 * sdma_v5_0_gfx_resume - setup and start the async dma engines
702 *
703 * @adev: amdgpu_device pointer
704 *
705 * Set up the gfx DMA ring buffers and enable them (NAVI10).
706 * Returns 0 for success, error for failure.
707 */
708static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
709{
710 struct amdgpu_ring *ring;
711 u32 rb_cntl, ib_cntl;
712 u32 rb_bufsz;
713 u32 doorbell;
714 u32 doorbell_offset;
715 u32 temp;
716 u32 wptr_poll_cntl;
717 u64 wptr_gpu_addr;
718 int i, r;
719
720 for (i = 0; i < adev->sdma.num_instances; i++) {
721 ring = &adev->sdma.instance[i].ring;
722
723 if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
724 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0)amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x0021
)), (0), 0);
725
726 /* Set ring buffer size in dwords */
727 rb_bufsz = order_base_2(ring->ring_size / 4)drm_order(ring->ring_size / 4);
728 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x0080), 0, GC_HWIP) : amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x0080)), 0));
729 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz)(((rb_cntl) & ~0x0000003EL) | (0x0000003EL & ((rb_bufsz
) << 0x1)));
730#ifdef __BIG_ENDIAN
731 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1)(((rb_cntl) & ~0x00000200L) | (0x00000200L & ((1) <<
0x9)));
732 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,(((rb_cntl) & ~0x00002000L) | (0x00002000L & ((1) <<
0xd)))
733 RPTR_WRITEBACK_SWAP_ENABLE, 1)(((rb_cntl) & ~0x00002000L) | (0x00002000L & ((1) <<
0xd)));
734#endif
735 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x0080), rb_cntl, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x0080)), (rb_cntl), 0));
736
737 /* Initialize the ring buffer's read and write pointers */
738 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x0083), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x0083)), (0), 0));
739 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x0084), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x0084)), (0), 0));
740 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x0085), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x0085)), (0), 0));
741 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x0086), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x0086)), (0), 0));
742
743 /* setup the wptr shadow polling */
744 wptr_gpu_addr = ring->wptr_gpu_addr;
745 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x00b3), ((u32)(wptr_gpu_addr)), 0, GC_HWIP) : amdgpu_device_wreg
(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x00b3)), (((u32)(wptr_gpu_addr
))), 0))
746 lower_32_bits(wptr_gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x00b3), ((u32)(wptr_gpu_addr)), 0, GC_HWIP) : amdgpu_device_wreg
(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x00b3)), (((u32)(wptr_gpu_addr
))), 0));
747 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x00b2), ((u32)(((wptr_gpu_addr) >> 16) >> 16)),
0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x00b2)), (((u32)(((wptr_gpu_addr) >> 16) >>
16))), 0))
748 upper_32_bits(wptr_gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x00b2), ((u32)(((wptr_gpu_addr) >> 16) >> 16)),
0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x00b2)), (((u32)(((wptr_gpu_addr) >> 16) >>
16))), 0));
749 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x0087), 0, GC_HWIP) : amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x0087)), 0))
750 mmSDMA0_GFX_RB_WPTR_POLL_CNTL))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x0087), 0, GC_HWIP) : amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x0087)), 0));
751 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,(((wptr_poll_cntl) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)))
752 SDMA0_GFX_RB_WPTR_POLL_CNTL,(((wptr_poll_cntl) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)))
753 F32_POLL_ENABLE, 1)(((wptr_poll_cntl) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)));
754 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x0087), wptr_poll_cntl, 0, GC_HWIP) : amdgpu_device_wreg(adev
, (sdma_v5_0_get_reg_offset(adev, i, 0x0087)), (wptr_poll_cntl
), 0))
755 wptr_poll_cntl)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x0087), wptr_poll_cntl, 0, GC_HWIP) : amdgpu_device_wreg(adev
, (sdma_v5_0_get_reg_offset(adev, i, 0x0087)), (wptr_poll_cntl
), 0));
756
757 /* set the wb address whether it's enabled or not */
758 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x0088), ((u32)(((ring->rptr_gpu_addr) >> 16) >>
16)) & 0xFFFFFFFF, 0, GC_HWIP) : amdgpu_device_wreg(adev
, (sdma_v5_0_get_reg_offset(adev, i, 0x0088)), (((u32)(((ring
->rptr_gpu_addr) >> 16) >> 16)) & 0xFFFFFFFF
), 0))
759 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x0088), ((u32)(((ring->rptr_gpu_addr) >> 16) >>
16)) & 0xFFFFFFFF, 0, GC_HWIP) : amdgpu_device_wreg(adev
, (sdma_v5_0_get_reg_offset(adev, i, 0x0088)), (((u32)(((ring
->rptr_gpu_addr) >> 16) >> 16)) & 0xFFFFFFFF
), 0));
760 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x0089), ((u32)(ring->rptr_gpu_addr)) & 0xFFFFFFFC, 0
, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x0089)), (((u32)(ring->rptr_gpu_addr)) & 0xFFFFFFFC
), 0))
761 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x0089), ((u32)(ring->rptr_gpu_addr)) & 0xFFFFFFFC, 0
, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x0089)), (((u32)(ring->rptr_gpu_addr)) & 0xFFFFFFFC
), 0));
762
763 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1)(((rb_cntl) & ~0x00001000L) | (0x00001000L & ((1) <<
0xc)));
764
765 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x0081), ring->gpu_addr >> 8, 0, GC_HWIP) : amdgpu_device_wreg
(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x0081)), (ring->
gpu_addr >> 8), 0))
766 ring->gpu_addr >> 8)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x0081), ring->gpu_addr >> 8, 0, GC_HWIP) : amdgpu_device_wreg
(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x0081)), (ring->
gpu_addr >> 8), 0));
767 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x0082), ring->gpu_addr >> 40, 0, GC_HWIP) : amdgpu_device_wreg
(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x0082)), (ring->
gpu_addr >> 40), 0))
768 ring->gpu_addr >> 40)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x0082), ring->gpu_addr >> 40, 0, GC_HWIP) : amdgpu_device_wreg
(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x0082)), (ring->
gpu_addr >> 40), 0));
769
770 ring->wptr = 0;
771
772 /* before programing wptr to a less value, need set minor_ptr_update first */
773 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x00b5), 1, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x00b5)), (1), 0));
774
775 if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { /* only bare-metal use register write for wptr */
776 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x0085
)), (((u32)(ring->wptr << 2))), 0)
777 lower_32_bits(ring->wptr << 2))amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x0085
)), (((u32)(ring->wptr << 2))), 0);
778 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x0086
)), (((u32)(((ring->wptr << 2) >> 16) >>
16))), 0)
779 upper_32_bits(ring->wptr << 2))amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x0086
)), (((u32)(((ring->wptr << 2) >> 16) >>
16))), 0);
780 }
781
782 doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x0092), 0, GC_HWIP) : amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x0092)), 0));
783 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x00ab), 0, GC_HWIP) : amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x00ab)), 0))
784 mmSDMA0_GFX_DOORBELL_OFFSET))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x00ab), 0, GC_HWIP) : amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x00ab)), 0));
785
786 if (ring->use_doorbell) {
787 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1)(((doorbell) & ~0x10000000L) | (0x10000000L & ((1) <<
0x1c)));
788 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,(((doorbell_offset) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & (
(ring->doorbell_index) << 0x2)))
789 OFFSET, ring->doorbell_index)(((doorbell_offset) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & (
(ring->doorbell_index) << 0x2)));
790 } else {
791 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0)(((doorbell) & ~0x10000000L) | (0x10000000L & ((0) <<
0x1c)));
792 }
793 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x0092), doorbell, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x0092)), (doorbell), 0));
794 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x00ab), doorbell_offset, 0, GC_HWIP) : amdgpu_device_wreg(adev
, (sdma_v5_0_get_reg_offset(adev, i, 0x00ab)), (doorbell_offset
), 0))
795 doorbell_offset)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x00ab), doorbell_offset, 0, GC_HWIP) : amdgpu_device_wreg(adev
, (sdma_v5_0_get_reg_offset(adev, i, 0x00ab)), (doorbell_offset
), 0));
796
797 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
798 ring->doorbell_index, 20);
799
800 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
801 sdma_v5_0_ring_set_wptr(ring);
802
803 /* set minor_ptr_update to 0 after wptr programed */
804 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x00b5), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x00b5)), (0), 0));
805
806 if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
807 /* set utc l1 enable flag always to 1 */
808 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL))amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x001c
)), 0);
809 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1)(((temp) & ~0x00000002L) | (0x00000002L & ((1) <<
0x1)));
810
811 /* enable MCBP */
812 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1)(((temp) & ~0x00000020L) | (0x00000020L & ((1) <<
0x5)));
813 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp)amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x001c
)), (temp), 0);
814
815 /* Set up RESP_MODE to non-copy addresses */
816 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL))amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x003c
)), 0);
817 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3)(((temp) & ~0x00000E00L) | (0x00000E00L & ((3) <<
0x9)));
818 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9)(((temp) & ~0x0000003EL) | (0x0000003EL & ((9) <<
0x1)));
819 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp)amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x003c
)), (temp), 0);
820
821 /* program default cache read and write policy */
822 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE))amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x0048
)), 0);
823 /* clean read policy and write policy bits */
824 temp &= 0xFF0FFF;
825 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
826 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp)amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x0048
)), (temp), 0);
827 }
828
829 if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
830 /* unhalt engine */
831 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL))amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x002a
)), 0);
832 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0)(((temp) & ~0x00000001L) | (0x00000001L & ((0) <<
0x0)));
833 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp)amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x002a
)), (temp), 0);
834 }
835
836 /* enable DMA RB */
837 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1)(((rb_cntl) & ~0x00000001L) | (0x00000001L & ((1) <<
0x0)));
838 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x0080), rb_cntl, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x0080)), (rb_cntl), 0));
839
840 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x008a), 0, GC_HWIP) : amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x008a)), 0));
841 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1)(((ib_cntl) & ~0x00000001L) | (0x00000001L & ((1) <<
0x0)));
842#ifdef __BIG_ENDIAN
843 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1)(((ib_cntl) & ~0x00000010L) | (0x00000010L & ((1) <<
0x4)));
844#endif
845 /* enable DMA IBs */
846 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, sdma_v5_0_get_reg_offset(adev, i,
0x008a), ib_cntl, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset
(adev, i, 0x008a)), (ib_cntl), 0));
847
848 ring->sched.ready = true1;
849
850 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { /* bare-metal sequence doesn't need below to lines */
851 sdma_v5_0_ctx_switch_enable(adev, true1);
852 sdma_v5_0_enable(adev, true1);
853 }
854
855 r = amdgpu_ring_test_helper(ring);
856 if (r)
857 return r;
858
859 if (adev->mman.buffer_funcs_ring == ring)
860 amdgpu_ttm_set_buffer_funcs_status(adev, true1);
861 }
862
863 return 0;
864}
865
866/**
867 * sdma_v5_0_rlc_resume - setup and start the async dma engines
868 *
869 * @adev: amdgpu_device pointer
870 *
871 * Set up the compute DMA queues and enable them (NAVI10).
872 * Returns 0 for success, error for failure.
873 */
874static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
875{
876 return 0;
877}
878
879/**
880 * sdma_v5_0_load_microcode - load the sDMA ME ucode
881 *
882 * @adev: amdgpu_device pointer
883 *
884 * Loads the sDMA0/1 ucode.
885 * Returns 0 for success, -EINVAL if the ucode is not available.
886 */
887static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
888{
889 const struct sdma_firmware_header_v1_0 *hdr;
890 const __le32 *fw_data;
891 u32 fw_size;
892 int i, j;
893
894 /* halt the MEs */
895 sdma_v5_0_enable(adev, false0);
896
897 for (i = 0; i < adev->sdma.num_instances; i++) {
898 if (!adev->sdma.instance[i].fw)
899 return -EINVAL22;
900
901 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
902 amdgpu_ucode_print_sdma_hdr(&hdr->header);
903 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes)((__uint32_t)(hdr->header.ucode_size_bytes)) / 4;
904
905 fw_data = (const __le32 *)
906 (adev->sdma.instance[i].fw->data +
907 le32_to_cpu(hdr->header.ucode_array_offset_bytes)((__uint32_t)(hdr->header.ucode_array_offset_bytes)));
908
909 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0)amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x5880
)), (0), 0);
910
911 for (j = 0; j < fw_size; j++) {
912 if (amdgpu_emu_mode == 1 && j % 500 == 0)
913 drm_msleep(1)mdelay(1);
914 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++))amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x5881
)), (((__uint32_t)(*(__uint32_t *)(fw_data++)))), 0);
915 }
916
917 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version)amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x5880
)), (adev->sdma.instance[i].fw_version), 0);
918 }
919
920 return 0;
921}
922
923/**
924 * sdma_v5_0_start - setup and start the async dma engines
925 *
926 * @adev: amdgpu_device pointer
927 *
928 * Set up the DMA engines and enable them (NAVI10).
929 * Returns 0 for success, error for failure.
930 */
931static int sdma_v5_0_start(struct amdgpu_device *adev)
932{
933 int r = 0;
934
935 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
936 sdma_v5_0_ctx_switch_enable(adev, false0);
937 sdma_v5_0_enable(adev, false0);
938
939 /* set RB registers */
940 r = sdma_v5_0_gfx_resume(adev);
941 return r;
942 }
943
944 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
945 r = sdma_v5_0_load_microcode(adev);
946 if (r)
947 return r;
948 }
949
950 /* unhalt the MEs */
951 sdma_v5_0_enable(adev, true1);
952 /* enable sdma ring preemption */
953 sdma_v5_0_ctx_switch_enable(adev, true1);
954
955 /* start the gfx rings and rlc compute queues */
956 r = sdma_v5_0_gfx_resume(adev);
957 if (r)
958 return r;
959 r = sdma_v5_0_rlc_resume(adev);
960
961 return r;
962}
963
964static int sdma_v5_0_mqd_init(struct amdgpu_device *adev, void *mqd,
965 struct amdgpu_mqd_prop *prop)
966{
967 struct v10_sdma_mqd *m = mqd;
968 uint64_t wb_gpu_addr;
969
970 m->sdmax_rlcx_rb_cntl =
971 order_base_2(prop->queue_size / 4)drm_order(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT0x1 |
972 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT0xc |
973 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT0x10 |
974 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT0x17;
975
976 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8)((u32)(prop->hqd_base_gpu_addr >> 8));
977 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8)((u32)(((prop->hqd_base_gpu_addr >> 8) >> 16) >>
16));
978
979 m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset(adev, 0, 0x0087
)), 0)
980 mmSDMA0_GFX_RB_WPTR_POLL_CNTL))amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset(adev, 0, 0x0087
)), 0);
981
982 wb_gpu_addr = prop->wptr_gpu_addr;
983 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr)((u32)(wb_gpu_addr));
984 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr)((u32)(((wb_gpu_addr) >> 16) >> 16));
985
986 wb_gpu_addr = prop->rptr_gpu_addr;
987 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr)((u32)(wb_gpu_addr));
988 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr)((u32)(((wb_gpu_addr) >> 16) >> 16));
989
990 m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset(adev, 0, 0x008a
)), 0)
991 mmSDMA0_GFX_IB_CNTL))amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset(adev, 0, 0x008a
)), 0);
992
993 m->sdmax_rlcx_doorbell_offset =
994 prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT0x2;
995
996 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1)(((0) & ~0x10000000L) | (0x10000000L & ((1) << 0x1c
)));
997
998 return 0;
999}
1000
1001static void sdma_v5_0_set_mqd_funcs(struct amdgpu_device *adev)
1002{
1003 adev->mqds[AMDGPU_HW_IP_DMA2].mqd_size = sizeof(struct v10_sdma_mqd);
1004 adev->mqds[AMDGPU_HW_IP_DMA2].init_mqd = sdma_v5_0_mqd_init;
1005}
1006
1007/**
1008 * sdma_v5_0_ring_test_ring - simple async dma engine test
1009 *
1010 * @ring: amdgpu_ring structure holding ring information
1011 *
1012 * Test the DMA engine by writing using it to write an
1013 * value to memory. (NAVI10).
1014 * Returns 0 for success, error for failure.
1015 */
1016static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
1017{
1018 struct amdgpu_device *adev = ring->adev;
1019 unsigned i;
1020 unsigned index;
1021 int r;
1022 u32 tmp;
1023 u64 gpu_addr;
1024 volatile uint32_t *cpu_ptr = NULL((void *)0);
1025
1026 tmp = 0xCAFEDEAD;
1027
1028 if (ring->is_mes_queue) {
1029 uint32_t offset = 0;
1030 offset = amdgpu_mes_ctx_get_offs(ring,
1031 AMDGPU_MES_CTX_PADDING_OFFS);
1032 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset)(ring->is_mes_queue && ring->mes_ctx ? (ring->
mes_ctx->meta_data_gpu_addr + offset) : 0);
1033 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset)(ring->is_mes_queue && ring->mes_ctx ? (void *)
((uint8_t *)(ring->mes_ctx->meta_data_ptr) + offset) : (
(void *)0));
1034 *cpu_ptr = tmp;
1035 } else {
1036 r = amdgpu_device_wb_get(adev, &index);
1037 if (r) {
1038 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r)printf("drm:pid%d:%s *ERROR* " "(%d) failed to allocate wb slot\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
1039 return r;
1040 }
1041
1042 gpu_addr = adev->wb.gpu_addr + (index * 4);
1043 adev->wb.wb[index] = cpu_to_le32(tmp)((__uint32_t)(tmp));
1044 }
1045
1046 r = amdgpu_ring_alloc(ring, 20);
1047 if (r) {
1048 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r)__drm_err("amdgpu: dma failed to lock ring %d (%d).\n", ring->
idx, r);
1049 amdgpu_device_wb_free(adev, index);
1050 return r;
1051 }
1052
1053 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE)(((2) & 0x000000FF) << 0) |
1054 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)(((0) & 0x000000FF) << 8));
1055 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)((u32)(gpu_addr)));
1056 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16)));
1057 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)(((0) & 0x000FFFFF) << 0));
1058 amdgpu_ring_write(ring, 0xDEADBEEF);
1059 amdgpu_ring_commit(ring);
1060
1061 for (i = 0; i < adev->usec_timeout; i++) {
1062 if (ring->is_mes_queue)
1063 tmp = le32_to_cpu(*cpu_ptr)((__uint32_t)(*cpu_ptr));
1064 else
1065 tmp = le32_to_cpu(adev->wb.wb[index])((__uint32_t)(adev->wb.wb[index]));
1066 if (tmp == 0xDEADBEEF)
1067 break;
1068 if (amdgpu_emu_mode == 1)
1069 drm_msleep(1)mdelay(1);
1070 else
1071 udelay(1);
1072 }
1073
1074 if (i >= adev->usec_timeout)
1075 r = -ETIMEDOUT60;
1076
1077 if (!ring->is_mes_queue)
1078 amdgpu_device_wb_free(adev, index);
1079
1080 return r;
1081}
1082
1083/**
1084 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
1085 *
1086 * @ring: amdgpu_ring structure holding ring information
1087 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1088 *
1089 * Test a simple IB in the DMA ring (NAVI10).
1090 * Returns 0 on success, error on failure.
1091 */
1092static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1093{
1094 struct amdgpu_device *adev = ring->adev;
1095 struct amdgpu_ib ib;
1096 struct dma_fence *f = NULL((void *)0);
1097 unsigned index;
1
'index' declared without an initial value
→
1098 long r;
1099 u32 tmp = 0;
1100 u64 gpu_addr;
1101 volatile uint32_t *cpu_ptr = NULL((void *)0);
1102
1103 tmp = 0xCAFEDEAD;
1104 memset(&ib, 0, sizeof(ib))__builtin_memset((&ib), (0), (sizeof(ib)));
1105
1106 if (ring->is_mes_queue) {
2
←
Assuming field 'is_mes_queue' is true
→
3
←
Taking true branch
→
1107 uint32_t offset = 0;
1108 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
1109 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset)(ring->is_mes_queue && ring->mes_ctx ? (ring->
mes_ctx->meta_data_gpu_addr + offset) : 0);
4
←
Assuming field 'is_mes_queue' is true
→
5
←
Assuming field 'mes_ctx' is non-null
→
6
←
'?' condition is true
→
1110 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset)(ring->is_mes_queue && ring->mes_ctx ? (void *)
((uint8_t *)(ring->mes_ctx->meta_data_ptr) + offset) : (
(void *)0));
7
←
'?' condition is true
→
1111
1112 offset = amdgpu_mes_ctx_get_offs(ring,
1113 AMDGPU_MES_CTX_PADDING_OFFS);
1114 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset)(ring->is_mes_queue && ring->mes_ctx ? (ring->
mes_ctx->meta_data_gpu_addr + offset) : 0);
8
←
Assuming field 'is_mes_queue' is true
→
9
←
Assuming field 'mes_ctx' is non-null
→
10
←
'?' condition is true
→
1115 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset)(ring->is_mes_queue && ring->mes_ctx ? (void *)
((uint8_t *)(ring->mes_ctx->meta_data_ptr) + offset) : (
(void *)0));
11
←
'?' condition is true
→
1116 *cpu_ptr = tmp;
1117 } else {
1118 r = amdgpu_device_wb_get(adev, &index);
1119 if (r) {
1120 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r)printf("drm:pid%d:%s *ERROR* " "(%ld) failed to allocate wb slot\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
1121 return r;
1122 }
1123
1124 gpu_addr = adev->wb.gpu_addr + (index * 4);
1125 adev->wb.wb[index] = cpu_to_le32(tmp)((__uint32_t)(tmp));
1126
1127 r = amdgpu_ib_get(adev, NULL((void *)0), 256,
1128 AMDGPU_IB_POOL_DIRECT, &ib);
1129 if (r) {
1130 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r)__drm_err("amdgpu: failed to get ib (%ld).\n", r);
1131 goto err0;
1132 }
1133 }
1134
1135 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE)(((2) & 0x000000FF) << 0) |
1136 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)(((0) & 0x000000FF) << 8);
1137 ib.ptr[1] = lower_32_bits(gpu_addr)((u32)(gpu_addr));
1138 ib.ptr[2] = upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16));
1139 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)(((0) & 0x000FFFFF) << 0);
1140 ib.ptr[4] = 0xDEADBEEF;
1141 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0);
1142 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0);
1143 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0);
1144 ib.length_dw = 8;
1145
1146 r = amdgpu_ib_schedule(ring, 1, &ib, NULL((void *)0), &f);
1147 if (r)
12
←
Assuming 'r' is 0
→
13
←
Taking false branch
→
1148 goto err1;
1149
1150 r = dma_fence_wait_timeout(f, false0, timeout);
1151 if (r == 0) {
14
←
Assuming 'r' is not equal to 0
→
15
←
Taking false branch
→
1152 DRM_ERROR("amdgpu: IB test timed out\n")__drm_err("amdgpu: IB test timed out\n");
1153 r = -ETIMEDOUT60;
1154 goto err1;
1155 } else if (r < 0) {
16
←
Assuming 'r' is >= 0
→
17
←
Taking false branch
→
1156 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r)__drm_err("amdgpu: fence wait failed (%ld).\n", r);
1157 goto err1;
1158 }
1159
1160 if (ring->is_mes_queue)
18
←
Assuming field 'is_mes_queue' is false
→
19
←
Taking false branch
→
1161 tmp = le32_to_cpu(*cpu_ptr)((__uint32_t)(*cpu_ptr));
1162 else
1163 tmp = le32_to_cpu(adev->wb.wb[index])((__uint32_t)(adev->wb.wb[index]));
20
←
Array subscript is undefined
1164
1165 if (tmp == 0xDEADBEEF)
1166 r = 0;
1167 else
1168 r = -EINVAL22;
1169
1170err1:
1171 amdgpu_ib_free(adev, &ib, NULL((void *)0));
1172 dma_fence_put(f);
1173err0:
1174 if (!ring->is_mes_queue)
1175 amdgpu_device_wb_free(adev, index);
1176 return r;
1177}
1178
1179
1180/**
1181 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
1182 *
1183 * @ib: indirect buffer to fill with commands
1184 * @pe: addr of the page entry
1185 * @src: src addr to copy from
1186 * @count: number of page entries to update
1187 *
1188 * Update PTEs by copying them from the GART using sDMA (NAVI10).
1189 */
1190static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
1191 uint64_t pe, uint64_t src,
1192 unsigned count)
1193{
1194 unsigned bytes = count * 8;
1195
1196 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY)(((1) & 0x000000FF) << 0) |
1197 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR)(((0) & 0x000000FF) << 8);
1198 ib->ptr[ib->length_dw++] = bytes - 1;
1199 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1200 ib->ptr[ib->length_dw++] = lower_32_bits(src)((u32)(src));
1201 ib->ptr[ib->length_dw++] = upper_32_bits(src)((u32)(((src) >> 16) >> 16));
1202 ib->ptr[ib->length_dw++] = lower_32_bits(pe)((u32)(pe));
1203 ib->ptr[ib->length_dw++] = upper_32_bits(pe)((u32)(((pe) >> 16) >> 16));
1204
1205}
1206
1207/**
1208 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1209 *
1210 * @ib: indirect buffer to fill with commands
1211 * @pe: addr of the page entry
1212 * @value: dst addr to write into pe
1213 * @count: number of page entries to update
1214 * @incr: increase next addr by incr bytes
1215 *
1216 * Update PTEs by writing them manually using sDMA (NAVI10).
1217 */
1218static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1219 uint64_t value, unsigned count,
1220 uint32_t incr)
1221{
1222 unsigned ndw = count * 2;
1223
1224 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE)(((2) & 0x000000FF) << 0) |
1225 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)(((0) & 0x000000FF) << 8);
1226 ib->ptr[ib->length_dw++] = lower_32_bits(pe)((u32)(pe));
1227 ib->ptr[ib->length_dw++] = upper_32_bits(pe)((u32)(((pe) >> 16) >> 16));
1228 ib->ptr[ib->length_dw++] = ndw - 1;
1229 for (; ndw > 0; ndw -= 2) {
1230 ib->ptr[ib->length_dw++] = lower_32_bits(value)((u32)(value));
1231 ib->ptr[ib->length_dw++] = upper_32_bits(value)((u32)(((value) >> 16) >> 16));
1232 value += incr;
1233 }
1234}
1235
1236/**
1237 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1238 *
1239 * @ib: indirect buffer to fill with commands
1240 * @pe: addr of the page entry
1241 * @addr: dst addr to write into pe
1242 * @count: number of page entries to update
1243 * @incr: increase next addr by incr bytes
1244 * @flags: access flags
1245 *
1246 * Update the page tables using sDMA (NAVI10).
1247 */
1248static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1249 uint64_t pe,
1250 uint64_t addr, unsigned count,
1251 uint32_t incr, uint64_t flags)
1252{
1253 /* for physically contiguous pages (vram) */
1254 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE)(((12) & 0x000000FF) << 0);
1255 ib->ptr[ib->length_dw++] = lower_32_bits(pe)((u32)(pe)); /* dst addr */
1256 ib->ptr[ib->length_dw++] = upper_32_bits(pe)((u32)(((pe) >> 16) >> 16));
1257 ib->ptr[ib->length_dw++] = lower_32_bits(flags)((u32)(flags)); /* mask */
1258 ib->ptr[ib->length_dw++] = upper_32_bits(flags)((u32)(((flags) >> 16) >> 16));
1259 ib->ptr[ib->length_dw++] = lower_32_bits(addr)((u32)(addr)); /* value */
1260 ib->ptr[ib->length_dw++] = upper_32_bits(addr)((u32)(((addr) >> 16) >> 16));
1261 ib->ptr[ib->length_dw++] = incr; /* increment size */
1262 ib->ptr[ib->length_dw++] = 0;
1263 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1264}
1265
1266/**
1267 * sdma_v5_0_ring_pad_ib - pad the IB
1268 * @ring: amdgpu_ring structure holding ring information
1269 * @ib: indirect buffer to fill with padding
1270 *
1271 * Pad the IB with NOPs to a boundary multiple of 8.
1272 */
1273static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1274{
1275 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1276 u32 pad_count;
1277 int i;
1278
1279 pad_count = (-ib->length_dw) & 0x7;
1280 for (i = 0; i < pad_count; i++)
1281 if (sdma && sdma->burst_nop && (i == 0))
1282 ib->ptr[ib->length_dw++] =
1283 SDMA_PKT_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0) |
1284 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1)(((pad_count - 1) & 0x00003FFF) << 16);
1285 else
1286 ib->ptr[ib->length_dw++] =
1287 SDMA_PKT_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0);
1288}
1289
1290
1291/**
1292 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1293 *
1294 * @ring: amdgpu_ring pointer
1295 *
1296 * Make sure all previous operations are completed (CIK).
1297 */
1298static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1299{
1300 uint32_t seq = ring->fence_drv.sync_seq;
1301 uint64_t addr = ring->fence_drv.gpu_addr;
1302
1303 /* wait for idle */
1304 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM)(((8) & 0x000000FF) << 0) |
1305 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0)(((0) & 0x00000001) << 26) |
1306 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)(((3) & 0x00000007) << 28) | /* equal */
1307 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)(((1) & 0x00000001) << 31));
1308 amdgpu_ring_write(ring, addr & 0xfffffffc);
1309 amdgpu_ring_write(ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)) & 0xffffffff);
1310 amdgpu_ring_write(ring, seq); /* reference */
1311 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1312 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff)(((0xfff) & 0x00000FFF) << 16) |
1313 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)(((4) & 0x0000FFFF) << 0)); /* retry count, poll interval */
1314}
1315
1316
1317/**
1318 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1319 *
1320 * @ring: amdgpu_ring pointer
1321 * @vmid: vmid number to use
1322 * @pd_addr: address
1323 *
1324 * Update the page table base and flush the VM TLB
1325 * using sDMA (NAVI10).
1326 */
1327static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1328 unsigned vmid, uint64_t pd_addr)
1329{
1330 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr)(ring)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((ring
), (vmid), (pd_addr));
1331}
1332
1333static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1334 uint32_t reg, uint32_t val)
1335{
1336 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE)(((14) & 0x000000FF) << 0) |
1337 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)(((0xf) & 0x0000000F) << 28));
1338 amdgpu_ring_write(ring, reg);
1339 amdgpu_ring_write(ring, val);
1340}
1341
1342static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1343 uint32_t val, uint32_t mask)
1344{
1345 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM)(((8) & 0x000000FF) << 0) |
1346 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0)(((0) & 0x00000001) << 26) |
1347 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)(((3) & 0x00000007) << 28)); /* equal */
1348 amdgpu_ring_write(ring, reg << 2);
1349 amdgpu_ring_write(ring, 0);
1350 amdgpu_ring_write(ring, val); /* reference */
1351 amdgpu_ring_write(ring, mask); /* mask */
1352 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff)(((0xfff) & 0x00000FFF) << 16) |
1353 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)(((10) & 0x0000FFFF) << 0));
1354}
1355
1356static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1357 uint32_t reg0, uint32_t reg1,
1358 uint32_t ref, uint32_t mask)
1359{
1360 amdgpu_ring_emit_wreg(ring, reg0, ref)(ring)->funcs->emit_wreg((ring), (reg0), (ref));
1361 /* wait for a cycle to reset vm_inv_eng*_ack */
1362 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0)(ring)->funcs->emit_reg_wait((ring), (reg0), (0), (0));
1363 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask)(ring)->funcs->emit_reg_wait((ring), (reg1), (mask), (mask
));
1364}
1365
1366static int sdma_v5_0_early_init(void *handle)
1367{
1368 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1369
1370 sdma_v5_0_set_ring_funcs(adev);
1371 sdma_v5_0_set_buffer_funcs(adev);
1372 sdma_v5_0_set_vm_pte_funcs(adev);
1373 sdma_v5_0_set_irq_funcs(adev);
1374 sdma_v5_0_set_mqd_funcs(adev);
1375
1376 return 0;
1377}
1378
1379
1380static int sdma_v5_0_sw_init(void *handle)
1381{
1382 struct amdgpu_ring *ring;
1383 int r, i;
1384 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1385
1386 /* SDMA trap event */
1387 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
1388 SDMA0_5_0__SRCID__SDMA_TRAP224,
1389 &adev->sdma.trap_irq);
1390 if (r)
1391 return r;
1392
1393 /* SDMA trap event */
1394 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
1395 SDMA1_5_0__SRCID__SDMA_TRAP224,
1396 &adev->sdma.trap_irq);
1397 if (r)
1398 return r;
1399
1400 r = sdma_v5_0_init_microcode(adev);
1401 if (r) {
1402 DRM_ERROR("Failed to load sdma firmware!\n")__drm_err("Failed to load sdma firmware!\n");
1403 return r;
1404 }
1405
1406 for (i = 0; i < adev->sdma.num_instances; i++) {
1407 ring = &adev->sdma.instance[i].ring;
1408 ring->ring_obj = NULL((void *)0);
1409 ring->use_doorbell = true1;
1410
1411 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,___drm_dbg(((void *)0), DRM_UT_CORE, "SDMA %d use_doorbell being set to: [%s]\n"
, i, ring->use_doorbell?"true":"false")
1412 ring->use_doorbell?"true":"false")___drm_dbg(((void *)0), DRM_UT_CORE, "SDMA %d use_doorbell being set to: [%s]\n"
, i, ring->use_doorbell?"true":"false");
1413
1414 ring->doorbell_index = (i == 0) ?
1415 (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1416 : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1417
1418 snprintf(ring->name, sizeof(ring->name), "sdma%d", i);
1419 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1420 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
1421 AMDGPU_SDMA_IRQ_INSTANCE1,
1422 AMDGPU_RING_PRIO_DEFAULT, NULL((void *)0));
1423 if (r)
1424 return r;
1425 }
1426
1427 return r;
1428}
1429
1430static int sdma_v5_0_sw_fini(void *handle)
1431{
1432 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1433 int i;
1434
1435 for (i = 0; i < adev->sdma.num_instances; i++)
1436 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1437
1438 amdgpu_sdma_destroy_inst_ctx(adev, false0);
1439
1440 return 0;
1441}
1442
1443static int sdma_v5_0_hw_init(void *handle)
1444{
1445 int r;
1446 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1447
1448 sdma_v5_0_init_golden_registers(adev);
1449
1450 r = sdma_v5_0_start(adev);
1451
1452 return r;
1453}
1454
1455static int sdma_v5_0_hw_fini(void *handle)
1456{
1457 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1458
1459 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
1460 /* disable the scheduler for SDMA */
1461 amdgpu_sdma_unset_buffer_funcs_helper(adev);
1462 return 0;
1463 }
1464
1465 sdma_v5_0_ctx_switch_enable(adev, false0);
1466 sdma_v5_0_enable(adev, false0);
1467
1468 return 0;
1469}
1470
1471static int sdma_v5_0_suspend(void *handle)
1472{
1473 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1474
1475 return sdma_v5_0_hw_fini(adev);
1476}
1477
1478static int sdma_v5_0_resume(void *handle)
1479{
1480 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1481
1482 return sdma_v5_0_hw_init(adev);
1483}
1484
1485static bool_Bool sdma_v5_0_is_idle(void *handle)
1486{
1487 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1488 u32 i;
1489
1490 for (i = 0; i < adev->sdma.num_instances; i++) {
1491 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG))amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x0025
)), 0);
1492
1493 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK0x00000001L))
1494 return false0;
1495 }
1496
1497 return true1;
1498}
1499
1500static int sdma_v5_0_wait_for_idle(void *handle)
1501{
1502 unsigned i;
1503 u32 sdma0, sdma1;
1504 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1505
1506 for (i = 0; i < adev->usec_timeout; i++) {
1507 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG))amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset(adev, 0, 0x0025
)), 0);
1508 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG))amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset(adev, 1, 0x0025
)), 0);
1509
1510 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK0x00000001L)
1511 return 0;
1512 udelay(1);
1513 }
1514 return -ETIMEDOUT60;
1515}
1516
1517static int sdma_v5_0_soft_reset(void *handle)
1518{
1519 /* todo */
1520
1521 return 0;
1522}
1523
1524static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1525{
1526 int i, r = 0;
1527 struct amdgpu_device *adev = ring->adev;
1528 u32 index = 0;
1529 u64 sdma_gfx_preempt;
1530
1531 amdgpu_sdma_get_index_from_ring(ring, &index);
1532 if (index == 0)
1533 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT0x00b0;
1534 else
1535 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT0x06b0;
1536
1537 /* assert preemption condition */
1538 amdgpu_ring_set_preempt_cond_exec(ring, false0);
1539
1540 /* emit the trailing fence */
1541 ring->trail_seq += 1;
1542 amdgpu_ring_alloc(ring, 10);
1543 sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1544 ring->trail_seq, 0);
1545 amdgpu_ring_commit(ring);
1546
1547 /* assert IB preemption */
1548 WREG32(sdma_gfx_preempt, 1)amdgpu_device_wreg(adev, (sdma_gfx_preempt), (1), 0);
1549
1550 /* poll the trailing fence */
1551 for (i = 0; i < adev->usec_timeout; i++) {
1552 if (ring->trail_seq ==
1553 le32_to_cpu(*(ring->trail_fence_cpu_addr))((__uint32_t)(*(ring->trail_fence_cpu_addr))))
1554 break;
1555 udelay(1);
1556 }
1557
1558 if (i >= adev->usec_timeout) {
1559 r = -EINVAL22;
1560 DRM_ERROR("ring %d failed to be preempted\n", ring->idx)__drm_err("ring %d failed to be preempted\n", ring->idx);
1561 }
1562
1563 /* deassert IB preemption */
1564 WREG32(sdma_gfx_preempt, 0)amdgpu_device_wreg(adev, (sdma_gfx_preempt), (0), 0);
1565
1566 /* deassert the preemption condition */
1567 amdgpu_ring_set_preempt_cond_exec(ring, true1);
1568 return r;
1569}
1570
1571static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1572 struct amdgpu_irq_src *source,
1573 unsigned type,
1574 enum amdgpu_interrupt_state state)
1575{
1576 u32 sdma_cntl;
1577
1578 if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
1579 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1580 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL0x001c) :
1581 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL0x001c);
1582
1583 sdma_cntl = RREG32(reg_offset)amdgpu_device_rreg(adev, (reg_offset), 0);
1584 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,(((sdma_cntl) & ~0x00000001L) | (0x00000001L & ((state
== AMDGPU_IRQ_STATE_ENABLE ? 1 : 0) << 0x0)))
1585 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0)(((sdma_cntl) & ~0x00000001L) | (0x00000001L & ((state
== AMDGPU_IRQ_STATE_ENABLE ? 1 : 0) << 0x0)));
1586 WREG32(reg_offset, sdma_cntl)amdgpu_device_wreg(adev, (reg_offset), (sdma_cntl), 0);
1587 }
1588
1589 return 0;
1590}
1591
1592static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1593 struct amdgpu_irq_src *source,
1594 struct amdgpu_iv_entry *entry)
1595{
1596 uint32_t mes_queue_id = entry->src_data[0];
1597
1598 DRM_DEBUG("IH: SDMA trap\n")___drm_dbg(((void *)0), DRM_UT_CORE, "IH: SDMA trap\n");
1599
1600 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG0x1000000u)) {
1601 struct amdgpu_mes_queue *queue;
1602
1603 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK(0x1000000u - 1);
1604
1605 spin_lock(&adev->mes.queue_id_lock)mtx_enter(&adev->mes.queue_id_lock);
1606 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1607 if (queue) {
1608 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id)___drm_dbg(((void *)0), DRM_UT_CORE, "process smda queue id = %d\n"
, mes_queue_id);
1609 amdgpu_fence_process(queue->ring);
1610 }
1611 spin_unlock(&adev->mes.queue_id_lock)mtx_leave(&adev->mes.queue_id_lock);
1612 return 0;
1613 }
1614
1615 switch (entry->client_id) {
1616 case SOC15_IH_CLIENTID_SDMA0:
1617 switch (entry->ring_id) {
1618 case 0:
1619 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1620 break;
1621 case 1:
1622 /* XXX compute */
1623 break;
1624 case 2:
1625 /* XXX compute */
1626 break;
1627 case 3:
1628 /* XXX page queue*/
1629 break;
1630 }
1631 break;
1632 case SOC15_IH_CLIENTID_SDMA1:
1633 switch (entry->ring_id) {
1634 case 0:
1635 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1636 break;
1637 case 1:
1638 /* XXX compute */
1639 break;
1640 case 2:
1641 /* XXX compute */
1642 break;
1643 case 3:
1644 /* XXX page queue*/
1645 break;
1646 }
1647 break;
1648 }
1649 return 0;
1650}
1651
1652static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1653 struct amdgpu_irq_src *source,
1654 struct amdgpu_iv_entry *entry)
1655{
1656 return 0;
1657}
1658
1659static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1660 bool_Bool enable)
1661{
1662 uint32_t data, def;
1663 int i;
1664
1665 for (i = 0; i < adev->sdma.num_instances; i++) {
1666 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG(1ULL << 11))) {
1667 /* Enable sdma clock gating */
1668 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL))amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x001b
)), 0);
1669 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK0x01000000L |
1670 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK0x02000000L |
1671 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK0x04000000L |
1672 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK0x08000000L |
1673 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK0x10000000L |
1674 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK0x20000000L |
1675 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK0x40000000L |
1676 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK0x80000000L);
1677 if (def != data)
1678 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data)amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x001b
)), (data), 0);
1679 } else {
1680 /* Disable sdma clock gating */
1681 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL))amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x001b
)), 0);
1682 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK0x01000000L |
1683 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK0x02000000L |
1684 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK0x04000000L |
1685 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK0x08000000L |
1686 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK0x10000000L |
1687 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK0x20000000L |
1688 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK0x40000000L |
1689 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK0x80000000L);
1690 if (def != data)
1691 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data)amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x001b
)), (data), 0);
1692 }
1693 }
1694}
1695
1696static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1697 bool_Bool enable)
1698{
1699 uint32_t data, def;
1700 int i;
1701
1702 for (i = 0; i < adev->sdma.num_instances; i++) {
1703 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS(1ULL << 10))) {
1704 /* Enable sdma mem light sleep */
1705 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL))amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x001a
)), 0);
1706 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK0x00000100L;
1707 if (def != data)
1708 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data)amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x001a
)), (data), 0);
1709
1710 } else {
1711 /* Disable sdma mem light sleep */
1712 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL))amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x001a
)), 0);
1713 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK0x00000100L;
1714 if (def != data)
1715 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data)amdgpu_device_wreg(adev, (sdma_v5_0_get_reg_offset(adev, i, 0x001a
)), (data), 0);
1716
1717 }
1718 }
1719}
1720
1721static int sdma_v5_0_set_clockgating_state(void *handle,
1722 enum amd_clockgating_state state)
1723{
1724 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1725
1726 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
1727 return 0;
1728
1729 switch (adev->ip_versions[SDMA0_HWIP][0]) {
1730 case IP_VERSION(5, 0, 0)(((5) << 16) | ((0) << 8) | (0)):
1731 case IP_VERSION(5, 0, 2)(((5) << 16) | ((0) << 8) | (2)):
1732 case IP_VERSION(5, 0, 5)(((5) << 16) | ((0) << 8) | (5)):
1733 sdma_v5_0_update_medium_grain_clock_gating(adev,
1734 state == AMD_CG_STATE_GATE);
1735 sdma_v5_0_update_medium_grain_light_sleep(adev,
1736 state == AMD_CG_STATE_GATE);
1737 break;
1738 default:
1739 break;
1740 }
1741
1742 return 0;
1743}
1744
1745static int sdma_v5_0_set_powergating_state(void *handle,
1746 enum amd_powergating_state state)
1747{
1748 return 0;
1749}
1750
1751static void sdma_v5_0_get_clockgating_state(void *handle, u64 *flags)
1752{
1753 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1754 int data;
1755
1756 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
1757 *flags = 0;
1758
1759 /* AMD_CG_SUPPORT_SDMA_MGCG */
1760 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL))amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset(adev, 0, 0x001b
)), 0);
1761 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK0x01000000L))
1762 *flags |= AMD_CG_SUPPORT_SDMA_MGCG(1ULL << 11);
1763
1764 /* AMD_CG_SUPPORT_SDMA_LS */
1765 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL))amdgpu_device_rreg(adev, (sdma_v5_0_get_reg_offset(adev, 0, 0x001a
)), 0);
1766 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK0x00000100L)
1767 *flags |= AMD_CG_SUPPORT_SDMA_LS(1ULL << 10);
1768}
1769
1770const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1771 .name = "sdma_v5_0",
1772 .early_init = sdma_v5_0_early_init,
1773 .late_init = NULL((void *)0),
1774 .sw_init = sdma_v5_0_sw_init,
1775 .sw_fini = sdma_v5_0_sw_fini,
1776 .hw_init = sdma_v5_0_hw_init,
1777 .hw_fini = sdma_v5_0_hw_fini,
1778 .suspend = sdma_v5_0_suspend,
1779 .resume = sdma_v5_0_resume,
1780 .is_idle = sdma_v5_0_is_idle,
1781 .wait_for_idle = sdma_v5_0_wait_for_idle,
1782 .soft_reset = sdma_v5_0_soft_reset,
1783 .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1784 .set_powergating_state = sdma_v5_0_set_powergating_state,
1785 .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1786};
1787
1788static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1789 .type = AMDGPU_RING_TYPE_SDMA,
1790 .align_mask = 0xf,
1791 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0),
1792 .support_64bit_ptrs = true1,
1793 .secure_submission_supported = true1,
1794 .vmhub = AMDGPU_GFXHUB_00,
1795 .get_rptr = sdma_v5_0_ring_get_rptr,
1796 .get_wptr = sdma_v5_0_ring_get_wptr,
1797 .set_wptr = sdma_v5_0_ring_set_wptr,
1798 .emit_frame_size =
1799 5 + /* sdma_v5_0_ring_init_cond_exec */
1800 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1801 3 + /* hdp_invalidate */
1802 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1803 /* sdma_v5_0_ring_emit_vm_flush */
1804 SOC15_FLUSH_GPU_TLB_NUM_WREG6 * 3 +
1805 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT3 * 6 * 2 +
1806 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1807 .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1808 .emit_ib = sdma_v5_0_ring_emit_ib,
1809 .emit_mem_sync = sdma_v5_0_ring_emit_mem_sync,
1810 .emit_fence = sdma_v5_0_ring_emit_fence,
1811 .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1812 .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1813 .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1814 .test_ring = sdma_v5_0_ring_test_ring,
1815 .test_ib = sdma_v5_0_ring_test_ib,
1816 .insert_nop = sdma_v5_0_ring_insert_nop,
1817 .pad_ib = sdma_v5_0_ring_pad_ib,
1818 .emit_wreg = sdma_v5_0_ring_emit_wreg,
1819 .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1820 .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
1821 .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1822 .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
1823 .preempt_ib = sdma_v5_0_ring_preempt_ib,
1824};
1825
1826static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1827{
1828 int i;
1829
1830 for (i = 0; i < adev->sdma.num_instances; i++) {
1831 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1832 adev->sdma.instance[i].ring.me = i;
1833 }
1834}
1835
1836static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1837 .set = sdma_v5_0_set_trap_irq_state,
1838 .process = sdma_v5_0_process_trap_irq,
1839};
1840
1841static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1842 .process = sdma_v5_0_process_illegal_inst_irq,
1843};
1844
1845static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1846{
1847 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1848 adev->sdma.num_instances;
1849 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
1850 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
1851}
1852
1853/**
1854 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1855 *
1856 * @ib: indirect buffer to copy to
1857 * @src_offset: src GPU address
1858 * @dst_offset: dst GPU address
1859 * @byte_count: number of bytes to xfer
1860 * @tmz: if a secure copy should be used
1861 *
1862 * Copy GPU buffers using the DMA engine (NAVI10).
1863 * Used by the amdgpu ttm implementation to move pages if
1864 * registered as the asic copy callback.
1865 */
1866static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
1867 uint64_t src_offset,
1868 uint64_t dst_offset,
1869 uint32_t byte_count,
1870 bool_Bool tmz)
1871{
1872 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY)(((1) & 0x000000FF) << 0) |
1873 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR)(((0) & 0x000000FF) << 8) |
1874 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0)(((tmz ? 1 : 0) & 0x00000001) << 18);
1875 ib->ptr[ib->length_dw++] = byte_count - 1;
1876 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1877 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset)((u32)(src_offset));
1878 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset)((u32)(((src_offset) >> 16) >> 16));
1879 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset)((u32)(dst_offset));
1880 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset)((u32)(((dst_offset) >> 16) >> 16));
1881}
1882
1883/**
1884 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1885 *
1886 * @ib: indirect buffer to fill
1887 * @src_data: value to write to buffer
1888 * @dst_offset: dst GPU address
1889 * @byte_count: number of bytes to xfer
1890 *
1891 * Fill GPU buffers using the DMA engine (NAVI10).
1892 */
1893static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
1894 uint32_t src_data,
1895 uint64_t dst_offset,
1896 uint32_t byte_count)
1897{
1898 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL)(((11) & 0x000000FF) << 0);
1899 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset)((u32)(dst_offset));
1900 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset)((u32)(((dst_offset) >> 16) >> 16));
1901 ib->ptr[ib->length_dw++] = src_data;
1902 ib->ptr[ib->length_dw++] = byte_count - 1;
1903}
1904
1905static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
1906 .copy_max_bytes = 0x400000,
1907 .copy_num_dw = 7,
1908 .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
1909
1910 .fill_max_bytes = 0x400000,
1911 .fill_num_dw = 5,
1912 .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
1913};
1914
1915static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
1916{
1917 if (adev->mman.buffer_funcs == NULL((void *)0)) {
1918 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
1919 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1920 }
1921}
1922
1923static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
1924 .copy_pte_num_dw = 7,
1925 .copy_pte = sdma_v5_0_vm_copy_pte,
1926 .write_pte = sdma_v5_0_vm_write_pte,
1927 .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
1928};
1929
1930static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1931{
1932 unsigned i;
1933
1934 if (adev->vm_manager.vm_pte_funcs == NULL((void *)0)) {
1935 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1936 for (i = 0; i < adev->sdma.num_instances; i++) {
1937 adev->vm_manager.vm_pte_scheds[i] =
1938 &adev->sdma.instance[i].ring.sched;
1939 }
1940 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1941 }
1942}
1943
1944const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
1945 .type = AMD_IP_BLOCK_TYPE_SDMA,
1946 .major = 5,
1947 .minor = 0,
1948 .rev = 0,
1949 .funcs = &sdma_v5_0_ip_funcs,
1950};