/usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86/X86TargetTransformInfo.cpp

Bug Summary

File:	src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
Warning:	line 3362, column 15 Division by zero

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/usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/IPO -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include -I /usr/src/gnu/usr.bin/clang/libLLVM/../include -I /usr/src/gnu/usr.bin/clang/libLLVM/obj -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include -D NDEBUG -D __STDC_LIMIT_MACROS -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D LLVM_PREFIX="/usr" -D PIC -internal-isystem /usr/include/c++/v1 -internal-isystem /usr/local/lib/clang/13.0.0/include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/usr/src/gnu/usr.bin/clang/libLLVM/obj -ferror-limit 19 -fvisibility-inlines-hidden -fwrapv -D_RET_PROTECTOR -ret-protector -fno-rtti -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /home/ben/Projects/vmm/scan-build/2022-01-12-194120-40624-1 -x c++ /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86/X86TargetTransformInfo.cpp

/usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86/X86TargetTransformInfo.cpp

→

1//===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file implements a TargetTransformInfo analysis pass specific to the
10/// X86 target machine. It uses the target's detailed information to provide
11/// more precise answers to certain TTI queries, while letting the target
12/// independent and default TTI implementations handle the rest.
13///
14//===----------------------------------------------------------------------===//
15/// About Cost Model numbers used below it's necessary to say the following:
16/// the numbers correspond to some "generic" X86 CPU instead of usage of
17/// concrete CPU model. Usually the numbers correspond to CPU where the feature
18/// apeared at the first time. For example, if we do Subtarget.hasSSE42() in
19/// the lookups below the cost is based on Nehalem as that was the first CPU
20/// to support that feature level and thus has most likely the worst case cost.
21/// Some examples of other technologies/CPUs:
22///   SSE 3   - Pentium4 / Athlon64
23///   SSE 4.1 - Penryn
24///   SSE 4.2 - Nehalem
25///   AVX     - Sandy Bridge
26///   AVX2    - Haswell
27///   AVX-512 - Xeon Phi / Skylake
28/// And some examples of instruction target dependent costs (latency)
29///                   divss     sqrtss          rsqrtss
30///   AMD K7            11-16     19              3
31///   Piledriver        9-24      13-15           5
32///   Jaguar            14        16              2
33///   Pentium II,III    18        30              2
34///   Nehalem           7-14      7-18            3
35///   Haswell           10-13     11              5
36/// TODO: Develop and implement  the target dependent cost model and
37/// specialize cost numbers for different Cost Model Targets such as throughput,
38/// code size, latency and uop count.
39//===----------------------------------------------------------------------===//

41#include "X86TargetTransformInfo.h"
42#include "llvm/Analysis/TargetTransformInfo.h"
43#include "llvm/CodeGen/BasicTTIImpl.h"
44#include "llvm/CodeGen/CostTable.h"
45#include "llvm/CodeGen/TargetLowering.h"
46#include "llvm/IR/IntrinsicInst.h"
47#include "llvm/Support/Debug.h"

49using namespace llvm;

51#define DEBUG_TYPE"x86tti" "x86tti"

53//===----------------------------------------------------------------------===//
54//
55// X86 cost model.
56//
57//===----------------------------------------------------------------------===//

59TargetTransformInfo::PopcntSupportKind
60X86TTIImpl::getPopcntSupport(unsigned TyWidth) {
assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2")((void)0);
// TODO: Currently the __builtin_popcount() implementation using SSE3
//   instructions is inefficient. Once the problem is fixed, we should
//   call ST->hasSSE3() instead of ST->hasPOPCNT().
return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software;
66}

68llvm::Optional<unsigned> X86TTIImpl::getCacheSize(
TargetTransformInfo::CacheLevel Level) const {
switch (Level) {
case TargetTransformInfo::CacheLevel::L1D:
  //   - Penryn
  //   - Nehalem
  //   - Westmere
  //   - Sandy Bridge
  //   - Ivy Bridge
  //   - Haswell
  //   - Broadwell
  //   - Skylake
  //   - Kabylake
  return 32 * 1024;  //  32 KByte
case TargetTransformInfo::CacheLevel::L2D:
  //   - Penryn
  //   - Nehalem
  //   - Westmere
  //   - Sandy Bridge
  //   - Ivy Bridge
  //   - Haswell
  //   - Broadwell
  //   - Skylake
  //   - Kabylake
  return 256 * 1024; // 256 KByte
}

llvm_unreachable("Unknown TargetTransformInfo::CacheLevel")__builtin_unreachable();
96}

98llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity(
TargetTransformInfo::CacheLevel Level) const {
//   - Penryn
//   - Nehalem
//   - Westmere
//   - Sandy Bridge
//   - Ivy Bridge
//   - Haswell
//   - Broadwell
//   - Skylake
//   - Kabylake
switch (Level) {
case TargetTransformInfo::CacheLevel::L1D:
  LLVM_FALLTHROUGH[[gnu::fallthrough]];
case TargetTransformInfo::CacheLevel::L2D:
  return 8;
}

llvm_unreachable("Unknown TargetTransformInfo::CacheLevel")__builtin_unreachable();
117}

119unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const {
bool Vector = (ClassID == 1);
if (Vector && !ST->hasSSE1())
  return 0;

if (ST->is64Bit()) {
  if (Vector && ST->hasAVX512())
    return 32;
  return 16;
}
return 8;
130}

132TypeSize
133X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
unsigned PreferVectorWidth = ST->getPreferVectorWidth();
switch (K) {
case TargetTransformInfo::RGK_Scalar:
  return TypeSize::getFixed(ST->is64Bit() ? 64 : 32);
case TargetTransformInfo::RGK_FixedWidthVector:
  if (ST->hasAVX512() && PreferVectorWidth >= 512)
    return TypeSize::getFixed(512);
  if (ST->hasAVX() && PreferVectorWidth >= 256)
    return TypeSize::getFixed(256);
  if (ST->hasSSE1() && PreferVectorWidth >= 128)
    return TypeSize::getFixed(128);
  return TypeSize::getFixed(0);
case TargetTransformInfo::RGK_ScalableVector:
  return TypeSize::getScalable(0);
}

llvm_unreachable("Unsupported register kind")__builtin_unreachable();
151}

153unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const {
return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector)
    .getFixedSize();
156}

158unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) {
// If the loop will not be vectorized, don't interleave the loop.
// Let regular unroll to unroll the loop, which saves the overflow
// check and memory check cost.
if (VF == 1)
  return 1;

if (ST->isAtom())
  return 1;

// Sandybridge and Haswell have multiple execution ports and pipelined
// vector units.
if (ST->hasAVX())
  return 4;

return 2;
174}

176InstructionCost X86TTIImpl::getArithmeticInstrCost(
  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
  TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info,
  TTI::OperandValueProperties Opd1PropInfo,
  TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args,
  const Instruction *CxtI) {
// TODO: Handle more cost kinds.
if (CostKind != TTI::TCK_RecipThroughput)
  return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
                                       Op2Info, Opd1PropInfo,
                                       Opd2PropInfo, Args, CxtI);

// vXi8 multiplications are always promoted to vXi16.
if (Opcode == Instruction::Mul && Ty->isVectorTy() &&
    Ty->getScalarSizeInBits() == 8) {
  Type *WideVecTy =
      VectorType::getExtendedElementVectorType(cast<VectorType>(Ty));
  return getCastInstrCost(Instruction::ZExt, WideVecTy, Ty,
                          TargetTransformInfo::CastContextHint::None,
                          CostKind) +
         getCastInstrCost(Instruction::Trunc, Ty, WideVecTy,
                          TargetTransformInfo::CastContextHint::None,
                          CostKind) +
         getArithmeticInstrCost(Opcode, WideVecTy, CostKind, Op1Info, Op2Info,
                                Opd1PropInfo, Opd2PropInfo);
}

// Legalize the type.
std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);

int ISD = TLI->InstructionOpcodeToISD(Opcode);
assert(ISD && "Invalid opcode")((void)0);

static const CostTblEntry GLMCostTable[] = {
  { ISD::FDIV,  MVT::f32,   18 }, // divss
  { ISD::FDIV,  MVT::v4f32, 35 }, // divps
  { ISD::FDIV,  MVT::f64,   33 }, // divsd
  { ISD::FDIV,  MVT::v2f64, 65 }, // divpd
};

if (ST->useGLMDivSqrtCosts())
  if (const auto *Entry = CostTableLookup(GLMCostTable, ISD,
                                          LT.second))
    return LT.first * Entry->Cost;

static const CostTblEntry SLMCostTable[] = {
  { ISD::MUL,   MVT::v4i32, 11 }, // pmulld
  { ISD::MUL,   MVT::v8i16, 2  }, // pmullw
  { ISD::FMUL,  MVT::f64,   2  }, // mulsd
  { ISD::FMUL,  MVT::v2f64, 4  }, // mulpd
  { ISD::FMUL,  MVT::v4f32, 2  }, // mulps
  { ISD::FDIV,  MVT::f32,   17 }, // divss
  { ISD::FDIV,  MVT::v4f32, 39 }, // divps
  { ISD::FDIV,  MVT::f64,   32 }, // divsd
  { ISD::FDIV,  MVT::v2f64, 69 }, // divpd
  { ISD::FADD,  MVT::v2f64, 2  }, // addpd
  { ISD::FSUB,  MVT::v2f64, 2  }, // subpd
  // v2i64/v4i64 mul is custom lowered as a series of long:
  // multiplies(3), shifts(3) and adds(2)
  // slm muldq version throughput is 2 and addq throughput 4
  // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) +
  //       3X4 (addq throughput) = 17
  { ISD::MUL,   MVT::v2i64, 17 },
  // slm addq\subq throughput is 4
  { ISD::ADD,   MVT::v2i64, 4  },
  { ISD::SUB,   MVT::v2i64, 4  },
};

if (ST->isSLM()) {
  if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) {
    // Check if the operands can be shrinked into a smaller datatype.
    bool Op1Signed = false;
    unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed);
    bool Op2Signed = false;
    unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed);

    bool SignedMode = Op1Signed || Op2Signed;
    unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize);

    if (OpMinSize <= 7)
      return LT.first * 3; // pmullw/sext
    if (!SignedMode && OpMinSize <= 8)
      return LT.first * 3; // pmullw/zext
    if (OpMinSize <= 15)
      return LT.first * 5; // pmullw/pmulhw/pshuf
    if (!SignedMode && OpMinSize <= 16)
      return LT.first * 5; // pmullw/pmulhw/pshuf
  }

  if (const auto *Entry = CostTableLookup(SLMCostTable, ISD,
                                          LT.second)) {
    return LT.first * Entry->Cost;
  }
}

if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV ||
     ISD == ISD::UREM) &&
    (Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
     Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) &&
    Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) {
  if (ISD == ISD::SDIV || ISD == ISD::SREM) {
    // On X86, vector signed division by constants power-of-two are
    // normally expanded to the sequence SRA + SRL + ADD + SRA.
    // The OperandValue properties may not be the same as that of the previous
    // operation; conservatively assume OP_None.
    InstructionCost Cost =
        2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info,
                                   Op2Info, TargetTransformInfo::OP_None,
                                   TargetTransformInfo::OP_None);
    Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info,
                                   Op2Info,
                                   TargetTransformInfo::OP_None,
                                   TargetTransformInfo::OP_None);
    Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info,
                                   Op2Info,
                                   TargetTransformInfo::OP_None,
                                   TargetTransformInfo::OP_None);

    if (ISD == ISD::SREM) {
      // For SREM: (X % C) is the equivalent of (X - (X/C)*C)
      Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info,
                                     Op2Info);
      Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info,
                                     Op2Info);
    }

    return Cost;
  }

  // Vector unsigned division/remainder will be simplified to shifts/masks.
  if (ISD == ISD::UDIV)
    return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind,
                                  Op1Info, Op2Info,
                                  TargetTransformInfo::OP_None,
                                  TargetTransformInfo::OP_None);

  else // UREM
    return getArithmeticInstrCost(Instruction::And, Ty, CostKind,
                                  Op1Info, Op2Info,
                                  TargetTransformInfo::OP_None,
                                  TargetTransformInfo::OP_None);
}

static const CostTblEntry AVX512BWUniformConstCostTable[] = {
  { ISD::SHL,  MVT::v64i8,   2 }, // psllw + pand.
  { ISD::SRL,  MVT::v64i8,   2 }, // psrlw + pand.
  { ISD::SRA,  MVT::v64i8,   4 }, // psrlw, pand, pxor, psubb.
};

if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
    ST->hasBWI()) {
  if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD,
                                          LT.second))
    return LT.first * Entry->Cost;
}

static const CostTblEntry AVX512UniformConstCostTable[] = {
  { ISD::SRA,  MVT::v2i64,   1 },
  { ISD::SRA,  MVT::v4i64,   1 },
  { ISD::SRA,  MVT::v8i64,   1 },

  { ISD::SHL,  MVT::v64i8,   4 }, // psllw + pand.
  { ISD::SRL,  MVT::v64i8,   4 }, // psrlw + pand.
  { ISD::SRA,  MVT::v64i8,   8 }, // psrlw, pand, pxor, psubb.

  { ISD::SDIV, MVT::v16i32,  6 }, // pmuludq sequence
  { ISD::SREM, MVT::v16i32,  8 }, // pmuludq+mul+sub sequence
  { ISD::UDIV, MVT::v16i32,  5 }, // pmuludq sequence
  { ISD::UREM, MVT::v16i32,  7 }, // pmuludq+mul+sub sequence
};

if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
    ST->hasAVX512()) {
  if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD,
                                          LT.second))
    return LT.first * Entry->Cost;
}

static const CostTblEntry AVX2UniformConstCostTable[] = {
  { ISD::SHL,  MVT::v32i8,   2 }, // psllw + pand.
  { ISD::SRL,  MVT::v32i8,   2 }, // psrlw + pand.
  { ISD::SRA,  MVT::v32i8,   4 }, // psrlw, pand, pxor, psubb.

  { ISD::SRA,  MVT::v4i64,   4 }, // 2 x psrad + shuffle.

  { ISD::SDIV, MVT::v8i32,   6 }, // pmuludq sequence
  { ISD::SREM, MVT::v8i32,   8 }, // pmuludq+mul+sub sequence
  { ISD::UDIV, MVT::v8i32,   5 }, // pmuludq sequence
  { ISD::UREM, MVT::v8i32,   7 }, // pmuludq+mul+sub sequence
};

if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
    ST->hasAVX2()) {
  if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD,
                                          LT.second))
    return LT.first * Entry->Cost;
}

static const CostTblEntry SSE2UniformConstCostTable[] = {
  { ISD::SHL,  MVT::v16i8,     2 }, // psllw + pand.
  { ISD::SRL,  MVT::v16i8,     2 }, // psrlw + pand.
  { ISD::SRA,  MVT::v16i8,     4 }, // psrlw, pand, pxor, psubb.

  { ISD::SHL,  MVT::v32i8,   4+2 }, // 2*(psllw + pand) + split.
  { ISD::SRL,  MVT::v32i8,   4+2 }, // 2*(psrlw + pand) + split.
  { ISD::SRA,  MVT::v32i8,   8+2 }, // 2*(psrlw, pand, pxor, psubb) + split.

  { ISD::SDIV, MVT::v8i32,  12+2 }, // 2*pmuludq sequence + split.
  { ISD::SREM, MVT::v8i32,  16+2 }, // 2*pmuludq+mul+sub sequence + split.
  { ISD::SDIV, MVT::v4i32,     6 }, // pmuludq sequence
  { ISD::SREM, MVT::v4i32,     8 }, // pmuludq+mul+sub sequence
  { ISD::UDIV, MVT::v8i32,  10+2 }, // 2*pmuludq sequence + split.
  { ISD::UREM, MVT::v8i32,  14+2 }, // 2*pmuludq+mul+sub sequence + split.
  { ISD::UDIV, MVT::v4i32,     5 }, // pmuludq sequence
  { ISD::UREM, MVT::v4i32,     7 }, // pmuludq+mul+sub sequence
};

// XOP has faster vXi8 shifts.
if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
    ST->hasSSE2() && !ST->hasXOP()) {
  if (const auto *Entry =
          CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second))
    return LT.first * Entry->Cost;
}

static const CostTblEntry AVX512BWConstCostTable[] = {
  { ISD::SDIV, MVT::v64i8,  14 }, // 2*ext+2*pmulhw sequence
  { ISD::SREM, MVT::v64i8,  16 }, // 2*ext+2*pmulhw+mul+sub sequence
  { ISD::UDIV, MVT::v64i8,  14 }, // 2*ext+2*pmulhw sequence
  { ISD::UREM, MVT::v64i8,  16 }, // 2*ext+2*pmulhw+mul+sub sequence
  { ISD::SDIV, MVT::v32i16,  6 }, // vpmulhw sequence
  { ISD::SREM, MVT::v32i16,  8 }, // vpmulhw+mul+sub sequence
  { ISD::UDIV, MVT::v32i16,  6 }, // vpmulhuw sequence
  { ISD::UREM, MVT::v32i16,  8 }, // vpmulhuw+mul+sub sequence
};

if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
     Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) &&
    ST->hasBWI()) {
  if (const auto *Entry =
          CostTableLookup(AVX512BWConstCostTable, ISD, LT.second))
    return LT.first * Entry->Cost;
}

static const CostTblEntry AVX512ConstCostTable[] = {
  { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence
  { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence
  { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence
  { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence
  { ISD::SDIV, MVT::v64i8,  28 }, // 4*ext+4*pmulhw sequence
  { ISD::SREM, MVT::v64i8,  32 }, // 4*ext+4*pmulhw+mul+sub sequence
  { ISD::UDIV, MVT::v64i8,  28 }, // 4*ext+4*pmulhw sequence
  { ISD::UREM, MVT::v64i8,  32 }, // 4*ext+4*pmulhw+mul+sub sequence
  { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence
  { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence
  { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence
  { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence
};

if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
     Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) &&
    ST->hasAVX512()) {
  if (const auto *Entry =
          CostTableLookup(AVX512ConstCostTable, ISD, LT.second))
    return LT.first * Entry->Cost;
}

static const CostTblEntry AVX2ConstCostTable[] = {
  { ISD::SDIV, MVT::v32i8,  14 }, // 2*ext+2*pmulhw sequence
  { ISD::SREM, MVT::v32i8,  16 }, // 2*ext+2*pmulhw+mul+sub sequence
  { ISD::UDIV, MVT::v32i8,  14 }, // 2*ext+2*pmulhw sequence
  { ISD::UREM, MVT::v32i8,  16 }, // 2*ext+2*pmulhw+mul+sub sequence
  { ISD::SDIV, MVT::v16i16,  6 }, // vpmulhw sequence
  { ISD::SREM, MVT::v16i16,  8 }, // vpmulhw+mul+sub sequence
  { ISD::UDIV, MVT::v16i16,  6 }, // vpmulhuw sequence
  { ISD::UREM, MVT::v16i16,  8 }, // vpmulhuw+mul+sub sequence
  { ISD::SDIV, MVT::v8i32,  15 }, // vpmuldq sequence
  { ISD::SREM, MVT::v8i32,  19 }, // vpmuldq+mul+sub sequence
  { ISD::UDIV, MVT::v8i32,  15 }, // vpmuludq sequence
  { ISD::UREM, MVT::v8i32,  19 }, // vpmuludq+mul+sub sequence
};

if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
     Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) &&
    ST->hasAVX2()) {
  if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second))
    return LT.first * Entry->Cost;
}

static const CostTblEntry SSE2ConstCostTable[] = {
  { ISD::SDIV, MVT::v32i8,  28+2 }, // 4*ext+4*pmulhw sequence + split.
  { ISD::SREM, MVT::v32i8,  32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split.
  { ISD::SDIV, MVT::v16i8,    14 }, // 2*ext+2*pmulhw sequence
  { ISD::SREM, MVT::v16i8,    16 }, // 2*ext+2*pmulhw+mul+sub sequence
  { ISD::UDIV, MVT::v32i8,  28+2 }, // 4*ext+4*pmulhw sequence + split.
  { ISD::UREM, MVT::v32i8,  32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split.
  { ISD::UDIV, MVT::v16i8,    14 }, // 2*ext+2*pmulhw sequence
  { ISD::UREM, MVT::v16i8,    16 }, // 2*ext+2*pmulhw+mul+sub sequence
  { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split.
  { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split.
  { ISD::SDIV, MVT::v8i16,     6 }, // pmulhw sequence
  { ISD::SREM, MVT::v8i16,     8 }, // pmulhw+mul+sub sequence
  { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split.
  { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split.
  { ISD::UDIV, MVT::v8i16,     6 }, // pmulhuw sequence
  { ISD::UREM, MVT::v8i16,     8 }, // pmulhuw+mul+sub sequence
  { ISD::SDIV, MVT::v8i32,  38+2 }, // 2*pmuludq sequence + split.
  { ISD::SREM, MVT::v8i32,  48+2 }, // 2*pmuludq+mul+sub sequence + split.
  { ISD::SDIV, MVT::v4i32,    19 }, // pmuludq sequence
  { ISD::SREM, MVT::v4i32,    24 }, // pmuludq+mul+sub sequence
  { ISD::UDIV, MVT::v8i32,  30+2 }, // 2*pmuludq sequence + split.
  { ISD::UREM, MVT::v8i32,  40+2 }, // 2*pmuludq+mul+sub sequence + split.
  { ISD::UDIV, MVT::v4i32,    15 }, // pmuludq sequence
  { ISD::UREM, MVT::v4i32,    20 }, // pmuludq+mul+sub sequence
};

if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
     Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) &&
    ST->hasSSE2()) {
  // pmuldq sequence.
  if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX())
    return LT.first * 32;
  if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX())
    return LT.first * 38;
  if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41())
    return LT.first * 15;
  if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41())
    return LT.first * 20;

  if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second))
    return LT.first * Entry->Cost;
}

static const CostTblEntry AVX512BWShiftCostTable[] = {
  { ISD::SHL,   MVT::v16i8,      4 }, // extend/vpsllvw/pack sequence.
  { ISD::SRL,   MVT::v16i8,      4 }, // extend/vpsrlvw/pack sequence.
  { ISD::SRA,   MVT::v16i8,      4 }, // extend/vpsravw/pack sequence.
  { ISD::SHL,   MVT::v32i8,      4 }, // extend/vpsllvw/pack sequence.
  { ISD::SRL,   MVT::v32i8,      4 }, // extend/vpsrlvw/pack sequence.
  { ISD::SRA,   MVT::v32i8,      6 }, // extend/vpsravw/pack sequence.
  { ISD::SHL,   MVT::v64i8,      6 }, // extend/vpsllvw/pack sequence.
  { ISD::SRL,   MVT::v64i8,      7 }, // extend/vpsrlvw/pack sequence.
  { ISD::SRA,   MVT::v64i8,     15 }, // extend/vpsravw/pack sequence.

  { ISD::SHL,   MVT::v8i16,      1 }, // vpsllvw
  { ISD::SRL,   MVT::v8i16,      1 }, // vpsrlvw
  { ISD::SRA,   MVT::v8i16,      1 }, // vpsravw
  { ISD::SHL,   MVT::v16i16,     1 }, // vpsllvw
  { ISD::SRL,   MVT::v16i16,     1 }, // vpsrlvw
  { ISD::SRA,   MVT::v16i16,     1 }, // vpsravw
  { ISD::SHL,   MVT::v32i16,     1 }, // vpsllvw
  { ISD::SRL,   MVT::v32i16,     1 }, // vpsrlvw
  { ISD::SRA,   MVT::v32i16,     1 }, // vpsravw
};

if (ST->hasBWI())
  if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second))
    return LT.first * Entry->Cost;

static const CostTblEntry AVX2UniformCostTable[] = {
  // Uniform splats are cheaper for the following instructions.
  { ISD::SHL,  MVT::v16i16, 1 }, // psllw.
  { ISD::SRL,  MVT::v16i16, 1 }, // psrlw.
  { ISD::SRA,  MVT::v16i16, 1 }, // psraw.
  { ISD::SHL,  MVT::v32i16, 2 }, // 2*psllw.
  { ISD::SRL,  MVT::v32i16, 2 }, // 2*psrlw.
  { ISD::SRA,  MVT::v32i16, 2 }, // 2*psraw.

  { ISD::SHL,  MVT::v8i32,  1 }, // pslld
  { ISD::SRL,  MVT::v8i32,  1 }, // psrld
  { ISD::SRA,  MVT::v8i32,  1 }, // psrad
  { ISD::SHL,  MVT::v4i64,  1 }, // psllq
  { ISD::SRL,  MVT::v4i64,  1 }, // psrlq
};

if (ST->hasAVX2() &&
    ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) ||
     (Op2Info == TargetTransformInfo::OK_UniformValue))) {
  if (const auto *Entry =
          CostTableLookup(AVX2UniformCostTable, ISD, LT.second))
    return LT.first * Entry->Cost;
}

static const CostTblEntry SSE2UniformCostTable[] = {
  // Uniform splats are cheaper for the following instructions.
  { ISD::SHL,  MVT::v8i16,  1 }, // psllw.
  { ISD::SHL,  MVT::v4i32,  1 }, // pslld
  { ISD::SHL,  MVT::v2i64,  1 }, // psllq.

  { ISD::SRL,  MVT::v8i16,  1 }, // psrlw.
  { ISD::SRL,  MVT::v4i32,  1 }, // psrld.
  { ISD::SRL,  MVT::v2i64,  1 }, // psrlq.

  { ISD::SRA,  MVT::v8i16,  1 }, // psraw.
  { ISD::SRA,  MVT::v4i32,  1 }, // psrad.
};

if (ST->hasSSE2() &&
    ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) ||
     (Op2Info == TargetTransformInfo::OK_UniformValue))) {
  if (const auto *Entry =
          CostTableLookup(SSE2UniformCostTable, ISD, LT.second))
    return LT.first * Entry->Cost;
}

static const CostTblEntry AVX512DQCostTable[] = {
  { ISD::MUL,  MVT::v2i64, 2 }, // pmullq
  { ISD::MUL,  MVT::v4i64, 2 }, // pmullq
  { ISD::MUL,  MVT::v8i64, 2 }  // pmullq
};

// Look for AVX512DQ lowering tricks for custom cases.
if (ST->hasDQI())
  if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second))
    return LT.first * Entry->Cost;

static const CostTblEntry AVX512BWCostTable[] = {
  { ISD::SHL,   MVT::v64i8,     11 }, // vpblendvb sequence.
  { ISD::SRL,   MVT::v64i8,     11 }, // vpblendvb sequence.
  { ISD::SRA,   MVT::v64i8,     24 }, // vpblendvb sequence.
};

// Look for AVX512BW lowering tricks for custom cases.
if (ST->hasBWI())
  if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second))
    return LT.first * Entry->Cost;

static const CostTblEntry AVX512CostTable[] = {
  { ISD::SHL,     MVT::v4i32,      1 },
  { ISD::SRL,     MVT::v4i32,      1 },
  { ISD::SRA,     MVT::v4i32,      1 },
  { ISD::SHL,     MVT::v8i32,      1 },
  { ISD::SRL,     MVT::v8i32,      1 },
  { ISD::SRA,     MVT::v8i32,      1 },
  { ISD::SHL,     MVT::v16i32,     1 },
  { ISD::SRL,     MVT::v16i32,     1 },
  { ISD::SRA,     MVT::v16i32,     1 },

  { ISD::SHL,     MVT::v2i64,      1 },
  { ISD::SRL,     MVT::v2i64,      1 },
  { ISD::SHL,     MVT::v4i64,      1 },
  { ISD::SRL,     MVT::v4i64,      1 },
  { ISD::SHL,     MVT::v8i64,      1 },
  { ISD::SRL,     MVT::v8i64,      1 },

  { ISD::SRA,     MVT::v2i64,      1 },
  { ISD::SRA,     MVT::v4i64,      1 },
  { ISD::SRA,     MVT::v8i64,      1 },

  { ISD::MUL,     MVT::v16i32,     1 }, // pmulld (Skylake from agner.org)
  { ISD::MUL,     MVT::v8i32,      1 }, // pmulld (Skylake from agner.org)
  { ISD::MUL,     MVT::v4i32,      1 }, // pmulld (Skylake from agner.org)
  { ISD::MUL,     MVT::v8i64,      6 }, // 3*pmuludq/3*shift/2*add

  { ISD::FNEG,    MVT::v8f64,      1 }, // Skylake from http://www.agner.org/
  { ISD::FADD,    MVT::v8f64,      1 }, // Skylake from http://www.agner.org/
  { ISD::FSUB,    MVT::v8f64,      1 }, // Skylake from http://www.agner.org/
  { ISD::FMUL,    MVT::v8f64,      1 }, // Skylake from http://www.agner.org/
  { ISD::FDIV,    MVT::f64,        4 }, // Skylake from http://www.agner.org/
  { ISD::FDIV,    MVT::v2f64,      4 }, // Skylake from http://www.agner.org/
  { ISD::FDIV,    MVT::v4f64,      8 }, // Skylake from http://www.agner.org/
  { ISD::FDIV,    MVT::v8f64,     16 }, // Skylake from http://www.agner.org/

  { ISD::FNEG,    MVT::v16f32,     1 }, // Skylake from http://www.agner.org/
  { ISD::FADD,    MVT::v16f32,     1 }, // Skylake from http://www.agner.org/
  { ISD::FSUB,    MVT::v16f32,     1 }, // Skylake from http://www.agner.org/
  { ISD::FMUL,    MVT::v16f32,     1 }, // Skylake from http://www.agner.org/
  { ISD::FDIV,    MVT::f32,        3 }, // Skylake from http://www.agner.org/
  { ISD::FDIV,    MVT::v4f32,      3 }, // Skylake from http://www.agner.org/
  { ISD::FDIV,    MVT::v8f32,      5 }, // Skylake from http://www.agner.org/
  { ISD::FDIV,    MVT::v16f32,    10 }, // Skylake from http://www.agner.org/
};

if (ST->hasAVX512())
  if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second))
    return LT.first * Entry->Cost;

static const CostTblEntry AVX2ShiftCostTable[] = {
  // Shifts on vXi64/vXi32 on AVX2 is legal even though we declare to
  // customize them to detect the cases where shift amount is a scalar one.
  { ISD::SHL,     MVT::v4i32,    2 }, // vpsllvd (Haswell from agner.org)
  { ISD::SRL,     MVT::v4i32,    2 }, // vpsrlvd (Haswell from agner.org)
  { ISD::SRA,     MVT::v4i32,    2 }, // vpsravd (Haswell from agner.org)
  { ISD::SHL,     MVT::v8i32,    2 }, // vpsllvd (Haswell from agner.org)
  { ISD::SRL,     MVT::v8i32,    2 }, // vpsrlvd (Haswell from agner.org)
  { ISD::SRA,     MVT::v8i32,    2 }, // vpsravd (Haswell from agner.org)
  { ISD::SHL,     MVT::v2i64,    1 }, // vpsllvq (Haswell from agner.org)
  { ISD::SRL,     MVT::v2i64,    1 }, // vpsrlvq (Haswell from agner.org)
  { ISD::SHL,     MVT::v4i64,    1 }, // vpsllvq (Haswell from agner.org)
  { ISD::SRL,     MVT::v4i64,    1 }, // vpsrlvq (Haswell from agner.org)
};

if (ST->hasAVX512()) {
  if (ISD == ISD::SHL && LT.second == MVT::v32i16 &&
      (Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
       Op2Info == TargetTransformInfo::OK_NonUniformConstantValue))
    // On AVX512, a packed v32i16 shift left by a constant build_vector
    // is lowered into a vector multiply (vpmullw).
    return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind,
                                  Op1Info, Op2Info,
                                  TargetTransformInfo::OP_None,
                                  TargetTransformInfo::OP_None);
}

// Look for AVX2 lowering tricks (XOP is always better at v4i32 shifts).
if (ST->hasAVX2() && !(ST->hasXOP() && LT.second == MVT::v4i32)) {
  if (ISD == ISD::SHL && LT.second == MVT::v16i16 &&
      (Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
       Op2Info == TargetTransformInfo::OK_NonUniformConstantValue))
    // On AVX2, a packed v16i16 shift left by a constant build_vector
    // is lowered into a vector multiply (vpmullw).
    return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind,
                                  Op1Info, Op2Info,
                                  TargetTransformInfo::OP_None,
                                  TargetTransformInfo::OP_None);

  if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second))
    return LT.first * Entry->Cost;
}

static const CostTblEntry XOPShiftCostTable[] = {
  // 128bit shifts take 1cy, but right shifts require negation beforehand.
  { ISD::SHL,     MVT::v16i8,    1 },
  { ISD::SRL,     MVT::v16i8,    2 },
  { ISD::SRA,     MVT::v16i8,    2 },
  { ISD::SHL,     MVT::v8i16,    1 },
  { ISD::SRL,     MVT::v8i16,    2 },
  { ISD::SRA,     MVT::v8i16,    2 },
  { ISD::SHL,     MVT::v4i32,    1 },
  { ISD::SRL,     MVT::v4i32,    2 },
  { ISD::SRA,     MVT::v4i32,    2 },
  { ISD::SHL,     MVT::v2i64,    1 },
  { ISD::SRL,     MVT::v2i64,    2 },
  { ISD::SRA,     MVT::v2i64,    2 },
  // 256bit shifts require splitting if AVX2 didn't catch them above.
  { ISD::SHL,     MVT::v32i8,  2+2 },
  { ISD::SRL,     MVT::v32i8,  4+2 },
  { ISD::SRA,     MVT::v32i8,  4+2 },
  { ISD::SHL,     MVT::v16i16, 2+2 },
  { ISD::SRL,     MVT::v16i16, 4+2 },
  { ISD::SRA,     MVT::v16i16, 4+2 },
  { ISD::SHL,     MVT::v8i32,  2+2 },
  { ISD::SRL,     MVT::v8i32,  4+2 },
  { ISD::SRA,     MVT::v8i32,  4+2 },
  { ISD::SHL,     MVT::v4i64,  2+2 },
  { ISD::SRL,     MVT::v4i64,  4+2 },
  { ISD::SRA,     MVT::v4i64,  4+2 },
};

// Look for XOP lowering tricks.
if (ST->hasXOP()) {
  // If the right shift is constant then we'll fold the negation so
  // it's as cheap as a left shift.
  int ShiftISD = ISD;
  if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) &&
      (Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
       Op2Info == TargetTransformInfo::OK_NonUniformConstantValue))
    ShiftISD = ISD::SHL;
  if (const auto *Entry =
          CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second))
    return LT.first * Entry->Cost;
}

static const CostTblEntry SSE2UniformShiftCostTable[] = {
  // Uniform splats are cheaper for the following instructions.
  { ISD::SHL,  MVT::v16i16, 2+2 }, // 2*psllw + split.
  { ISD::SHL,  MVT::v8i32,  2+2 }, // 2*pslld + split.
  { ISD::SHL,  MVT::v4i64,  2+2 }, // 2*psllq + split.

  { ISD::SRL,  MVT::v16i16, 2+2 }, // 2*psrlw + split.
  { ISD::SRL,  MVT::v8i32,  2+2 }, // 2*psrld + split.
  { ISD::SRL,  MVT::v4i64,  2+2 }, // 2*psrlq + split.

  { ISD::SRA,  MVT::v16i16, 2+2 }, // 2*psraw + split.
  { ISD::SRA,  MVT::v8i32,  2+2 }, // 2*psrad + split.
  { ISD::SRA,  MVT::v2i64,    4 }, // 2*psrad + shuffle.
  { ISD::SRA,  MVT::v4i64,  8+2 }, // 2*(2*psrad + shuffle) + split.
};

if (ST->hasSSE2() &&
    ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) ||
     (Op2Info == TargetTransformInfo::OK_UniformValue))) {

  // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table.
  if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2())
    return LT.first * 4; // 2*psrad + shuffle.

  if (const auto *Entry =
          CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second))
    return LT.first * Entry->Cost;
}

if (ISD == ISD::SHL &&
    Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) {
  MVT VT = LT.second;
  // Vector shift left by non uniform constant can be lowered
  // into vector multiply.
  if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) ||
      ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX()))
    ISD = ISD::MUL;
}

static const CostTblEntry AVX2CostTable[] = {
  { ISD::SHL,  MVT::v16i8,      6 }, // vpblendvb sequence.
  { ISD::SHL,  MVT::v32i8,      6 }, // vpblendvb sequence.
  { ISD::SHL,  MVT::v64i8,     12 }, // 2*vpblendvb sequence.
  { ISD::SHL,  MVT::v8i16,      5 }, // extend/vpsrlvd/pack sequence.
  { ISD::SHL,  MVT::v16i16,     7 }, // extend/vpsrlvd/pack sequence.
  { ISD::SHL,  MVT::v32i16,    14 }, // 2*extend/vpsrlvd/pack sequence.

  { ISD::SRL,  MVT::v16i8,      6 }, // vpblendvb sequence.
  { ISD::SRL,  MVT::v32i8,      6 }, // vpblendvb sequence.
  { ISD::SRL,  MVT::v64i8,     12 }, // 2*vpblendvb sequence.
  { ISD::SRL,  MVT::v8i16,      5 }, // extend/vpsrlvd/pack sequence.
  { ISD::SRL,  MVT::v16i16,     7 }, // extend/vpsrlvd/pack sequence.
  { ISD::SRL,  MVT::v32i16,    14 }, // 2*extend/vpsrlvd/pack sequence.

  { ISD::SRA,  MVT::v16i8,     17 }, // vpblendvb sequence.
  { ISD::SRA,  MVT::v32i8,     17 }, // vpblendvb sequence.
  { ISD::SRA,  MVT::v64i8,     34 }, // 2*vpblendvb sequence.
  { ISD::SRA,  MVT::v8i16,      5 }, // extend/vpsravd/pack sequence.
  { ISD::SRA,  MVT::v16i16,     7 }, // extend/vpsravd/pack sequence.
  { ISD::SRA,  MVT::v32i16,    14 }, // 2*extend/vpsravd/pack sequence.
  { ISD::SRA,  MVT::v2i64,      2 }, // srl/xor/sub sequence.
  { ISD::SRA,  MVT::v4i64,      2 }, // srl/xor/sub sequence.

  { ISD::SUB,  MVT::v32i8,      1 }, // psubb
  { ISD::ADD,  MVT::v32i8,      1 }, // paddb
  { ISD::SUB,  MVT::v16i16,     1 }, // psubw
  { ISD::ADD,  MVT::v16i16,     1 }, // paddw
  { ISD::SUB,  MVT::v8i32,      1 }, // psubd
  { ISD::ADD,  MVT::v8i32,      1 }, // paddd
  { ISD::SUB,  MVT::v4i64,      1 }, // psubq
  { ISD::ADD,  MVT::v4i64,      1 }, // paddq

  { ISD::MUL,  MVT::v16i16,     1 }, // pmullw
  { ISD::MUL,  MVT::v8i32,      2 }, // pmulld (Haswell from agner.org)
  { ISD::MUL,  MVT::v4i64,      6 }, // 3*pmuludq/3*shift/2*add

  { ISD::FNEG, MVT::v4f64,      1 }, // Haswell from http://www.agner.org/
  { ISD::FNEG, MVT::v8f32,      1 }, // Haswell from http://www.agner.org/
  { ISD::FADD, MVT::v4f64,      1 }, // Haswell from http://www.agner.org/
  { ISD::FADD, MVT::v8f32,      1 }, // Haswell from http://www.agner.org/
  { ISD::FSUB, MVT::v4f64,      1 }, // Haswell from http://www.agner.org/
  { ISD::FSUB, MVT::v8f32,      1 }, // Haswell from http://www.agner.org/
  { ISD::FMUL, MVT::f64,        1 }, // Haswell from http://www.agner.org/
  { ISD::FMUL, MVT::v2f64,      1 }, // Haswell from http://www.agner.org/
  { ISD::FMUL, MVT::v4f64,      1 }, // Haswell from http://www.agner.org/
  { ISD::FMUL, MVT::v8f32,      1 }, // Haswell from http://www.agner.org/

  { ISD::FDIV, MVT::f32,        7 }, // Haswell from http://www.agner.org/
  { ISD::FDIV, MVT::v4f32,      7 }, // Haswell from http://www.agner.org/
  { ISD::FDIV, MVT::v8f32,     14 }, // Haswell from http://www.agner.org/
  { ISD::FDIV, MVT::f64,       14 }, // Haswell from http://www.agner.org/
  { ISD::FDIV, MVT::v2f64,     14 }, // Haswell from http://www.agner.org/
  { ISD::FDIV, MVT::v4f64,     28 }, // Haswell from http://www.agner.org/
};

// Look for AVX2 lowering tricks for custom cases.
if (ST->hasAVX2())
  if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second))
    return LT.first * Entry->Cost;

static const CostTblEntry AVX1CostTable[] = {
  // We don't have to scalarize unsupported ops. We can issue two half-sized
  // operations and we only need to extract the upper YMM half.
  // Two ops + 1 extract + 1 insert = 4.
  { ISD::MUL,     MVT::v16i16,     4 },
  { ISD::MUL,     MVT::v8i32,      5 }, // BTVER2 from http://www.agner.org/
  { ISD::MUL,     MVT::v4i64,     12 },

  { ISD::SUB,     MVT::v32i8,      4 },
  { ISD::ADD,     MVT::v32i8,      4 },
  { ISD::SUB,     MVT::v16i16,     4 },
  { ISD::ADD,     MVT::v16i16,     4 },
  { ISD::SUB,     MVT::v8i32,      4 },
  { ISD::ADD,     MVT::v8i32,      4 },
  { ISD::SUB,     MVT::v4i64,      4 },
  { ISD::ADD,     MVT::v4i64,      4 },

  { ISD::SHL,     MVT::v32i8,     22 }, // pblendvb sequence + split.
  { ISD::SHL,     MVT::v8i16,      6 }, // pblendvb sequence.
  { ISD::SHL,     MVT::v16i16,    13 }, // pblendvb sequence + split.
  { ISD::SHL,     MVT::v4i32,      3 }, // pslld/paddd/cvttps2dq/pmulld
  { ISD::SHL,     MVT::v8i32,      9 }, // pslld/paddd/cvttps2dq/pmulld + split
  { ISD::SHL,     MVT::v2i64,      2 }, // Shift each lane + blend.
  { ISD::SHL,     MVT::v4i64,      6 }, // Shift each lane + blend + split.

  { ISD::SRL,     MVT::v32i8,     23 }, // pblendvb sequence + split.
  { ISD::SRL,     MVT::v16i16,    28 }, // pblendvb sequence + split.
  { ISD::SRL,     MVT::v4i32,      6 }, // Shift each lane + blend.
  { ISD::SRL,     MVT::v8i32,     14 }, // Shift each lane + blend + split.
  { ISD::SRL,     MVT::v2i64,      2 }, // Shift each lane + blend.
  { ISD::SRL,     MVT::v4i64,      6 }, // Shift each lane + blend + split.

  { ISD::SRA,     MVT::v32i8,     44 }, // pblendvb sequence + split.
  { ISD::SRA,     MVT::v16i16,    28 }, // pblendvb sequence + split.
  { ISD::SRA,     MVT::v4i32,      6 }, // Shift each lane + blend.
  { ISD::SRA,     MVT::v8i32,     14 }, // Shift each lane + blend + split.
  { ISD::SRA,     MVT::v2i64,      5 }, // Shift each lane + blend.
  { ISD::SRA,     MVT::v4i64,     12 }, // Shift each lane + blend + split.

  { ISD::FNEG,    MVT::v4f64,      2 }, // BTVER2 from http://www.agner.org/
  { ISD::FNEG,    MVT::v8f32,      2 }, // BTVER2 from http://www.agner.org/

  { ISD::FMUL,    MVT::f64,        2 }, // BTVER2 from http://www.agner.org/
  { ISD::FMUL,    MVT::v2f64,      2 }, // BTVER2 from http://www.agner.org/
  { ISD::FMUL,    MVT::v4f64,      4 }, // BTVER2 from http://www.agner.org/

  { ISD::FDIV,    MVT::f32,       14 }, // SNB from http://www.agner.org/
  { ISD::FDIV,    MVT::v4f32,     14 }, // SNB from http://www.agner.org/
  { ISD::FDIV,    MVT::v8f32,     28 }, // SNB from http://www.agner.org/
  { ISD::FDIV,    MVT::f64,       22 }, // SNB from http://www.agner.org/
  { ISD::FDIV,    MVT::v2f64,     22 }, // SNB from http://www.agner.org/
  { ISD::FDIV,    MVT::v4f64,     44 }, // SNB from http://www.agner.org/
};

if (ST->hasAVX())
  if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second))
    return LT.first * Entry->Cost;

static const CostTblEntry SSE42CostTable[] = {
  { ISD::FADD, MVT::f64,     1 }, // Nehalem from http://www.agner.org/
  { ISD::FADD, MVT::f32,     1 }, // Nehalem from http://www.agner.org/
  { ISD::FADD, MVT::v2f64,   1 }, // Nehalem from http://www.agner.org/
  { ISD::FADD, MVT::v4f32,   1 }, // Nehalem from http://www.agner.org/

  { ISD::FSUB, MVT::f64,     1 }, // Nehalem from http://www.agner.org/
  { ISD::FSUB, MVT::f32 ,    1 }, // Nehalem from http://www.agner.org/
  { ISD::FSUB, MVT::v2f64,   1 }, // Nehalem from http://www.agner.org/
  { ISD::FSUB, MVT::v4f32,   1 }, // Nehalem from http://www.agner.org/

  { ISD::FMUL, MVT::f64,     1 }, // Nehalem from http://www.agner.org/
  { ISD::FMUL, MVT::f32,     1 }, // Nehalem from http://www.agner.org/
  { ISD::FMUL, MVT::v2f64,   1 }, // Nehalem from http://www.agner.org/
  { ISD::FMUL, MVT::v4f32,   1 }, // Nehalem from http://www.agner.org/

  { ISD::FDIV,  MVT::f32,   14 }, // Nehalem from http://www.agner.org/
  { ISD::FDIV,  MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/
  { ISD::FDIV,  MVT::f64,   22 }, // Nehalem from http://www.agner.org/
  { ISD::FDIV,  MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/

  { ISD::MUL,   MVT::v2i64,  6 }  // 3*pmuludq/3*shift/2*add
};

if (ST->hasSSE42())
  if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second))
    return LT.first * Entry->Cost;

static const CostTblEntry SSE41CostTable[] = {
  { ISD::SHL,  MVT::v16i8,      10 }, // pblendvb sequence.
  { ISD::SHL,  MVT::v8i16,      11 }, // pblendvb sequence.
  { ISD::SHL,  MVT::v4i32,       4 }, // pslld/paddd/cvttps2dq/pmulld

  { ISD::SRL,  MVT::v16i8,      11 }, // pblendvb sequence.
  { ISD::SRL,  MVT::v8i16,      13 }, // pblendvb sequence.
  { ISD::SRL,  MVT::v4i32,      16 }, // Shift each lane + blend.

  { ISD::SRA,  MVT::v16i8,      21 }, // pblendvb sequence.
  { ISD::SRA,  MVT::v8i16,      13 }, // pblendvb sequence.

  { ISD::MUL,  MVT::v4i32,       2 }  // pmulld (Nehalem from agner.org)
};

if (ST->hasSSE41())
  if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second))
    return LT.first * Entry->Cost;

static const CostTblEntry SSE2CostTable[] = {
  // We don't correctly identify costs of casts because they are marked as
  // custom.
  { ISD::SHL,  MVT::v16i8,      13 }, // cmpgtb sequence.
  { ISD::SHL,  MVT::v8i16,      25 }, // cmpgtw sequence.
  { ISD::SHL,  MVT::v4i32,      16 }, // pslld/paddd/cvttps2dq/pmuludq.
  { ISD::SHL,  MVT::v2i64,       4 }, // splat+shuffle sequence.

  { ISD::SRL,  MVT::v16i8,      14 }, // cmpgtb sequence.
  { ISD::SRL,  MVT::v8i16,      16 }, // cmpgtw sequence.
  { ISD::SRL,  MVT::v4i32,      12 }, // Shift each lane + blend.
  { ISD::SRL,  MVT::v2i64,       4 }, // splat+shuffle sequence.

  { ISD::SRA,  MVT::v16i8,      27 }, // unpacked cmpgtb sequence.
  { ISD::SRA,  MVT::v8i16,      16 }, // cmpgtw sequence.
  { ISD::SRA,  MVT::v4i32,      12 }, // Shift each lane + blend.
  { ISD::SRA,  MVT::v2i64,       8 }, // srl/xor/sub splat+shuffle sequence.

  { ISD::MUL,  MVT::v8i16,       1 }, // pmullw
  { ISD::MUL,  MVT::v4i32,       6 }, // 3*pmuludq/4*shuffle
  { ISD::MUL,  MVT::v2i64,       8 }, // 3*pmuludq/3*shift/2*add

  { ISD::FDIV, MVT::f32,        23 }, // Pentium IV from http://www.agner.org/
  { ISD::FDIV, MVT::v4f32,      39 }, // Pentium IV from http://www.agner.org/
  { ISD::FDIV, MVT::f64,        38 }, // Pentium IV from http://www.agner.org/
  { ISD::FDIV, MVT::v2f64,      69 }, // Pentium IV from http://www.agner.org/

  { ISD::FNEG, MVT::f32,         1 }, // Pentium IV from http://www.agner.org/
  { ISD::FNEG, MVT::f64,         1 }, // Pentium IV from http://www.agner.org/
  { ISD::FNEG, MVT::v4f32,       1 }, // Pentium IV from http://www.agner.org/
  { ISD::FNEG, MVT::v2f64,       1 }, // Pentium IV from http://www.agner.org/

  { ISD::FADD, MVT::f32,         2 }, // Pentium IV from http://www.agner.org/
  { ISD::FADD, MVT::f64,         2 }, // Pentium IV from http://www.agner.org/

  { ISD::FSUB, MVT::f32,         2 }, // Pentium IV from http://www.agner.org/
  { ISD::FSUB, MVT::f64,         2 }, // Pentium IV from http://www.agner.org/
};

if (ST->hasSSE2())
  if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second))
    return LT.first * Entry->Cost;

static const CostTblEntry SSE1CostTable[] = {
  { ISD::FDIV, MVT::f32,   17 }, // Pentium III from http://www.agner.org/
  { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/

  { ISD::FNEG, MVT::f32,    2 }, // Pentium III from http://www.agner.org/
  { ISD::FNEG, MVT::v4f32,  2 }, // Pentium III from http://www.agner.org/

  { ISD::FADD, MVT::f32,    1 }, // Pentium III from http://www.agner.org/
  { ISD::FADD, MVT::v4f32,  2 }, // Pentium III from http://www.agner.org/

  { ISD::FSUB, MVT::f32,    1 }, // Pentium III from http://www.agner.org/
  { ISD::FSUB, MVT::v4f32,  2 }, // Pentium III from http://www.agner.org/
};

if (ST->hasSSE1())
  if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second))
    return LT.first * Entry->Cost;

static const CostTblEntry X64CostTbl[] = { // 64-bit targets
  { ISD::ADD,  MVT::i64,    1 }, // Core (Merom) from http://www.agner.org/
  { ISD::SUB,  MVT::i64,    1 }, // Core (Merom) from http://www.agner.org/
};

if (ST->is64Bit())
  if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, LT.second))
    return LT.first * Entry->Cost;

static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets
  { ISD::ADD,  MVT::i8,    1 }, // Pentium III from http://www.agner.org/
  { ISD::ADD,  MVT::i16,   1 }, // Pentium III from http://www.agner.org/
  { ISD::ADD,  MVT::i32,   1 }, // Pentium III from http://www.agner.org/

  { ISD::SUB,  MVT::i8,    1 }, // Pentium III from http://www.agner.org/
  { ISD::SUB,  MVT::i16,   1 }, // Pentium III from http://www.agner.org/
  { ISD::SUB,  MVT::i32,   1 }, // Pentium III from http://www.agner.org/
};

if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, LT.second))
  return LT.first * Entry->Cost;

// It is not a good idea to vectorize division. We have to scalarize it and
// in the process we will often end up having to spilling regular
// registers. The overhead of division is going to dominate most kernels
// anyways so try hard to prevent vectorization of division - it is
// generally a bad idea. Assume somewhat arbitrarily that we have to be able
// to hide "20 cycles" for each lane.
if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM ||
                             ISD == ISD::UDIV || ISD == ISD::UREM)) {
  InstructionCost ScalarCost = getArithmeticInstrCost(
      Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info,
      TargetTransformInfo::OP_None, TargetTransformInfo::OP_None);
  return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost;
}

// Fallback to the default implementation.
return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info);
1043}

1045InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
                                         VectorType *BaseTp,
                                         ArrayRef<int> Mask, int Index,
                                         VectorType *SubTp) {
// 64-bit packed float vectors (v2f32) are widened to type v4f32.
// 64-bit packed integer vectors (v2i32) are widened to type v4i32.
std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp);

Kind = improveShuffleKindFromMask(Kind, Mask);
// Treat Transpose as 2-op shuffles - there's no difference in lowering.
if (Kind == TTI::SK_Transpose)
  Kind = TTI::SK_PermuteTwoSrc;

// For Broadcasts we are splatting the first element from the first input
// register, so only need to reference that input and all the output
// registers are the same.
if (Kind == TTI::SK_Broadcast)
  LT.first = 1;

// Subvector extractions are free if they start at the beginning of a
// vector and cheap if the subvectors are aligned.
if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) {
  int NumElts = LT.second.getVectorNumElements();
  if ((Index % NumElts) == 0)
    return 0;
  std::pair<InstructionCost, MVT> SubLT =
      TLI->getTypeLegalizationCost(DL, SubTp);
  if (SubLT.second.isVector()) {
    int NumSubElts = SubLT.second.getVectorNumElements();
    if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0)
      return SubLT.first;
    // Handle some cases for widening legalization. For now we only handle
    // cases where the original subvector was naturally aligned and evenly
    // fit in its legalized subvector type.
    // FIXME: Remove some of the alignment restrictions.
    // FIXME: We can use permq for 64-bit or larger extracts from 256-bit
    // vectors.
    int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements();
    if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 &&
        (NumSubElts % OrigSubElts) == 0 &&
        LT.second.getVectorElementType() ==
            SubLT.second.getVectorElementType() &&
        LT.second.getVectorElementType().getSizeInBits() ==
            BaseTp->getElementType()->getPrimitiveSizeInBits()) {
      assert(NumElts >= NumSubElts && NumElts > OrigSubElts &&((void)0)
             "Unexpected number of elements!")((void)0);
      auto *VecTy = FixedVectorType::get(BaseTp->getElementType(),
                                         LT.second.getVectorNumElements());
      auto *SubTy = FixedVectorType::get(BaseTp->getElementType(),
                                         SubLT.second.getVectorNumElements());
      int ExtractIndex = alignDown((Index % NumElts), NumSubElts);
      InstructionCost ExtractCost = getShuffleCost(
          TTI::SK_ExtractSubvector, VecTy, None, ExtractIndex, SubTy);

      // If the original size is 32-bits or more, we can use pshufd. Otherwise
      // if we have SSSE3 we can use pshufb.
      if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3())
        return ExtractCost + 1; // pshufd or pshufb

      assert(SubTp->getPrimitiveSizeInBits() == 16 &&((void)0)
             "Unexpected vector size")((void)0);

      return ExtractCost + 2; // worst case pshufhw + pshufd
    }
  }
}

// Subvector insertions are cheap if the subvectors are aligned.
// Note that in general, the insertion starting at the beginning of a vector
// isn't free, because we need to preserve the rest of the wide vector.
if (Kind == TTI::SK_InsertSubvector && LT.second.isVector()) {
  int NumElts = LT.second.getVectorNumElements();
  std::pair<InstructionCost, MVT> SubLT =
      TLI->getTypeLegalizationCost(DL, SubTp);
  if (SubLT.second.isVector()) {
    int NumSubElts = SubLT.second.getVectorNumElements();
    if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0)
      return SubLT.first;
  }
}

// Handle some common (illegal) sub-vector types as they are often very cheap
// to shuffle even on targets without PSHUFB.
EVT VT = TLI->getValueType(DL, BaseTp);
if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 &&
    !ST->hasSSSE3()) {
   static const CostTblEntry SSE2SubVectorShuffleTbl[] = {
    {TTI::SK_Broadcast,        MVT::v4i16, 1}, // pshuflw
    {TTI::SK_Broadcast,        MVT::v2i16, 1}, // pshuflw
    {TTI::SK_Broadcast,        MVT::v8i8,  2}, // punpck/pshuflw
    {TTI::SK_Broadcast,        MVT::v4i8,  2}, // punpck/pshuflw
    {TTI::SK_Broadcast,        MVT::v2i8,  1}, // punpck

    {TTI::SK_Reverse,          MVT::v4i16, 1}, // pshuflw
    {TTI::SK_Reverse,          MVT::v2i16, 1}, // pshuflw
    {TTI::SK_Reverse,          MVT::v4i8,  3}, // punpck/pshuflw/packus
    {TTI::SK_Reverse,          MVT::v2i8,  1}, // punpck

    {TTI::SK_PermuteTwoSrc,    MVT::v4i16, 2}, // punpck/pshuflw
    {TTI::SK_PermuteTwoSrc,    MVT::v2i16, 2}, // punpck/pshuflw
    {TTI::SK_PermuteTwoSrc,    MVT::v8i8,  7}, // punpck/pshuflw
    {TTI::SK_PermuteTwoSrc,    MVT::v4i8,  4}, // punpck/pshuflw
    {TTI::SK_PermuteTwoSrc,    MVT::v2i8,  2}, // punpck

    {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw
    {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw
    {TTI::SK_PermuteSingleSrc, MVT::v8i8,  5}, // punpck/pshuflw
    {TTI::SK_PermuteSingleSrc, MVT::v4i8,  3}, // punpck/pshuflw
    {TTI::SK_PermuteSingleSrc, MVT::v2i8,  1}, // punpck
  };

  if (ST->hasSSE2())
    if (const auto *Entry =
            CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT()))
      return Entry->Cost;
}

// We are going to permute multiple sources and the result will be in multiple
// destinations. Providing an accurate cost only for splits where the element
// type remains the same.
if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) {
  MVT LegalVT = LT.second;
  if (LegalVT.isVector() &&
      LegalVT.getVectorElementType().getSizeInBits() ==
          BaseTp->getElementType()->getPrimitiveSizeInBits() &&
      LegalVT.getVectorNumElements() <
          cast<FixedVectorType>(BaseTp)->getNumElements()) {

    unsigned VecTySize = DL.getTypeStoreSize(BaseTp);
    unsigned LegalVTSize = LegalVT.getStoreSize();
    // Number of source vectors after legalization:
    unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize;
    // Number of destination vectors after legalization:
    InstructionCost NumOfDests = LT.first;

    auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(),
                                            LegalVT.getVectorNumElements());

    InstructionCost NumOfShuffles = (NumOfSrcs - 1) * NumOfDests;
    return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy,
                                          None, 0, nullptr);
  }

  return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp);
}

// For 2-input shuffles, we must account for splitting the 2 inputs into many.
if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) {
  // We assume that source and destination have the same vector type.
  InstructionCost NumOfDests = LT.first;
  InstructionCost NumOfShufflesPerDest = LT.first * 2 - 1;
  LT.first = NumOfDests * NumOfShufflesPerDest;
}

static const CostTblEntry AVX512VBMIShuffleTbl[] = {
    {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb
    {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb

    {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb
    {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb

    {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b
    {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b
    {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2}  // vpermt2b
};

if (ST->hasVBMI())
  if (const auto *Entry =
          CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second))
    return LT.first * Entry->Cost;

static const CostTblEntry AVX512BWShuffleTbl[] = {
    {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw
    {TTI::SK_Broadcast, MVT::v64i8, 1},  // vpbroadcastb

    {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw
    {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw
    {TTI::SK_Reverse, MVT::v64i8, 2},  // pshufb + vshufi64x2

    {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw
    {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw
    {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8},  // extend to v32i16

    {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w
    {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w
    {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2},  // vpermt2w
    {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1

    {TTI::SK_Select, MVT::v32i16, 1}, // vblendmw
    {TTI::SK_Select, MVT::v64i8,  1}, // vblendmb
};

if (ST->hasBWI())
  if (const auto *Entry =
          CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second))
    return LT.first * Entry->Cost;

static const CostTblEntry AVX512ShuffleTbl[] = {
    {TTI::SK_Broadcast, MVT::v8f64, 1},  // vbroadcastpd
    {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps
    {TTI::SK_Broadcast, MVT::v8i64, 1},  // vpbroadcastq
    {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd
    {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw
    {TTI::SK_Broadcast, MVT::v64i8, 1},  // vpbroadcastb

    {TTI::SK_Reverse, MVT::v8f64, 1},  // vpermpd
    {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps
    {TTI::SK_Reverse, MVT::v8i64, 1},  // vpermq
    {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd
    {TTI::SK_Reverse, MVT::v32i16, 7}, // per mca
    {TTI::SK_Reverse, MVT::v64i8,  7}, // per mca

    {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1},  // vpermpd
    {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1},  // vpermpd
    {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1},  // vpermpd
    {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps
    {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1},  // vpermps
    {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1},  // vpermps
    {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1},  // vpermq
    {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1},  // vpermq
    {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1},  // vpermq
    {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd
    {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1},  // vpermd
    {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1},  // vpermd
    {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1},  // pshufb

    {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1},  // vpermt2pd
    {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps
    {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1},  // vpermt2q
    {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d
    {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1},  // vpermt2pd
    {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1},  // vpermt2ps
    {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1},  // vpermt2q
    {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1},  // vpermt2d
    {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1},  // vpermt2pd
    {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1},  // vpermt2ps
    {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1},  // vpermt2q
    {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1},  // vpermt2d

    // FIXME: This just applies the type legalization cost rules above
    // assuming these completely split.
    {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14},
    {TTI::SK_PermuteSingleSrc, MVT::v64i8,  14},
    {TTI::SK_PermuteTwoSrc,    MVT::v32i16, 42},
    {TTI::SK_PermuteTwoSrc,    MVT::v64i8,  42},

    {TTI::SK_Select, MVT::v32i16, 1}, // vpternlogq
    {TTI::SK_Select, MVT::v64i8,  1}, // vpternlogq
    {TTI::SK_Select, MVT::v8f64,  1}, // vblendmpd
    {TTI::SK_Select, MVT::v16f32, 1}, // vblendmps
    {TTI::SK_Select, MVT::v8i64,  1}, // vblendmq
    {TTI::SK_Select, MVT::v16i32, 1}, // vblendmd
};

if (ST->hasAVX512())
  if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second))
    return LT.first * Entry->Cost;

static const CostTblEntry AVX2ShuffleTbl[] = {
    {TTI::SK_Broadcast, MVT::v4f64, 1},  // vbroadcastpd
    {TTI::SK_Broadcast, MVT::v8f32, 1},  // vbroadcastps
    {TTI::SK_Broadcast, MVT::v4i64, 1},  // vpbroadcastq
    {TTI::SK_Broadcast, MVT::v8i32, 1},  // vpbroadcastd
    {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw
    {TTI::SK_Broadcast, MVT::v32i8, 1},  // vpbroadcastb

    {TTI::SK_Reverse, MVT::v4f64, 1},  // vpermpd
    {TTI::SK_Reverse, MVT::v8f32, 1},  // vpermps
    {TTI::SK_Reverse, MVT::v4i64, 1},  // vpermq
    {TTI::SK_Reverse, MVT::v8i32, 1},  // vpermd
    {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb
    {TTI::SK_Reverse, MVT::v32i8, 2},  // vperm2i128 + pshufb

    {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb
    {TTI::SK_Select, MVT::v32i8, 1},  // vpblendvb

    {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1},  // vpermpd
    {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1},  // vpermps
    {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1},  // vpermq
    {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1},  // vpermd
    {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb
                                                // + vpblendvb
    {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4},  // vperm2i128 + 2*vpshufb
                                                // + vpblendvb

    {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3},  // 2*vpermpd + vblendpd
    {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3},  // 2*vpermps + vblendps
    {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3},  // 2*vpermq + vpblendd
    {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3},  // 2*vpermd + vpblendd
    {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb
                                             // + vpblendvb
    {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7},  // 2*vperm2i128 + 4*vpshufb
                                             // + vpblendvb
};

if (ST->hasAVX2())
  if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second))
    return LT.first * Entry->Cost;

static const CostTblEntry XOPShuffleTbl[] = {
    {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2},  // vperm2f128 + vpermil2pd
    {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2},  // vperm2f128 + vpermil2ps
    {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2},  // vperm2f128 + vpermil2pd
    {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2},  // vperm2f128 + vpermil2ps
    {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm
                                                // + vinsertf128
    {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4},  // vextractf128 + 2*vpperm
                                                // + vinsertf128

    {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm
                                             // + vinsertf128
    {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1},  // vpperm
    {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9},  // 2*vextractf128 + 6*vpperm
                                             // + vinsertf128
    {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1},  // vpperm
};

if (ST->hasXOP())
  if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second))
    return LT.first * Entry->Cost;

static const CostTblEntry AVX1ShuffleTbl[] = {
    {TTI::SK_Broadcast, MVT::v4f64, 2},  // vperm2f128 + vpermilpd
    {TTI::SK_Broadcast, MVT::v8f32, 2},  // vperm2f128 + vpermilps
    {TTI::SK_Broadcast, MVT::v4i64, 2},  // vperm2f128 + vpermilpd
    {TTI::SK_Broadcast, MVT::v8i32, 2},  // vperm2f128 + vpermilps
    {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128
    {TTI::SK_Broadcast, MVT::v32i8, 2},  // vpshufb + vinsertf128

    {TTI::SK_Reverse, MVT::v4f64, 2},  // vperm2f128 + vpermilpd
    {TTI::SK_Reverse, MVT::v8f32, 2},  // vperm2f128 + vpermilps
    {TTI::SK_Reverse, MVT::v4i64, 2},  // vperm2f128 + vpermilpd
    {TTI::SK_Reverse, MVT::v8i32, 2},  // vperm2f128 + vpermilps
    {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb
                                       // + vinsertf128
    {TTI::SK_Reverse, MVT::v32i8, 4},  // vextractf128 + 2*pshufb
                                       // + vinsertf128

    {TTI::SK_Select, MVT::v4i64, 1},  // vblendpd
    {TTI::SK_Select, MVT::v4f64, 1},  // vblendpd
    {TTI::SK_Select, MVT::v8i32, 1},  // vblendps
    {TTI::SK_Select, MVT::v8f32, 1},  // vblendps
    {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor
    {TTI::SK_Select, MVT::v32i8, 3},  // vpand + vpandn + vpor

    {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2},  // vperm2f128 + vshufpd
    {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2},  // vperm2f128 + vshufpd
    {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4},  // 2*vperm2f128 + 2*vshufps
    {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4},  // 2*vperm2f128 + 2*vshufps
    {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb
                                                // + 2*por + vinsertf128
    {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8},  // vextractf128 + 4*pshufb
                                                // + 2*por + vinsertf128

    {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3},   // 2*vperm2f128 + vshufpd
    {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3},   // 2*vperm2f128 + vshufpd
    {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4},   // 2*vperm2f128 + 2*vshufps
    {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4},   // 2*vperm2f128 + 2*vshufps
    {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb
                                              // + 4*por + vinsertf128
    {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15},  // 2*vextractf128 + 8*pshufb
                                              // + 4*por + vinsertf128
};

if (ST->hasAVX())
  if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second))
    return LT.first * Entry->Cost;

static const CostTblEntry SSE41ShuffleTbl[] = {
    {TTI::SK_Select, MVT::v2i64, 1}, // pblendw
    {TTI::SK_Select, MVT::v2f64, 1}, // movsd
    {TTI::SK_Select, MVT::v4i32, 1}, // pblendw
    {TTI::SK_Select, MVT::v4f32, 1}, // blendps
    {TTI::SK_Select, MVT::v8i16, 1}, // pblendw
    {TTI::SK_Select, MVT::v16i8, 1}  // pblendvb
};

if (ST->hasSSE41())
  if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second))
    return LT.first * Entry->Cost;

static const CostTblEntry SSSE3ShuffleTbl[] = {
    {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb
    {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb

    {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb
    {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb

    {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por
    {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por

    {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb
    {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb

    {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por
    {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por
};

if (ST->hasSSSE3())
  if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second))
    return LT.first * Entry->Cost;

static const CostTblEntry SSE2ShuffleTbl[] = {
    {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd
    {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd
    {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd
    {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd
    {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd

    {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd
    {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd
    {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd
    {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd
    {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw
                                      // + 2*pshufd + 2*unpck + packus

    {TTI::SK_Select, MVT::v2i64, 1}, // movsd
    {TTI::SK_Select, MVT::v2f64, 1}, // movsd
    {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps
    {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por
    {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por

    {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd
    {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd
    {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd
    {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw
                                                // + pshufd/unpck
  { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw
                                                // + 2*pshufd + 2*unpck + 2*packus

  { TTI::SK_PermuteTwoSrc,    MVT::v2f64,  1 }, // shufpd
  { TTI::SK_PermuteTwoSrc,    MVT::v2i64,  1 }, // shufpd
  { TTI::SK_PermuteTwoSrc,    MVT::v4i32,  2 }, // 2*{unpck,movsd,pshufd}
  { TTI::SK_PermuteTwoSrc,    MVT::v8i16,  8 }, // blend+permute
  { TTI::SK_PermuteTwoSrc,    MVT::v16i8, 13 }, // blend+permute
};

if (ST->hasSSE2())
  if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second))
    return LT.first * Entry->Cost;

static const CostTblEntry SSE1ShuffleTbl[] = {
  { TTI::SK_Broadcast,        MVT::v4f32, 1 }, // shufps
  { TTI::SK_Reverse,          MVT::v4f32, 1 }, // shufps
  { TTI::SK_Select,           MVT::v4f32, 2 }, // 2*shufps
  { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps
  { TTI::SK_PermuteTwoSrc,    MVT::v4f32, 2 }, // 2*shufps
};

if (ST->hasSSE1())
  if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second))
    return LT.first * Entry->Cost;

return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp);
1499}

1501InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
                                           Type *Src,
                                           TTI::CastContextHint CCH,
                                           TTI::TargetCostKind CostKind,
                                           const Instruction *I) {
int ISD = TLI->InstructionOpcodeToISD(Opcode);
assert(ISD && "Invalid opcode")((void)0);

// TODO: Allow non-throughput costs that aren't binary.
auto AdjustCost = [&CostKind](InstructionCost Cost) -> InstructionCost {
  if (CostKind != TTI::TCK_RecipThroughput)
    return Cost == 0 ? 0 : 1;
  return Cost;
};

// The cost tables include both specific, custom (non-legal) src/dst type
// conversions and generic, legalized types. We test for customs first, before
// falling back to legalization.
// FIXME: Need a better design of the cost table to handle non-simple types of
// potential massive combinations (elem_num x src_type x dst_type).
static const TypeConversionCostTblEntry AVX512BWConversionTbl[] {
  { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 },
  { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 },

  // Mask sign extend has an instruction.
  { ISD::SIGN_EXTEND, MVT::v2i8,   MVT::v2i1,  1 },
  { ISD::SIGN_EXTEND, MVT::v2i16,  MVT::v2i1,  1 },
  { ISD::SIGN_EXTEND, MVT::v4i8,   MVT::v4i1,  1 },
  { ISD::SIGN_EXTEND, MVT::v4i16,  MVT::v4i1,  1 },
  { ISD::SIGN_EXTEND, MVT::v8i8,   MVT::v8i1,  1 },
  { ISD::SIGN_EXTEND, MVT::v8i16,  MVT::v8i1,  1 },
  { ISD::SIGN_EXTEND, MVT::v16i8,  MVT::v16i1, 1 },
  { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 },
  { ISD::SIGN_EXTEND, MVT::v32i8,  MVT::v32i1, 1 },
  { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 },
  { ISD::SIGN_EXTEND, MVT::v64i8,  MVT::v64i1, 1 },

  // Mask zero extend is a sext + shift.
  { ISD::ZERO_EXTEND, MVT::v2i8,   MVT::v2i1,  2 },
  { ISD::ZERO_EXTEND, MVT::v2i16,  MVT::v2i1,  2 },
  { ISD::ZERO_EXTEND, MVT::v4i8,   MVT::v4i1,  2 },
  { ISD::ZERO_EXTEND, MVT::v4i16,  MVT::v4i1,  2 },
  { ISD::ZERO_EXTEND, MVT::v8i8,   MVT::v8i1,  2 },
  { ISD::ZERO_EXTEND, MVT::v8i16,  MVT::v8i1,  2 },
  { ISD::ZERO_EXTEND, MVT::v16i8,  MVT::v16i1, 2 },
  { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 },
  { ISD::ZERO_EXTEND, MVT::v32i8,  MVT::v32i1, 2 },
  { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 },
  { ISD::ZERO_EXTEND, MVT::v64i8,  MVT::v64i1, 2 },

  { ISD::TRUNCATE,    MVT::v32i8,  MVT::v32i16, 2 },
  { ISD::TRUNCATE,    MVT::v16i8,  MVT::v16i16, 2 }, // widen to zmm
  { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i8,   2 }, // widen to zmm
  { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i16,  2 }, // widen to zmm
  { ISD::TRUNCATE,    MVT::v2i8,   MVT::v2i16,  2 }, // vpmovwb
  { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i8,   2 }, // widen to zmm
  { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i16,  2 }, // widen to zmm
  { ISD::TRUNCATE,    MVT::v4i8,   MVT::v4i16,  2 }, // vpmovwb
  { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i8,   2 }, // widen to zmm
  { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i16,  2 }, // widen to zmm
  { ISD::TRUNCATE,    MVT::v8i8,   MVT::v8i16,  2 }, // vpmovwb
  { ISD::TRUNCATE,    MVT::v16i1,  MVT::v16i8,  2 }, // widen to zmm
  { ISD::TRUNCATE,    MVT::v16i1,  MVT::v16i16, 2 }, // widen to zmm
  { ISD::TRUNCATE,    MVT::v32i1,  MVT::v32i8,  2 }, // widen to zmm
  { ISD::TRUNCATE,    MVT::v32i1,  MVT::v32i16, 2 },
  { ISD::TRUNCATE,    MVT::v64i1,  MVT::v64i8,  2 },
};

static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = {
  { ISD::SINT_TO_FP,  MVT::v8f32,  MVT::v8i64,  1 },
  { ISD::SINT_TO_FP,  MVT::v8f64,  MVT::v8i64,  1 },

  { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i64,  1 },
  { ISD::UINT_TO_FP,  MVT::v8f64,  MVT::v8i64,  1 },

  { ISD::FP_TO_SINT,  MVT::v8i64,  MVT::v8f32,  1 },
  { ISD::FP_TO_SINT,  MVT::v8i64,  MVT::v8f64,  1 },

  { ISD::FP_TO_UINT,  MVT::v8i64,  MVT::v8f32,  1 },
  { ISD::FP_TO_UINT,  MVT::v8i64,  MVT::v8f64,  1 },
};

// TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and
// 256-bit wide vectors.

static const TypeConversionCostTblEntry AVX512FConversionTbl[] = {
  { ISD::FP_EXTEND, MVT::v8f64,   MVT::v8f32,  1 },
  { ISD::FP_EXTEND, MVT::v8f64,   MVT::v16f32, 3 },
  { ISD::FP_ROUND,  MVT::v8f32,   MVT::v8f64,  1 },

  { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i8,   3 }, // sext+vpslld+vptestmd
  { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i8,   3 }, // sext+vpslld+vptestmd
  { ISD::TRUNCATE,  MVT::v8i1,    MVT::v8i8,   3 }, // sext+vpslld+vptestmd
  { ISD::TRUNCATE,  MVT::v16i1,   MVT::v16i8,  3 }, // sext+vpslld+vptestmd
  { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i16,  3 }, // sext+vpsllq+vptestmq
  { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i16,  3 }, // sext+vpsllq+vptestmq
  { ISD::TRUNCATE,  MVT::v8i1,    MVT::v8i16,  3 }, // sext+vpsllq+vptestmq
  { ISD::TRUNCATE,  MVT::v16i1,   MVT::v16i16, 3 }, // sext+vpslld+vptestmd
  { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i32,  2 }, // zmm vpslld+vptestmd
  { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i32,  2 }, // zmm vpslld+vptestmd
  { ISD::TRUNCATE,  MVT::v8i1,    MVT::v8i32,  2 }, // zmm vpslld+vptestmd
  { ISD::TRUNCATE,  MVT::v16i1,   MVT::v16i32, 2 }, // vpslld+vptestmd
  { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i64,  2 }, // zmm vpsllq+vptestmq
  { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i64,  2 }, // zmm vpsllq+vptestmq
  { ISD::TRUNCATE,  MVT::v8i1,    MVT::v8i64,  2 }, // vpsllq+vptestmq
  { ISD::TRUNCATE,  MVT::v2i8,    MVT::v2i32,  2 }, // vpmovdb
  { ISD::TRUNCATE,  MVT::v4i8,    MVT::v4i32,  2 }, // vpmovdb
  { ISD::TRUNCATE,  MVT::v16i8,   MVT::v16i32, 2 }, // vpmovdb
  { ISD::TRUNCATE,  MVT::v16i16,  MVT::v16i32, 2 }, // vpmovdb
  { ISD::TRUNCATE,  MVT::v2i8,    MVT::v2i64,  2 }, // vpmovqb
  { ISD::TRUNCATE,  MVT::v2i16,   MVT::v2i64,  1 }, // vpshufb
  { ISD::TRUNCATE,  MVT::v8i8,    MVT::v8i64,  2 }, // vpmovqb
  { ISD::TRUNCATE,  MVT::v8i16,   MVT::v8i64,  2 }, // vpmovqw
  { ISD::TRUNCATE,  MVT::v8i32,   MVT::v8i64,  1 }, // vpmovqd
  { ISD::TRUNCATE,  MVT::v4i32,   MVT::v4i64,  1 }, // zmm vpmovqd
  { ISD::TRUNCATE,  MVT::v16i8,   MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb

  { ISD::TRUNCATE,  MVT::v16i8,  MVT::v16i16,  3 }, // extend to v16i32
  { ISD::TRUNCATE,  MVT::v32i8,  MVT::v32i16,  8 },

  // Sign extend is zmm vpternlogd+vptruncdb.
  // Zero extend is zmm broadcast load+vptruncdw.
  { ISD::SIGN_EXTEND, MVT::v2i8,   MVT::v2i1,   3 },
  { ISD::ZERO_EXTEND, MVT::v2i8,   MVT::v2i1,   4 },
  { ISD::SIGN_EXTEND, MVT::v4i8,   MVT::v4i1,   3 },
  { ISD::ZERO_EXTEND, MVT::v4i8,   MVT::v4i1,   4 },
  { ISD::SIGN_EXTEND, MVT::v8i8,   MVT::v8i1,   3 },
  { ISD::ZERO_EXTEND, MVT::v8i8,   MVT::v8i1,   4 },
  { ISD::SIGN_EXTEND, MVT::v16i8,  MVT::v16i1,  3 },
  { ISD::ZERO_EXTEND, MVT::v16i8,  MVT::v16i1,  4 },

  // Sign extend is zmm vpternlogd+vptruncdw.
  // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw.
  { ISD::SIGN_EXTEND, MVT::v2i16,  MVT::v2i1,   3 },
  { ISD::ZERO_EXTEND, MVT::v2i16,  MVT::v2i1,   4 },
  { ISD::SIGN_EXTEND, MVT::v4i16,  MVT::v4i1,   3 },
  { ISD::ZERO_EXTEND, MVT::v4i16,  MVT::v4i1,   4 },
  { ISD::SIGN_EXTEND, MVT::v8i16,  MVT::v8i1,   3 },
  { ISD::ZERO_EXTEND, MVT::v8i16,  MVT::v8i1,   4 },
  { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1,  3 },
  { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1,  4 },

  { ISD::SIGN_EXTEND, MVT::v2i32,  MVT::v2i1,   1 }, // zmm vpternlogd
  { ISD::ZERO_EXTEND, MVT::v2i32,  MVT::v2i1,   2 }, // zmm vpternlogd+psrld
  { ISD::SIGN_EXTEND, MVT::v4i32,  MVT::v4i1,   1 }, // zmm vpternlogd
  { ISD::ZERO_EXTEND, MVT::v4i32,  MVT::v4i1,   2 }, // zmm vpternlogd+psrld
  { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i1,   1 }, // zmm vpternlogd
  { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i1,   2 }, // zmm vpternlogd+psrld
  { ISD::SIGN_EXTEND, MVT::v2i64,  MVT::v2i1,   1 }, // zmm vpternlogq
  { ISD::ZERO_EXTEND, MVT::v2i64,  MVT::v2i1,   2 }, // zmm vpternlogq+psrlq
  { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i1,   1 }, // zmm vpternlogq
  { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i1,   2 }, // zmm vpternlogq+psrlq

  { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1,  1 }, // vpternlogd
  { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1,  2 }, // vpternlogd+psrld
  { ISD::SIGN_EXTEND, MVT::v8i64,  MVT::v8i1,   1 }, // vpternlogq
  { ISD::ZERO_EXTEND, MVT::v8i64,  MVT::v8i1,   2 }, // vpternlogq+psrlq

  { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8,  1 },
  { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8,  1 },
  { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
  { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
  { ISD::SIGN_EXTEND, MVT::v8i64,  MVT::v8i8,   1 },
  { ISD::ZERO_EXTEND, MVT::v8i64,  MVT::v8i8,   1 },
  { ISD::SIGN_EXTEND, MVT::v8i64,  MVT::v8i16,  1 },
  { ISD::ZERO_EXTEND, MVT::v8i64,  MVT::v8i16,  1 },
  { ISD::SIGN_EXTEND, MVT::v8i64,  MVT::v8i32,  1 },
  { ISD::ZERO_EXTEND, MVT::v8i64,  MVT::v8i32,  1 },

  { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8,  3 }, // FIXME: May not be right
  { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8,  3 }, // FIXME: May not be right

  { ISD::SINT_TO_FP,  MVT::v8f64,  MVT::v8i1,   4 },
  { ISD::SINT_TO_FP,  MVT::v16f32, MVT::v16i1,  3 },
  { ISD::SINT_TO_FP,  MVT::v8f64,  MVT::v16i8,  2 },
  { ISD::SINT_TO_FP,  MVT::v16f32, MVT::v16i8,  1 },
  { ISD::SINT_TO_FP,  MVT::v8f64,  MVT::v8i16,  2 },
  { ISD::SINT_TO_FP,  MVT::v16f32, MVT::v16i16, 1 },
  { ISD::SINT_TO_FP,  MVT::v8f64,  MVT::v8i32,  1 },
  { ISD::SINT_TO_FP,  MVT::v16f32, MVT::v16i32, 1 },

  { ISD::UINT_TO_FP,  MVT::v8f64,  MVT::v8i1,   4 },
  { ISD::UINT_TO_FP,  MVT::v16f32, MVT::v16i1,  3 },
  { ISD::UINT_TO_FP,  MVT::v8f64,  MVT::v16i8,  2 },
  { ISD::UINT_TO_FP,  MVT::v16f32, MVT::v16i8,  1 },
  { ISD::UINT_TO_FP,  MVT::v8f64,  MVT::v8i16,  2 },
  { ISD::UINT_TO_FP,  MVT::v16f32, MVT::v16i16, 1 },
  { ISD::UINT_TO_FP,  MVT::v8f64,  MVT::v8i32,  1 },
  { ISD::UINT_TO_FP,  MVT::v16f32, MVT::v16i32, 1 },
  { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i64, 26 },
  { ISD::UINT_TO_FP,  MVT::v8f64,  MVT::v8i64,  5 },

  { ISD::FP_TO_SINT,  MVT::v16i8,  MVT::v16f32, 2 },
  { ISD::FP_TO_SINT,  MVT::v16i8,  MVT::v16f64, 7 },
  { ISD::FP_TO_SINT,  MVT::v32i8,  MVT::v32f64,15 },
  { ISD::FP_TO_SINT,  MVT::v64i8,  MVT::v64f32,11 },
  { ISD::FP_TO_SINT,  MVT::v64i8,  MVT::v64f64,31 },
  { ISD::FP_TO_SINT,  MVT::v8i16,  MVT::v8f64,  3 },
  { ISD::FP_TO_SINT,  MVT::v16i16, MVT::v16f64, 7 },
  { ISD::FP_TO_SINT,  MVT::v32i16, MVT::v32f32, 5 },
  { ISD::FP_TO_SINT,  MVT::v32i16, MVT::v32f64,15 },
  { ISD::FP_TO_SINT,  MVT::v8i32,  MVT::v8f64,  1 },
  { ISD::FP_TO_SINT,  MVT::v16i32, MVT::v16f64, 3 },

  { ISD::FP_TO_UINT,  MVT::v8i32,  MVT::v8f64,  1 },
  { ISD::FP_TO_UINT,  MVT::v8i16,  MVT::v8f64,  3 },
  { ISD::FP_TO_UINT,  MVT::v8i8,   MVT::v8f64,  3 },
  { ISD::FP_TO_UINT,  MVT::v16i32, MVT::v16f32, 1 },
  { ISD::FP_TO_UINT,  MVT::v16i16, MVT::v16f32, 3 },
  { ISD::FP_TO_UINT,  MVT::v16i8,  MVT::v16f32, 3 },
};

static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] {
  // Mask sign extend has an instruction.
  { ISD::SIGN_EXTEND, MVT::v2i8,   MVT::v2i1,  1 },
  { ISD::SIGN_EXTEND, MVT::v2i16,  MVT::v2i1,  1 },
  { ISD::SIGN_EXTEND, MVT::v4i8,   MVT::v4i1,  1 },
  { ISD::SIGN_EXTEND, MVT::v4i16,  MVT::v4i1,  1 },
  { ISD::SIGN_EXTEND, MVT::v8i8,   MVT::v8i1,  1 },
  { ISD::SIGN_EXTEND, MVT::v8i16,  MVT::v8i1,  1 },
  { ISD::SIGN_EXTEND, MVT::v16i8,  MVT::v16i1, 1 },
  { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 },
  { ISD::SIGN_EXTEND, MVT::v32i8,  MVT::v32i1, 1 },

  // Mask zero extend is a sext + shift.
  { ISD::ZERO_EXTEND, MVT::v2i8,   MVT::v2i1,  2 },
  { ISD::ZERO_EXTEND, MVT::v2i16,  MVT::v2i1,  2 },
  { ISD::ZERO_EXTEND, MVT::v4i8,   MVT::v4i1,  2 },
  { ISD::ZERO_EXTEND, MVT::v4i16,  MVT::v4i1,  2 },
  { ISD::ZERO_EXTEND, MVT::v8i8,   MVT::v8i1,  2 },
  { ISD::ZERO_EXTEND, MVT::v8i16,  MVT::v8i1,  2 },
  { ISD::ZERO_EXTEND, MVT::v16i8,  MVT::v16i1, 2 },
  { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 },
  { ISD::ZERO_EXTEND, MVT::v32i8,  MVT::v32i1, 2 },

  { ISD::TRUNCATE,    MVT::v16i8,  MVT::v16i16, 2 },
  { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i8,   2 }, // vpsllw+vptestmb
  { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i16,  2 }, // vpsllw+vptestmw
  { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i8,   2 }, // vpsllw+vptestmb
  { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i16,  2 }, // vpsllw+vptestmw
  { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i8,   2 }, // vpsllw+vptestmb
  { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i16,  2 }, // vpsllw+vptestmw
  { ISD::TRUNCATE,    MVT::v16i1,  MVT::v16i8,  2 }, // vpsllw+vptestmb
  { ISD::TRUNCATE,    MVT::v16i1,  MVT::v16i16, 2 }, // vpsllw+vptestmw
  { ISD::TRUNCATE,    MVT::v32i1,  MVT::v32i8,  2 }, // vpsllw+vptestmb
};

static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = {
  { ISD::SINT_TO_FP,  MVT::v2f32,  MVT::v2i64,  1 },
  { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v2i64,  1 },
  { ISD::SINT_TO_FP,  MVT::v4f32,  MVT::v4i64,  1 },
  { ISD::SINT_TO_FP,  MVT::v4f64,  MVT::v4i64,  1 },

  { ISD::UINT_TO_FP,  MVT::v2f32,  MVT::v2i64,  1 },
  { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v2i64,  1 },
  { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v4i64,  1 },
  { ISD::UINT_TO_FP,  MVT::v4f64,  MVT::v4i64,  1 },

  { ISD::FP_TO_SINT,  MVT::v2i64,  MVT::v4f32,  1 },
  { ISD::FP_TO_SINT,  MVT::v4i64,  MVT::v4f32,  1 },
  { ISD::FP_TO_SINT,  MVT::v2i64,  MVT::v2f64,  1 },
  { ISD::FP_TO_SINT,  MVT::v4i64,  MVT::v4f64,  1 },

  { ISD::FP_TO_UINT,  MVT::v2i64,  MVT::v4f32,  1 },
  { ISD::FP_TO_UINT,  MVT::v4i64,  MVT::v4f32,  1 },
  { ISD::FP_TO_UINT,  MVT::v2i64,  MVT::v2f64,  1 },
  { ISD::FP_TO_UINT,  MVT::v4i64,  MVT::v4f64,  1 },
};

static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = {
  { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i8,   3 }, // sext+vpslld+vptestmd
  { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i8,   3 }, // sext+vpslld+vptestmd
  { ISD::TRUNCATE,  MVT::v8i1,    MVT::v8i8,   3 }, // sext+vpslld+vptestmd
  { ISD::TRUNCATE,  MVT::v16i1,   MVT::v16i8,  8 }, // split+2*v8i8
  { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i16,  3 }, // sext+vpsllq+vptestmq
  { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i16,  3 }, // sext+vpsllq+vptestmq
  { ISD::TRUNCATE,  MVT::v8i1,    MVT::v8i16,  3 }, // sext+vpsllq+vptestmq
  { ISD::TRUNCATE,  MVT::v16i1,   MVT::v16i16, 8 }, // split+2*v8i16
  { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i32,  2 }, // vpslld+vptestmd
  { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i32,  2 }, // vpslld+vptestmd
  { ISD::TRUNCATE,  MVT::v8i1,    MVT::v8i32,  2 }, // vpslld+vptestmd
  { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i64,  2 }, // vpsllq+vptestmq
  { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i64,  2 }, // vpsllq+vptestmq
  { ISD::TRUNCATE,  MVT::v4i32,   MVT::v4i64,  1 }, // vpmovqd
  { ISD::TRUNCATE,  MVT::v4i8,    MVT::v4i64,  2 }, // vpmovqb
  { ISD::TRUNCATE,  MVT::v4i16,   MVT::v4i64,  2 }, // vpmovqw
  { ISD::TRUNCATE,  MVT::v8i8,    MVT::v8i32,  2 }, // vpmovwb

  // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb
  // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb
  { ISD::SIGN_EXTEND, MVT::v2i8,   MVT::v2i1,   5 },
  { ISD::ZERO_EXTEND, MVT::v2i8,   MVT::v2i1,   6 },
  { ISD::SIGN_EXTEND, MVT::v4i8,   MVT::v4i1,   5 },
  { ISD::ZERO_EXTEND, MVT::v4i8,   MVT::v4i1,   6 },
  { ISD::SIGN_EXTEND, MVT::v8i8,   MVT::v8i1,   5 },
  { ISD::ZERO_EXTEND, MVT::v8i8,   MVT::v8i1,   6 },
  { ISD::SIGN_EXTEND, MVT::v16i8,  MVT::v16i1, 10 },
  { ISD::ZERO_EXTEND, MVT::v16i8,  MVT::v16i1, 12 },

  // sign extend is vpcmpeq+maskedmove+vpmovdw
  // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw
  { ISD::SIGN_EXTEND, MVT::v2i16,  MVT::v2i1,   4 },
  { ISD::ZERO_EXTEND, MVT::v2i16,  MVT::v2i1,   5 },
  { ISD::SIGN_EXTEND, MVT::v4i16,  MVT::v4i1,   4 },
  { ISD::ZERO_EXTEND, MVT::v4i16,  MVT::v4i1,   5 },
  { ISD::SIGN_EXTEND, MVT::v8i16,  MVT::v8i1,   4 },
  { ISD::ZERO_EXTEND, MVT::v8i16,  MVT::v8i1,   5 },
  { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 },
  { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 },

  { ISD::SIGN_EXTEND, MVT::v2i32,  MVT::v2i1,   1 }, // vpternlogd
  { ISD::ZERO_EXTEND, MVT::v2i32,  MVT::v2i1,   2 }, // vpternlogd+psrld
  { ISD::SIGN_EXTEND, MVT::v4i32,  MVT::v4i1,   1 }, // vpternlogd
  { ISD::ZERO_EXTEND, MVT::v4i32,  MVT::v4i1,   2 }, // vpternlogd+psrld
  { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i1,   1 }, // vpternlogd
  { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i1,   2 }, // vpternlogd+psrld
  { ISD::SIGN_EXTEND, MVT::v2i64,  MVT::v2i1,   1 }, // vpternlogq
  { ISD::ZERO_EXTEND, MVT::v2i64,  MVT::v2i1,   2 }, // vpternlogq+psrlq
  { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i1,   1 }, // vpternlogq
  { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i1,   2 }, // vpternlogq+psrlq

  { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v16i8,  1 },
  { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v16i8,  1 },
  { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v16i8,  1 },
  { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v16i8,  1 },
  { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8,  1 },
  { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8,  1 },
  { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v8i16,  1 },
  { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v8i16,  1 },
  { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i16,  1 },
  { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i16,  1 },
  { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i32,  1 },
  { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i32,  1 },

  { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v16i8,  1 },
  { ISD::SINT_TO_FP,  MVT::v8f32,  MVT::v16i8,  1 },
  { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v8i16,  1 },
  { ISD::SINT_TO_FP,  MVT::v8f32,  MVT::v8i16,  1 },

  { ISD::UINT_TO_FP,  MVT::f32,    MVT::i64,    1 },
  { ISD::UINT_TO_FP,  MVT::f64,    MVT::i64,    1 },
  { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v16i8,  1 },
  { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v16i8,  1 },
  { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v8i16,  1 },
  { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i16,  1 },
  { ISD::UINT_TO_FP,  MVT::v2f32,  MVT::v2i32,  1 },
  { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v4i32,  1 },
  { ISD::UINT_TO_FP,  MVT::v4f64,  MVT::v4i32,  1 },
  { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i32,  1 },
  { ISD::UINT_TO_FP,  MVT::v2f32,  MVT::v2i64,  5 },
  { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v2i64,  5 },
  { ISD::UINT_TO_FP,  MVT::v4f64,  MVT::v4i64,  5 },

  { ISD::FP_TO_SINT,  MVT::v16i8,  MVT::v8f32,  2 },
  { ISD::FP_TO_SINT,  MVT::v16i8,  MVT::v16f32, 2 },
  { ISD::FP_TO_SINT,  MVT::v32i8,  MVT::v32f32, 5 },

  { ISD::FP_TO_UINT,  MVT::i64,    MVT::f32,    1 },
  { ISD::FP_TO_UINT,  MVT::i64,    MVT::f64,    1 },
  { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v4f32,  1 },
  { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v2f64,  1 },
  { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v4f64,  1 },
  { ISD::FP_TO_UINT,  MVT::v8i32,  MVT::v8f32,  1 },
  { ISD::FP_TO_UINT,  MVT::v8i32,  MVT::v8f64,  1 },
};

static const TypeConversionCostTblEntry AVX2ConversionTbl[] = {
  { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i1,   3 },
  { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i1,   3 },
  { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i1,   3 },
  { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i1,   3 },
  { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1,  1 },
  { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1,  1 },

  { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v16i8,  2 },
  { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v16i8,  2 },
  { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v16i8,  2 },
  { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v16i8,  2 },
  { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8,  2 },
  { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8,  2 },
  { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v8i16,  2 },
  { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v8i16,  2 },
  { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i16,  2 },
  { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i16,  2 },
  { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 },
  { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 },
  { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i32,  2 },
  { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i32,  2 },

  { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i32,  2 },

  { ISD::TRUNCATE,    MVT::v16i8,  MVT::v8i16,  1 },
  { ISD::TRUNCATE,    MVT::v16i8,  MVT::v4i32,  1 },
  { ISD::TRUNCATE,    MVT::v16i8,  MVT::v2i64,  1 },
  { ISD::TRUNCATE,    MVT::v16i8,  MVT::v8i32,  4 },
  { ISD::TRUNCATE,    MVT::v16i8,  MVT::v4i64,  4 },
  { ISD::TRUNCATE,    MVT::v8i16,  MVT::v4i32,  1 },
  { ISD::TRUNCATE,    MVT::v8i16,  MVT::v2i64,  1 },
  { ISD::TRUNCATE,    MVT::v8i16,  MVT::v4i64,  5 },
  { ISD::TRUNCATE,    MVT::v4i32,  MVT::v4i64,  1 },
  { ISD::TRUNCATE,    MVT::v8i16,  MVT::v8i32,  2 },

  { ISD::FP_EXTEND,   MVT::v8f64,  MVT::v8f32,  3 },
  { ISD::FP_ROUND,    MVT::v8f32,  MVT::v8f64,  3 },

  { ISD::FP_TO_SINT,  MVT::v16i16, MVT::v8f32,  1 },
  { ISD::FP_TO_SINT,  MVT::v4i32,  MVT::v4f64,  1 },
  { ISD::FP_TO_SINT,  MVT::v8i32,  MVT::v8f32,  1 },
  { ISD::FP_TO_SINT,  MVT::v8i32,  MVT::v8f64,  3 },

  { ISD::FP_TO_UINT,  MVT::i64,    MVT::f32,    3 },
  { ISD::FP_TO_UINT,  MVT::i64,    MVT::f64,    3 },
  { ISD::FP_TO_UINT,  MVT::v16i16, MVT::v8f32,  1 },
  { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v4f32,  3 },
  { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v2f64,  4 },
  { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v4f64,  4 },
  { ISD::FP_TO_UINT,  MVT::v8i32,  MVT::v8f32,  3 },
  { ISD::FP_TO_UINT,  MVT::v8i32,  MVT::v4f64,  4 },

  { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v16i8,  2 },
  { ISD::SINT_TO_FP,  MVT::v8f32,  MVT::v16i8,  2 },
  { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v8i16,  2 },
  { ISD::SINT_TO_FP,  MVT::v8f32,  MVT::v8i16,  2 },
  { ISD::SINT_TO_FP,  MVT::v4f64,  MVT::v4i32,  1 },
  { ISD::SINT_TO_FP,  MVT::v8f32,  MVT::v8i32,  1 },
  { ISD::SINT_TO_FP,  MVT::v8f64,  MVT::v8i32,  3 },

  { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v16i8,  2 },
  { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v16i8,  2 },
  { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v8i16,  2 },
  { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i16,  2 },
  { ISD::UINT_TO_FP,  MVT::v2f32,  MVT::v2i32,  2 },
  { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v2i32,  1 },
  { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v4i32,  2 },
  { ISD::UINT_TO_FP,  MVT::v4f64,  MVT::v4i32,  2 },
  { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i32,  2 },
  { ISD::UINT_TO_FP,  MVT::v8f64,  MVT::v8i32,  4 },
};

static const TypeConversionCostTblEntry AVXConversionTbl[] = {
  { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i1,   6 },
  { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i1,   4 },
  { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i1,   7 },
  { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i1,   4 },
  { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1,  4 },
  { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1,  4 },

  { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v16i8,  3 },
  { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v16i8,  3 },
  { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v16i8,  3 },
  { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v16i8,  3 },
  { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8,  3 },
  { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8,  3 },
  { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v8i16,  3 },
  { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v8i16,  3 },
  { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i16,  3 },
  { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i16,  3 },
  { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i32,  3 },
  { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i32,  3 },

  { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i64,  4 },
  { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i32,  5 },
  { ISD::TRUNCATE,    MVT::v16i1,  MVT::v16i16, 4 },
  { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i64,  9 },
  { ISD::TRUNCATE,    MVT::v16i1,  MVT::v16i64, 11 },

  { ISD::TRUNCATE,    MVT::v16i8,  MVT::v16i16, 2 }, // and+extract+packuswb
  { ISD::TRUNCATE,    MVT::v16i8,  MVT::v8i32,  5 },
  { ISD::TRUNCATE,    MVT::v8i16,  MVT::v8i32,  5 },
  { ISD::TRUNCATE,    MVT::v16i8,  MVT::v4i64,  5 },
  { ISD::TRUNCATE,    MVT::v8i16,  MVT::v4i64,  3 }, // and+extract+2*packusdw
  { ISD::TRUNCATE,    MVT::v4i32,  MVT::v4i64,  2 },

  { ISD::SINT_TO_FP,  MVT::v4f32,  MVT::v4i1,   3 },
  { ISD::SINT_TO_FP,  MVT::v4f64,  MVT::v4i1,   3 },
  { ISD::SINT_TO_FP,  MVT::v8f32,  MVT::v8i1,   8 },
  { ISD::SINT_TO_FP,  MVT::v8f32,  MVT::v16i8,  4 },
  { ISD::SINT_TO_FP,  MVT::v4f64,  MVT::v16i8,  2 },
  { ISD::SINT_TO_FP,  MVT::v8f32,  MVT::v8i16,  4 },
  { ISD::SINT_TO_FP,  MVT::v4f64,  MVT::v8i16,  2 },
  { ISD::SINT_TO_FP,  MVT::v4f64,  MVT::v4i32,  2 },
  { ISD::SINT_TO_FP,  MVT::v8f32,  MVT::v8i32,  2 },
  { ISD::SINT_TO_FP,  MVT::v8f64,  MVT::v8i32,  4 },
  { ISD::SINT_TO_FP,  MVT::v4f32,  MVT::v2i64,  5 },
  { ISD::SINT_TO_FP,  MVT::v4f32,  MVT::v4i64,  8 },

  { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v4i1,   7 },
  { ISD::UINT_TO_FP,  MVT::v4f64,  MVT::v4i1,   7 },
  { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i1,   6 },
  { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v16i8,  4 },
  { ISD::UINT_TO_FP,  MVT::v4f64,  MVT::v16i8,  2 },
  { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i16,  4 },
  { ISD::UINT_TO_FP,  MVT::v4f64,  MVT::v8i16,  2 },
  { ISD::UINT_TO_FP,  MVT::v2f32,  MVT::v2i32,  4 },
  { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v2i32,  4 },
  { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v4i32,  5 },
  { ISD::UINT_TO_FP,  MVT::v4f64,  MVT::v4i32,  6 },
  { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i32,  8 },
  { ISD::UINT_TO_FP,  MVT::v8f64,  MVT::v8i32, 10 },
  { ISD::UINT_TO_FP,  MVT::v2f32,  MVT::v2i64, 10 },
  { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v4i64, 18 },
  { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v2i64,  5 },
  { ISD::UINT_TO_FP,  MVT::v4f64,  MVT::v4i64, 10 },

  { ISD::FP_TO_SINT,  MVT::v16i8,  MVT::v8f32,  2 },
  { ISD::FP_TO_SINT,  MVT::v16i8,  MVT::v4f64,  2 },
  { ISD::FP_TO_SINT,  MVT::v32i8,  MVT::v8f32,  2 },
  { ISD::FP_TO_SINT,  MVT::v32i8,  MVT::v4f64,  2 },
  { ISD::FP_TO_SINT,  MVT::v8i16,  MVT::v8f32,  2 },
  { ISD::FP_TO_SINT,  MVT::v8i16,  MVT::v4f64,  2 },
  { ISD::FP_TO_SINT,  MVT::v16i16, MVT::v8f32,  2 },
  { ISD::FP_TO_SINT,  MVT::v16i16, MVT::v4f64,  2 },
  { ISD::FP_TO_SINT,  MVT::v4i32,  MVT::v4f64,  2 },
  { ISD::FP_TO_SINT,  MVT::v8i32,  MVT::v8f32,  2 },
  { ISD::FP_TO_SINT,  MVT::v8i32,  MVT::v8f64,  5 },

  { ISD::FP_TO_UINT,  MVT::v16i8,  MVT::v8f32,  2 },
  { ISD::FP_TO_UINT,  MVT::v16i8,  MVT::v4f64,  2 },
  { ISD::FP_TO_UINT,  MVT::v32i8,  MVT::v8f32,  2 },
  { ISD::FP_TO_UINT,  MVT::v32i8,  MVT::v4f64,  2 },
  { ISD::FP_TO_UINT,  MVT::v8i16,  MVT::v8f32,  2 },
  { ISD::FP_TO_UINT,  MVT::v8i16,  MVT::v4f64,  2 },
  { ISD::FP_TO_UINT,  MVT::v16i16, MVT::v8f32,  2 },
  { ISD::FP_TO_UINT,  MVT::v16i16, MVT::v4f64,  2 },
  { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v4f32,  3 },
  { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v2f64,  4 },
  { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v4f64,  6 },
  { ISD::FP_TO_UINT,  MVT::v8i32,  MVT::v8f32,  7 },
  { ISD::FP_TO_UINT,  MVT::v8i32,  MVT::v4f64,  7 },

  { ISD::FP_EXTEND,   MVT::v4f64,  MVT::v4f32,  1 },
  { ISD::FP_ROUND,    MVT::v4f32,  MVT::v4f64,  1 },
};

static const TypeConversionCostTblEntry SSE41ConversionTbl[] = {
  { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8,   1 },
  { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8,   1 },
  { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8,   1 },
  { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8,   1 },
  { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8,   1 },
  { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8,   1 },
  { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16,   1 },
  { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16,   1 },
  { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16,   1 },
  { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16,   1 },
  { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32,   1 },
  { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32,   1 },

  // These truncates end up widening elements.
  { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i8,   1 }, // PMOVXZBQ
  { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i16,  1 }, // PMOVXZWQ
  { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i8,   1 }, // PMOVXZBD

  { ISD::TRUNCATE,    MVT::v16i8,  MVT::v4i32,  2 },
  { ISD::TRUNCATE,    MVT::v8i16,  MVT::v4i32,  2 },
  { ISD::TRUNCATE,    MVT::v16i8,  MVT::v2i64,  2 },

  { ISD::SINT_TO_FP,  MVT::f32,    MVT::i32,    1 },
  { ISD::SINT_TO_FP,  MVT::f64,    MVT::i32,    1 },
  { ISD::SINT_TO_FP,  MVT::f32,    MVT::i64,    1 },
  { ISD::SINT_TO_FP,  MVT::f64,    MVT::i64,    1 },
  { ISD::SINT_TO_FP,  MVT::v4f32,  MVT::v16i8,  1 },
  { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v16i8,  1 },
  { ISD::SINT_TO_FP,  MVT::v4f32,  MVT::v8i16,  1 },
  { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v8i16,  1 },
  { ISD::SINT_TO_FP,  MVT::v4f32,  MVT::v4i32,  1 },
  { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v4i32,  1 },
  { ISD::SINT_TO_FP,  MVT::v4f64,  MVT::v4i32,  2 },

  { ISD::UINT_TO_FP,  MVT::f32,    MVT::i32,    1 },
  { ISD::UINT_TO_FP,  MVT::f64,    MVT::i32,    1 },
  { ISD::UINT_TO_FP,  MVT::f32,    MVT::i64,    4 },
  { ISD::UINT_TO_FP,  MVT::f64,    MVT::i64,    4 },
  { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v16i8,  1 },
  { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v16i8,  1 },
  { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v8i16,  1 },
  { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v8i16,  1 },
  { ISD::UINT_TO_FP,  MVT::v2f32,  MVT::v2i32,  3 },
  { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v4i32,  3 },
  { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v4i32,  2 },
  { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v2i64, 12 },
  { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v4i64, 22 },
  { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v2i64,  4 },

  { ISD::FP_TO_SINT,  MVT::i32,    MVT::f32,    1 },
  { ISD::FP_TO_SINT,  MVT::i64,    MVT::f32,    1 },
  { ISD::FP_TO_SINT,  MVT::i32,    MVT::f64,    1 },
  { ISD::FP_TO_SINT,  MVT::i64,    MVT::f64,    1 },
  { ISD::FP_TO_SINT,  MVT::v16i8,  MVT::v4f32,  2 },
  { ISD::FP_TO_SINT,  MVT::v16i8,  MVT::v2f64,  2 },
  { ISD::FP_TO_SINT,  MVT::v8i16,  MVT::v4f32,  1 },
  { ISD::FP_TO_SINT,  MVT::v8i16,  MVT::v2f64,  1 },
  { ISD::FP_TO_SINT,  MVT::v4i32,  MVT::v4f32,  1 },
  { ISD::FP_TO_SINT,  MVT::v4i32,  MVT::v2f64,  1 },

  { ISD::FP_TO_UINT,  MVT::i32,    MVT::f32,    1 },
  { ISD::FP_TO_UINT,  MVT::i64,    MVT::f32,    4 },
  { ISD::FP_TO_UINT,  MVT::i32,    MVT::f64,    1 },
  { ISD::FP_TO_UINT,  MVT::i64,    MVT::f64,    4 },
  { ISD::FP_TO_UINT,  MVT::v16i8,  MVT::v4f32,  2 },
  { ISD::FP_TO_UINT,  MVT::v16i8,  MVT::v2f64,  2 },
  { ISD::FP_TO_UINT,  MVT::v8i16,  MVT::v4f32,  1 },
  { ISD::FP_TO_UINT,  MVT::v8i16,  MVT::v2f64,  1 },
  { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v4f32,  4 },
  { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v2f64,  4 },
};

static const TypeConversionCostTblEntry SSE2ConversionTbl[] = {
  // These are somewhat magic numbers justified by comparing the
  // output of llvm-mca for our various supported scheduler models
  // and basing it off the worst case scenario.
  { ISD::SINT_TO_FP,  MVT::f32,    MVT::i32,    3 },
  { ISD::SINT_TO_FP,  MVT::f64,    MVT::i32,    3 },
  { ISD::SINT_TO_FP,  MVT::f32,    MVT::i64,    3 },
  { ISD::SINT_TO_FP,  MVT::f64,    MVT::i64,    3 },
  { ISD::SINT_TO_FP,  MVT::v4f32,  MVT::v16i8,  3 },
  { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v16i8,  4 },
  { ISD::SINT_TO_FP,  MVT::v4f32,  MVT::v8i16,  3 },
  { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v8i16,  4 },
  { ISD::SINT_TO_FP,  MVT::v4f32,  MVT::v4i32,  3 },
  { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v4i32,  4 },
  { ISD::SINT_TO_FP,  MVT::v4f32,  MVT::v2i64,  8 },
  { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v2i64,  8 },

  { ISD::UINT_TO_FP,  MVT::f32,    MVT::i32,    3 },
  { ISD::UINT_TO_FP,  MVT::f64,    MVT::i32,    3 },
  { ISD::UINT_TO_FP,  MVT::f32,    MVT::i64,    8 },
  { ISD::UINT_TO_FP,  MVT::f64,    MVT::i64,    9 },
  { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v16i8,  4 },
  { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v16i8,  4 },
  { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v8i16,  4 },
  { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v8i16,  4 },
  { ISD::UINT_TO_FP,  MVT::v2f32,  MVT::v2i32,  7 },
  { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v4i32,  7 },
  { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v4i32,  5 },
  { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v2i64, 15 },
  { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v2i64, 18 },

  { ISD::FP_TO_SINT,  MVT::i32,    MVT::f32,    4 },
  { ISD::FP_TO_SINT,  MVT::i64,    MVT::f32,    4 },
  { ISD::FP_TO_SINT,  MVT::i32,    MVT::f64,    4 },
  { ISD::FP_TO_SINT,  MVT::i64,    MVT::f64,    4 },
  { ISD::FP_TO_SINT,  MVT::v16i8,  MVT::v4f32,  6 },
  { ISD::FP_TO_SINT,  MVT::v16i8,  MVT::v2f64,  6 },
  { ISD::FP_TO_SINT,  MVT::v8i16,  MVT::v4f32,  5 },
  { ISD::FP_TO_SINT,  MVT::v8i16,  MVT::v2f64,  5 },
  { ISD::FP_TO_SINT,  MVT::v4i32,  MVT::v4f32,  4 },
  { ISD::FP_TO_SINT,  MVT::v4i32,  MVT::v2f64,  4 },

  { ISD::FP_TO_UINT,  MVT::i32,    MVT::f32,    4 },
  { ISD::FP_TO_UINT,  MVT::i64,    MVT::f32,    4 },
  { ISD::FP_TO_UINT,  MVT::i32,    MVT::f64,    4 },
  { ISD::FP_TO_UINT,  MVT::i64,    MVT::f64,   15 },
  { ISD::FP_TO_UINT,  MVT::v16i8,  MVT::v4f32,  6 },
  { ISD::FP_TO_UINT,  MVT::v16i8,  MVT::v2f64,  6 },
  { ISD::FP_TO_UINT,  MVT::v8i16,  MVT::v4f32,  5 },
  { ISD::FP_TO_UINT,  MVT::v8i16,  MVT::v2f64,  5 },
  { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v4f32,  8 },
  { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v2f64,  8 },

  { ISD::ZERO_EXTEND, MVT::v2i64,  MVT::v16i8,  4 },
  { ISD::SIGN_EXTEND, MVT::v2i64,  MVT::v16i8,  4 },
  { ISD::ZERO_EXTEND, MVT::v4i32,  MVT::v16i8,  2 },
  { ISD::SIGN_EXTEND, MVT::v4i32,  MVT::v16i8,  3 },
  { ISD::ZERO_EXTEND, MVT::v8i16,  MVT::v16i8,  1 },
  { ISD::SIGN_EXTEND, MVT::v8i16,  MVT::v16i8,  2 },
  { ISD::ZERO_EXTEND, MVT::v2i64,  MVT::v8i16,  2 },
  { ISD::SIGN_EXTEND, MVT::v2i64,  MVT::v8i16,  3 },
  { ISD::ZERO_EXTEND, MVT::v4i32,  MVT::v8i16,  1 },
  { ISD::SIGN_EXTEND, MVT::v4i32,  MVT::v8i16,  2 },
  { ISD::ZERO_EXTEND, MVT::v2i64,  MVT::v4i32,  1 },
  { ISD::SIGN_EXTEND, MVT::v2i64,  MVT::v4i32,  2 },

  // These truncates are really widening elements.
  { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i32,  1 }, // PSHUFD
  { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i16,  2 }, // PUNPCKLWD+DQ
  { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i8,   3 }, // PUNPCKLBW+WD+PSHUFD
  { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i16,  1 }, // PUNPCKLWD
  { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i8,   2 }, // PUNPCKLBW+WD
  { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i8,   1 }, // PUNPCKLBW

  { ISD::TRUNCATE,    MVT::v16i8,  MVT::v8i16,  2 }, // PAND+PACKUSWB
  { ISD::TRUNCATE,    MVT::v16i8,  MVT::v16i16, 3 },
  { ISD::TRUNCATE,    MVT::v16i8,  MVT::v4i32,  3 }, // PAND+2*PACKUSWB
  { ISD::TRUNCATE,    MVT::v16i8,  MVT::v16i32, 7 },
  { ISD::TRUNCATE,    MVT::v2i16,  MVT::v2i32,  1 },
  { ISD::TRUNCATE,    MVT::v8i16,  MVT::v4i32,  3 },
  { ISD::TRUNCATE,    MVT::v8i16,  MVT::v8i32,  5 },
  { ISD::TRUNCATE,    MVT::v16i16, MVT::v16i32,10 },
  { ISD::TRUNCATE,    MVT::v16i8,  MVT::v2i64,  4 }, // PAND+3*PACKUSWB
  { ISD::TRUNCATE,    MVT::v8i16,  MVT::v2i64,  2 }, // PSHUFD+PSHUFLW
  { ISD::TRUNCATE,    MVT::v4i32,  MVT::v2i64,  1 }, // PSHUFD
};

// Attempt to map directly to (simple) MVT types to let us match custom entries.
EVT SrcTy = TLI->getValueType(DL, Src);
EVT DstTy = TLI->getValueType(DL, Dst);

// The function getSimpleVT only handles simple value types.
if (SrcTy.isSimple() && DstTy.isSimple()) {
  MVT SimpleSrcTy = SrcTy.getSimpleVT();
  MVT SimpleDstTy = DstTy.getSimpleVT();

  if (ST->useAVX512Regs()) {
    if (ST->hasBWI())
      if (const auto *Entry = ConvertCostTableLookup(
              AVX512BWConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
        return AdjustCost(Entry->Cost);

    if (ST->hasDQI())
      if (const auto *Entry = ConvertCostTableLookup(
              AVX512DQConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
        return AdjustCost(Entry->Cost);

    if (ST->hasAVX512())
      if (const auto *Entry = ConvertCostTableLookup(
              AVX512FConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
        return AdjustCost(Entry->Cost);
  }

  if (ST->hasBWI())
    if (const auto *Entry = ConvertCostTableLookup(
            AVX512BWVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
      return AdjustCost(Entry->Cost);

  if (ST->hasDQI())
    if (const auto *Entry = ConvertCostTableLookup(
            AVX512DQVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
      return AdjustCost(Entry->Cost);

  if (ST->hasAVX512())
    if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD,
                                                   SimpleDstTy, SimpleSrcTy))
      return AdjustCost(Entry->Cost);

  if (ST->hasAVX2()) {
    if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD,
                                                   SimpleDstTy, SimpleSrcTy))
      return AdjustCost(Entry->Cost);
  }

  if (ST->hasAVX()) {
    if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD,
                                                   SimpleDstTy, SimpleSrcTy))
      return AdjustCost(Entry->Cost);
  }

  if (ST->hasSSE41()) {
    if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD,
                                                   SimpleDstTy, SimpleSrcTy))
      return AdjustCost(Entry->Cost);
  }

  if (ST->hasSSE2()) {
    if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD,
                                                   SimpleDstTy, SimpleSrcTy))
      return AdjustCost(Entry->Cost);
  }
}

// Fall back to legalized types.
std::pair<InstructionCost, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src);
std::pair<InstructionCost, MVT> LTDest =
    TLI->getTypeLegalizationCost(DL, Dst);

if (ST->useAVX512Regs()) {
  if (ST->hasBWI())
    if (const auto *Entry = ConvertCostTableLookup(
            AVX512BWConversionTbl, ISD, LTDest.second, LTSrc.second))
      return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);

  if (ST->hasDQI())
    if (const auto *Entry = ConvertCostTableLookup(
            AVX512DQConversionTbl, ISD, LTDest.second, LTSrc.second))
      return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);

  if (ST->hasAVX512())
    if (const auto *Entry = ConvertCostTableLookup(
            AVX512FConversionTbl, ISD, LTDest.second, LTSrc.second))
      return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);
}

if (ST->hasBWI())
  if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD,
                                                 LTDest.second, LTSrc.second))
    return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);

if (ST->hasDQI())
  if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD,
                                                 LTDest.second, LTSrc.second))
    return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);

if (ST->hasAVX512())
  if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD,
                                                 LTDest.second, LTSrc.second))
    return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);

if (ST->hasAVX2())
  if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD,
                                                 LTDest.second, LTSrc.second))
    return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);

if (ST->hasAVX())
  if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD,
                                                 LTDest.second, LTSrc.second))
    return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);

if (ST->hasSSE41())
  if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD,
                                                 LTDest.second, LTSrc.second))
    return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);

if (ST->hasSSE2())
  if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD,
                                                 LTDest.second, LTSrc.second))
    return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost);

// Fallback, for i8/i16 sitofp/uitofp cases we need to extend to i32 for
// sitofp.
if ((ISD == ISD::SINT_TO_FP || ISD == ISD::UINT_TO_FP) &&
    1 < Src->getScalarSizeInBits() && Src->getScalarSizeInBits() < 32) {
  Type *ExtSrc = Src->getWithNewBitWidth(32);
  unsigned ExtOpc =
      (ISD == ISD::SINT_TO_FP) ? Instruction::SExt : Instruction::ZExt;

  // For scalar loads the extend would be free.
  InstructionCost ExtCost = 0;
  if (!(Src->isIntegerTy() && I && isa<LoadInst>(I->getOperand(0))))
    ExtCost = getCastInstrCost(ExtOpc, ExtSrc, Src, CCH, CostKind);

  return ExtCost + getCastInstrCost(Instruction::SIToFP, Dst, ExtSrc,
                                    TTI::CastContextHint::None, CostKind);
}

// Fallback for fptosi/fptoui i8/i16 cases we need to truncate from fptosi
// i32.
if ((ISD == ISD::FP_TO_SINT || ISD == ISD::FP_TO_UINT) &&
    1 < Dst->getScalarSizeInBits() && Dst->getScalarSizeInBits() < 32) {
  Type *TruncDst = Dst->getWithNewBitWidth(32);
  return getCastInstrCost(Instruction::FPToSI, TruncDst, Src, CCH, CostKind) +
         getCastInstrCost(Instruction::Trunc, Dst, TruncDst,
                          TTI::CastContextHint::None, CostKind);
}

return AdjustCost(
    BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I));
2347}

2349InstructionCost X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
                                             Type *CondTy,
                                             CmpInst::Predicate VecPred,
                                             TTI::TargetCostKind CostKind,
                                             const Instruction *I) {
// TODO: Handle other cost kinds.
if (CostKind != TTI::TCK_RecipThroughput)
  return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind,
                                   I);

// Legalize the type.
std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);

MVT MTy = LT.second;

int ISD = TLI->InstructionOpcodeToISD(Opcode);
assert(ISD && "Invalid opcode")((void)0);

unsigned ExtraCost = 0;
if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) {
  // Some vector comparison predicates cost extra instructions.
  if (MTy.isVector() &&
      !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) ||
        (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) ||
        ST->hasBWI())) {
    switch (cast<CmpInst>(I)->getPredicate()) {
    case CmpInst::Predicate::ICMP_NE:
      // xor(cmpeq(x,y),-1)
      ExtraCost = 1;
      break;
    case CmpInst::Predicate::ICMP_SGE:
    case CmpInst::Predicate::ICMP_SLE:
      // xor(cmpgt(x,y),-1)
      ExtraCost = 1;
      break;
    case CmpInst::Predicate::ICMP_ULT:
    case CmpInst::Predicate::ICMP_UGT:
      // cmpgt(xor(x,signbit),xor(y,signbit))
      // xor(cmpeq(pmaxu(x,y),x),-1)
      ExtraCost = 2;
      break;
    case CmpInst::Predicate::ICMP_ULE:
    case CmpInst::Predicate::ICMP_UGE:
      if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) ||
          (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) {
        // cmpeq(psubus(x,y),0)
        // cmpeq(pminu(x,y),x)
        ExtraCost = 1;
      } else {
        // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1)
        ExtraCost = 3;
      }
      break;
    default:
      break;
    }
  }
}

static const CostTblEntry SLMCostTbl[] = {
  // slm pcmpeq/pcmpgt throughput is 2
  { ISD::SETCC,   MVT::v2i64,   2 },
};

static const CostTblEntry AVX512BWCostTbl[] = {
  { ISD::SETCC,   MVT::v32i16,  1 },
  { ISD::SETCC,   MVT::v64i8,   1 },

  { ISD::SELECT,  MVT::v32i16,  1 },
  { ISD::SELECT,  MVT::v64i8,   1 },
};

static const CostTblEntry AVX512CostTbl[] = {
  { ISD::SETCC,   MVT::v8i64,   1 },
  { ISD::SETCC,   MVT::v16i32,  1 },
  { ISD::SETCC,   MVT::v8f64,   1 },
  { ISD::SETCC,   MVT::v16f32,  1 },

  { ISD::SELECT,  MVT::v8i64,   1 },
  { ISD::SELECT,  MVT::v16i32,  1 },
  { ISD::SELECT,  MVT::v8f64,   1 },
  { ISD::SELECT,  MVT::v16f32,  1 },

  { ISD::SETCC,   MVT::v32i16,  2 }, // FIXME: should probably be 4
  { ISD::SETCC,   MVT::v64i8,   2 }, // FIXME: should probably be 4

  { ISD::SELECT,  MVT::v32i16,  2 }, // FIXME: should be 3
  { ISD::SELECT,  MVT::v64i8,   2 }, // FIXME: should be 3
};

static const CostTblEntry AVX2CostTbl[] = {
  { ISD::SETCC,   MVT::v4i64,   1 },
  { ISD::SETCC,   MVT::v8i32,   1 },
  { ISD::SETCC,   MVT::v16i16,  1 },
  { ISD::SETCC,   MVT::v32i8,   1 },

  { ISD::SELECT,  MVT::v4i64,   1 }, // pblendvb
  { ISD::SELECT,  MVT::v8i32,   1 }, // pblendvb
  { ISD::SELECT,  MVT::v16i16,  1 }, // pblendvb
  { ISD::SELECT,  MVT::v32i8,   1 }, // pblendvb
};

static const CostTblEntry AVX1CostTbl[] = {
  { ISD::SETCC,   MVT::v4f64,   1 },
  { ISD::SETCC,   MVT::v8f32,   1 },
  // AVX1 does not support 8-wide integer compare.
  { ISD::SETCC,   MVT::v4i64,   4 },
  { ISD::SETCC,   MVT::v8i32,   4 },
  { ISD::SETCC,   MVT::v16i16,  4 },
  { ISD::SETCC,   MVT::v32i8,   4 },

  { ISD::SELECT,  MVT::v4f64,   1 }, // vblendvpd
  { ISD::SELECT,  MVT::v8f32,   1 }, // vblendvps
  { ISD::SELECT,  MVT::v4i64,   1 }, // vblendvpd
  { ISD::SELECT,  MVT::v8i32,   1 }, // vblendvps
  { ISD::SELECT,  MVT::v16i16,  3 }, // vandps + vandnps + vorps
  { ISD::SELECT,  MVT::v32i8,   3 }, // vandps + vandnps + vorps
};

static const CostTblEntry SSE42CostTbl[] = {
  { ISD::SETCC,   MVT::v2f64,   1 },
  { ISD::SETCC,   MVT::v4f32,   1 },
  { ISD::SETCC,   MVT::v2i64,   1 },
};

static const CostTblEntry SSE41CostTbl[] = {
  { ISD::SELECT,  MVT::v2f64,   1 }, // blendvpd
  { ISD::SELECT,  MVT::v4f32,   1 }, // blendvps
  { ISD::SELECT,  MVT::v2i64,   1 }, // pblendvb
  { ISD::SELECT,  MVT::v4i32,   1 }, // pblendvb
  { ISD::SELECT,  MVT::v8i16,   1 }, // pblendvb
  { ISD::SELECT,  MVT::v16i8,   1 }, // pblendvb
};

static const CostTblEntry SSE2CostTbl[] = {
  { ISD::SETCC,   MVT::v2f64,   2 },
  { ISD::SETCC,   MVT::f64,     1 },
  { ISD::SETCC,   MVT::v2i64,   8 },
  { ISD::SETCC,   MVT::v4i32,   1 },
  { ISD::SETCC,   MVT::v8i16,   1 },
  { ISD::SETCC,   MVT::v16i8,   1 },

  { ISD::SELECT,  MVT::v2f64,   3 }, // andpd + andnpd + orpd
  { ISD::SELECT,  MVT::v2i64,   3 }, // pand + pandn + por
  { ISD::SELECT,  MVT::v4i32,   3 }, // pand + pandn + por
  { ISD::SELECT,  MVT::v8i16,   3 }, // pand + pandn + por
  { ISD::SELECT,  MVT::v16i8,   3 }, // pand + pandn + por
};

static const CostTblEntry SSE1CostTbl[] = {
  { ISD::SETCC,   MVT::v4f32,   2 },
  { ISD::SETCC,   MVT::f32,     1 },

  { ISD::SELECT,  MVT::v4f32,   3 }, // andps + andnps + orps
};

if (ST->isSLM())
  if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy))
    return LT.first * (ExtraCost + Entry->Cost);

if (ST->hasBWI())
  if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
    return LT.first * (ExtraCost + Entry->Cost);

if (ST->hasAVX512())
  if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
    return LT.first * (ExtraCost + Entry->Cost);

if (ST->hasAVX2())
  if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy))
    return LT.first * (ExtraCost + Entry->Cost);

if (ST->hasAVX())
  if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
    return LT.first * (ExtraCost + Entry->Cost);

if (ST->hasSSE42())
  if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy))
    return LT.first * (ExtraCost + Entry->Cost);

if (ST->hasSSE41())
  if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy))
    return LT.first * (ExtraCost + Entry->Cost);

if (ST->hasSSE2())
  if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
    return LT.first * (ExtraCost + Entry->Cost);

if (ST->hasSSE1())
  if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy))
    return LT.first * (ExtraCost + Entry->Cost);

return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I);
2542}

2544unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; }

2546InstructionCost
2547X86TTIImpl::getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
                                         TTI::TargetCostKind CostKind) {

// Costs should match the codegen from:
// BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll
// BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll
// CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll
// CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll
// CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll

// TODO: Overflow intrinsics (*ADDO, *SUBO, *MULO) with vector types are not
//       specialized in these tables yet.
static const CostTblEntry AVX512CDCostTbl[] = {
  { ISD::CTLZ,       MVT::v8i64,   1 },
  { ISD::CTLZ,       MVT::v16i32,  1 },
  { ISD::CTLZ,       MVT::v32i16,  8 },
  { ISD::CTLZ,       MVT::v64i8,  20 },
  { ISD::CTLZ,       MVT::v4i64,   1 },
  { ISD::CTLZ,       MVT::v8i32,   1 },
  { ISD::CTLZ,       MVT::v16i16,  4 },
  { ISD::CTLZ,       MVT::v32i8,  10 },
  { ISD::CTLZ,       MVT::v2i64,   1 },
  { ISD::CTLZ,       MVT::v4i32,   1 },
  { ISD::CTLZ,       MVT::v8i16,   4 },
  { ISD::CTLZ,       MVT::v16i8,   4 },
};
static const CostTblEntry AVX512BWCostTbl[] = {
  { ISD::ABS,        MVT::v32i16,  1 },
  { ISD::ABS,        MVT::v64i8,   1 },
  { ISD::BITREVERSE, MVT::v8i64,   5 },
  { ISD::BITREVERSE, MVT::v16i32,  5 },
  { ISD::BITREVERSE, MVT::v32i16,  5 },
  { ISD::BITREVERSE, MVT::v64i8,   5 },
  { ISD::BSWAP,      MVT::v8i64,   1 },
  { ISD::BSWAP,      MVT::v16i32,  1 },
  { ISD::BSWAP,      MVT::v32i16,  1 },
  { ISD::CTLZ,       MVT::v8i64,  23 },
  { ISD::CTLZ,       MVT::v16i32, 22 },
  { ISD::CTLZ,       MVT::v32i16, 18 },
  { ISD::CTLZ,       MVT::v64i8,  17 },
  { ISD::CTPOP,      MVT::v8i64,   7 },
  { ISD::CTPOP,      MVT::v16i32, 11 },
  { ISD::CTPOP,      MVT::v32i16,  9 },
  { ISD::CTPOP,      MVT::v64i8,   6 },
  { ISD::CTTZ,       MVT::v8i64,  10 },
  { ISD::CTTZ,       MVT::v16i32, 14 },
  { ISD::CTTZ,       MVT::v32i16, 12 },
  { ISD::CTTZ,       MVT::v64i8,   9 },
  { ISD::SADDSAT,    MVT::v32i16,  1 },
  { ISD::SADDSAT,    MVT::v64i8,   1 },
  { ISD::SMAX,       MVT::v32i16,  1 },
  { ISD::SMAX,       MVT::v64i8,   1 },
  { ISD::SMIN,       MVT::v32i16,  1 },
  { ISD::SMIN,       MVT::v64i8,   1 },
  { ISD::SSUBSAT,    MVT::v32i16,  1 },
  { ISD::SSUBSAT,    MVT::v64i8,   1 },
  { ISD::UADDSAT,    MVT::v32i16,  1 },
  { ISD::UADDSAT,    MVT::v64i8,   1 },
  { ISD::UMAX,       MVT::v32i16,  1 },
  { ISD::UMAX,       MVT::v64i8,   1 },
  { ISD::UMIN,       MVT::v32i16,  1 },
  { ISD::UMIN,       MVT::v64i8,   1 },
  { ISD::USUBSAT,    MVT::v32i16,  1 },
  { ISD::USUBSAT,    MVT::v64i8,   1 },
};
static const CostTblEntry AVX512CostTbl[] = {
  { ISD::ABS,        MVT::v8i64,   1 },
  { ISD::ABS,        MVT::v16i32,  1 },
  { ISD::ABS,        MVT::v32i16,  2 }, // FIXME: include split
  { ISD::ABS,        MVT::v64i8,   2 }, // FIXME: include split
  { ISD::ABS,        MVT::v4i64,   1 },
  { ISD::ABS,        MVT::v2i64,   1 },
  { ISD::BITREVERSE, MVT::v8i64,  36 },
  { ISD::BITREVERSE, MVT::v16i32, 24 },
  { ISD::BITREVERSE, MVT::v32i16, 10 },
  { ISD::BITREVERSE, MVT::v64i8,  10 },
  { ISD::BSWAP,      MVT::v8i64,   4 },
  { ISD::BSWAP,      MVT::v16i32,  4 },
  { ISD::BSWAP,      MVT::v32i16,  4 },
  { ISD::CTLZ,       MVT::v8i64,  29 },
  { ISD::CTLZ,       MVT::v16i32, 35 },
  { ISD::CTLZ,       MVT::v32i16, 28 },
  { ISD::CTLZ,       MVT::v64i8,  18 },
  { ISD::CTPOP,      MVT::v8i64,  16 },
  { ISD::CTPOP,      MVT::v16i32, 24 },
  { ISD::CTPOP,      MVT::v32i16, 18 },
  { ISD::CTPOP,      MVT::v64i8,  12 },
  { ISD::CTTZ,       MVT::v8i64,  20 },
  { ISD::CTTZ,       MVT::v16i32, 28 },
  { ISD::CTTZ,       MVT::v32i16, 24 },
  { ISD::CTTZ,       MVT::v64i8,  18 },
  { ISD::SMAX,       MVT::v8i64,   1 },
  { ISD::SMAX,       MVT::v16i32,  1 },
  { ISD::SMAX,       MVT::v32i16,  2 }, // FIXME: include split
  { ISD::SMAX,       MVT::v64i8,   2 }, // FIXME: include split
  { ISD::SMAX,       MVT::v4i64,   1 },
  { ISD::SMAX,       MVT::v2i64,   1 },
  { ISD::SMIN,       MVT::v8i64,   1 },
  { ISD::SMIN,       MVT::v16i32,  1 },
  { ISD::SMIN,       MVT::v32i16,  2 }, // FIXME: include split
  { ISD::SMIN,       MVT::v64i8,   2 }, // FIXME: include split
  { ISD::SMIN,       MVT::v4i64,   1 },
  { ISD::SMIN,       MVT::v2i64,   1 },
  { ISD::UMAX,       MVT::v8i64,   1 },
  { ISD::UMAX,       MVT::v16i32,  1 },
  { ISD::UMAX,       MVT::v32i16,  2 }, // FIXME: include split
  { ISD::UMAX,       MVT::v64i8,   2 }, // FIXME: include split
  { ISD::UMAX,       MVT::v4i64,   1 },
  { ISD::UMAX,       MVT::v2i64,   1 },
  { ISD::UMIN,       MVT::v8i64,   1 },
  { ISD::UMIN,       MVT::v16i32,  1 },
  { ISD::UMIN,       MVT::v32i16,  2 }, // FIXME: include split
  { ISD::UMIN,       MVT::v64i8,   2 }, // FIXME: include split
  { ISD::UMIN,       MVT::v4i64,   1 },
  { ISD::UMIN,       MVT::v2i64,   1 },
  { ISD::USUBSAT,    MVT::v16i32,  2 }, // pmaxud + psubd
  { ISD::USUBSAT,    MVT::v2i64,   2 }, // pmaxuq + psubq
  { ISD::USUBSAT,    MVT::v4i64,   2 }, // pmaxuq + psubq
  { ISD::USUBSAT,    MVT::v8i64,   2 }, // pmaxuq + psubq
  { ISD::UADDSAT,    MVT::v16i32,  3 }, // not + pminud + paddd
  { ISD::UADDSAT,    MVT::v2i64,   3 }, // not + pminuq + paddq
  { ISD::UADDSAT,    MVT::v4i64,   3 }, // not + pminuq + paddq
  { ISD::UADDSAT,    MVT::v8i64,   3 }, // not + pminuq + paddq
  { ISD::SADDSAT,    MVT::v32i16,  2 }, // FIXME: include split
  { ISD::SADDSAT,    MVT::v64i8,   2 }, // FIXME: include split
  { ISD::SSUBSAT,    MVT::v32i16,  2 }, // FIXME: include split
  { ISD::SSUBSAT,    MVT::v64i8,   2 }, // FIXME: include split
  { ISD::UADDSAT,    MVT::v32i16,  2 }, // FIXME: include split
  { ISD::UADDSAT,    MVT::v64i8,   2 }, // FIXME: include split
  { ISD::USUBSAT,    MVT::v32i16,  2 }, // FIXME: include split
  { ISD::USUBSAT,    MVT::v64i8,   2 }, // FIXME: include split
  { ISD::FMAXNUM,    MVT::f32,     2 },
  { ISD::FMAXNUM,    MVT::v4f32,   2 },
  { ISD::FMAXNUM,    MVT::v8f32,   2 },
  { ISD::FMAXNUM,    MVT::v16f32,  2 },
  { ISD::FMAXNUM,    MVT::f64,     2 },
  { ISD::FMAXNUM,    MVT::v2f64,   2 },
  { ISD::FMAXNUM,    MVT::v4f64,   2 },
  { ISD::FMAXNUM,    MVT::v8f64,   2 },
};
static const CostTblEntry XOPCostTbl[] = {
  { ISD::BITREVERSE, MVT::v4i64,   4 },
  { ISD::BITREVERSE, MVT::v8i32,   4 },
  { ISD::BITREVERSE, MVT::v16i16,  4 },
  { ISD::BITREVERSE, MVT::v32i8,   4 },
  { ISD::BITREVERSE, MVT::v2i64,   1 },
  { ISD::BITREVERSE, MVT::v4i32,   1 },
  { ISD::BITREVERSE, MVT::v8i16,   1 },
  { ISD::BITREVERSE, MVT::v16i8,   1 },
  { ISD::BITREVERSE, MVT::i64,     3 },
  { ISD::BITREVERSE, MVT::i32,     3 },
  { ISD::BITREVERSE, MVT::i16,     3 },
  { ISD::BITREVERSE, MVT::i8,      3 }
};
static const CostTblEntry AVX2CostTbl[] = {
  { ISD::ABS,        MVT::v4i64,   2 }, // VBLENDVPD(X,VPSUBQ(0,X),X)
  { ISD::ABS,        MVT::v8i32,   1 },
  { ISD::ABS,        MVT::v16i16,  1 },
  { ISD::ABS,        MVT::v32i8,   1 },
  { ISD::BITREVERSE, MVT::v4i64,   5 },
  { ISD::BITREVERSE, MVT::v8i32,   5 },
  { ISD::BITREVERSE, MVT::v16i16,  5 },
  { ISD::BITREVERSE, MVT::v32i8,   5 },
  { ISD::BSWAP,      MVT::v4i64,   1 },
  { ISD::BSWAP,      MVT::v8i32,   1 },
  { ISD::BSWAP,      MVT::v16i16,  1 },
  { ISD::CTLZ,       MVT::v4i64,  23 },
  { ISD::CTLZ,       MVT::v8i32,  18 },
  { ISD::CTLZ,       MVT::v16i16, 14 },
  { ISD::CTLZ,       MVT::v32i8,   9 },
  { ISD::CTPOP,      MVT::v4i64,   7 },
  { ISD::CTPOP,      MVT::v8i32,  11 },
  { ISD::CTPOP,      MVT::v16i16,  9 },
  { ISD::CTPOP,      MVT::v32i8,   6 },
  { ISD::CTTZ,       MVT::v4i64,  10 },
  { ISD::CTTZ,       MVT::v8i32,  14 },
  { ISD::CTTZ,       MVT::v16i16, 12 },
  { ISD::CTTZ,       MVT::v32i8,   9 },
  { ISD::SADDSAT,    MVT::v16i16,  1 },
  { ISD::SADDSAT,    MVT::v32i8,   1 },
  { ISD::SMAX,       MVT::v8i32,   1 },
  { ISD::SMAX,       MVT::v16i16,  1 },
  { ISD::SMAX,       MVT::v32i8,   1 },
  { ISD::SMIN,       MVT::v8i32,   1 },
  { ISD::SMIN,       MVT::v16i16,  1 },
  { ISD::SMIN,       MVT::v32i8,   1 },
  { ISD::SSUBSAT,    MVT::v16i16,  1 },
  { ISD::SSUBSAT,    MVT::v32i8,   1 },
  { ISD::UADDSAT,    MVT::v16i16,  1 },
  { ISD::UADDSAT,    MVT::v32i8,   1 },
  { ISD::UADDSAT,    MVT::v8i32,   3 }, // not + pminud + paddd
  { ISD::UMAX,       MVT::v8i32,   1 },
  { ISD::UMAX,       MVT::v16i16,  1 },
  { ISD::UMAX,       MVT::v32i8,   1 },
  { ISD::UMIN,       MVT::v8i32,   1 },
  { ISD::UMIN,       MVT::v16i16,  1 },
  { ISD::UMIN,       MVT::v32i8,   1 },
  { ISD::USUBSAT,    MVT::v16i16,  1 },
  { ISD::USUBSAT,    MVT::v32i8,   1 },
  { ISD::USUBSAT,    MVT::v8i32,   2 }, // pmaxud + psubd
  { ISD::FMAXNUM,    MVT::v8f32,   3 }, // MAXPS + CMPUNORDPS + BLENDVPS
  { ISD::FMAXNUM,    MVT::v4f64,   3 }, // MAXPD + CMPUNORDPD + BLENDVPD
  { ISD::FSQRT,      MVT::f32,     7 }, // Haswell from http://www.agner.org/
  { ISD::FSQRT,      MVT::v4f32,   7 }, // Haswell from http://www.agner.org/
  { ISD::FSQRT,      MVT::v8f32,  14 }, // Haswell from http://www.agner.org/
  { ISD::FSQRT,      MVT::f64,    14 }, // Haswell from http://www.agner.org/
  { ISD::FSQRT,      MVT::v2f64,  14 }, // Haswell from http://www.agner.org/
  { ISD::FSQRT,      MVT::v4f64,  28 }, // Haswell from http://www.agner.org/
};
static const CostTblEntry AVX1CostTbl[] = {
  { ISD::ABS,        MVT::v4i64,   5 }, // VBLENDVPD(X,VPSUBQ(0,X),X)
  { ISD::ABS,        MVT::v8i32,   3 },
  { ISD::ABS,        MVT::v16i16,  3 },
  { ISD::ABS,        MVT::v32i8,   3 },
  { ISD::BITREVERSE, MVT::v4i64,  12 }, // 2 x 128-bit Op + extract/insert
  { ISD::BITREVERSE, MVT::v8i32,  12 }, // 2 x 128-bit Op + extract/insert
  { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert
  { ISD::BITREVERSE, MVT::v32i8,  12 }, // 2 x 128-bit Op + extract/insert
  { ISD::BSWAP,      MVT::v4i64,   4 },
  { ISD::BSWAP,      MVT::v8i32,   4 },
  { ISD::BSWAP,      MVT::v16i16,  4 },
  { ISD::CTLZ,       MVT::v4i64,  48 }, // 2 x 128-bit Op + extract/insert
  { ISD::CTLZ,       MVT::v8i32,  38 }, // 2 x 128-bit Op + extract/insert
  { ISD::CTLZ,       MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert
  { ISD::CTLZ,       MVT::v32i8,  20 }, // 2 x 128-bit Op + extract/insert
  { ISD::CTPOP,      MVT::v4i64,  16 }, // 2 x 128-bit Op + extract/insert
  { ISD::CTPOP,      MVT::v8i32,  24 }, // 2 x 128-bit Op + extract/insert
  { ISD::CTPOP,      MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert
  { ISD::CTPOP,      MVT::v32i8,  14 }, // 2 x 128-bit Op + extract/insert
  { ISD::CTTZ,       MVT::v4i64,  22 }, // 2 x 128-bit Op + extract/insert
  { ISD::CTTZ,       MVT::v8i32,  30 }, // 2 x 128-bit Op + extract/insert
  { ISD::CTTZ,       MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert
  { ISD::CTTZ,       MVT::v32i8,  20 }, // 2 x 128-bit Op + extract/insert
  { ISD::SADDSAT,    MVT::v16i16,  4 }, // 2 x 128-bit Op + extract/insert
  { ISD::SADDSAT,    MVT::v32i8,   4 }, // 2 x 128-bit Op + extract/insert
  { ISD::SMAX,       MVT::v8i32,   4 }, // 2 x 128-bit Op + extract/insert
  { ISD::SMAX,       MVT::v16i16,  4 }, // 2 x 128-bit Op + extract/insert
  { ISD::SMAX,       MVT::v32i8,   4 }, // 2 x 128-bit Op + extract/insert
  { ISD::SMIN,       MVT::v8i32,   4 }, // 2 x 128-bit Op + extract/insert
  { ISD::SMIN,       MVT::v16i16,  4 }, // 2 x 128-bit Op + extract/insert
  { ISD::SMIN,       MVT::v32i8,   4 }, // 2 x 128-bit Op + extract/insert
  { ISD::SSUBSAT,    MVT::v16i16,  4 }, // 2 x 128-bit Op + extract/insert
  { ISD::SSUBSAT,    MVT::v32i8,   4 }, // 2 x 128-bit Op + extract/insert
  { ISD::UADDSAT,    MVT::v16i16,  4 }, // 2 x 128-bit Op + extract/insert
  { ISD::UADDSAT,    MVT::v32i8,   4 }, // 2 x 128-bit Op + extract/insert
  { ISD::UADDSAT,    MVT::v8i32,   8 }, // 2 x 128-bit Op + extract/insert
  { ISD::UMAX,       MVT::v8i32,   4 }, // 2 x 128-bit Op + extract/insert
  { ISD::UMAX,       MVT::v16i16,  4 }, // 2 x 128-bit Op + extract/insert
  { ISD::UMAX,       MVT::v32i8,   4 }, // 2 x 128-bit Op + extract/insert
  { ISD::UMIN,       MVT::v8i32,   4 }, // 2 x 128-bit Op + extract/insert
  { ISD::UMIN,       MVT::v16i16,  4 }, // 2 x 128-bit Op + extract/insert
  { ISD::UMIN,       MVT::v32i8,   4 }, // 2 x 128-bit Op + extract/insert
  { ISD::USUBSAT,    MVT::v16i16,  4 }, // 2 x 128-bit Op + extract/insert
  { ISD::USUBSAT,    MVT::v32i8,   4 }, // 2 x 128-bit Op + extract/insert
  { ISD::USUBSAT,    MVT::v8i32,   6 }, // 2 x 128-bit Op + extract/insert
  { ISD::FMAXNUM,    MVT::f32,     3 }, // MAXSS + CMPUNORDSS + BLENDVPS
  { ISD::FMAXNUM,    MVT::v4f32,   3 }, // MAXPS + CMPUNORDPS + BLENDVPS
  { ISD::FMAXNUM,    MVT::v8f32,   5 }, // MAXPS + CMPUNORDPS + BLENDVPS + ?
  { ISD::FMAXNUM,    MVT::f64,     3 }, // MAXSD + CMPUNORDSD + BLENDVPD
  { ISD::FMAXNUM,    MVT::v2f64,   3 }, // MAXPD + CMPUNORDPD + BLENDVPD
  { ISD::FMAXNUM,    MVT::v4f64,   5 }, // MAXPD + CMPUNORDPD + BLENDVPD + ?
  { ISD::FSQRT,      MVT::f32,    14 }, // SNB from http://www.agner.org/
  { ISD::FSQRT,      MVT::v4f32,  14 }, // SNB from http://www.agner.org/
  { ISD::FSQRT,      MVT::v8f32,  28 }, // SNB from http://www.agner.org/
  { ISD::FSQRT,      MVT::f64,    21 }, // SNB from http://www.agner.org/
  { ISD::FSQRT,      MVT::v2f64,  21 }, // SNB from http://www.agner.org/
  { ISD::FSQRT,      MVT::v4f64,  43 }, // SNB from http://www.agner.org/
};
static const CostTblEntry GLMCostTbl[] = {
  { ISD::FSQRT, MVT::f32,   19 }, // sqrtss
  { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps
  { ISD::FSQRT, MVT::f64,   34 }, // sqrtsd
  { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd
};
static const CostTblEntry SLMCostTbl[] = {
  { ISD::FSQRT, MVT::f32,   20 }, // sqrtss
  { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps
  { ISD::FSQRT, MVT::f64,   35 }, // sqrtsd
  { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd
};
static const CostTblEntry SSE42CostTbl[] = {
  { ISD::USUBSAT,    MVT::v4i32,   2 }, // pmaxud + psubd
  { ISD::UADDSAT,    MVT::v4i32,   3 }, // not + pminud + paddd
  { ISD::FSQRT,      MVT::f32,    18 }, // Nehalem from http://www.agner.org/
  { ISD::FSQRT,      MVT::v4f32,  18 }, // Nehalem from http://www.agner.org/
};
static const CostTblEntry SSE41CostTbl[] = {
  { ISD::ABS,        MVT::v2i64,   2 }, // BLENDVPD(X,PSUBQ(0,X),X)
  { ISD::SMAX,       MVT::v4i32,   1 },
  { ISD::SMAX,       MVT::v16i8,   1 },
  { ISD::SMIN,       MVT::v4i32,   1 },
  { ISD::SMIN,       MVT::v16i8,   1 },
  { ISD::UMAX,       MVT::v4i32,   1 },
  { ISD::UMAX,       MVT::v8i16,   1 },
  { ISD::UMIN,       MVT::v4i32,   1 },
  { ISD::UMIN,       MVT::v8i16,   1 },
};
static const CostTblEntry SSSE3CostTbl[] = {
  { ISD::ABS,        MVT::v4i32,   1 },
  { ISD::ABS,        MVT::v8i16,   1 },
  { ISD::ABS,        MVT::v16i8,   1 },
  { ISD::BITREVERSE, MVT::v2i64,   5 },
  { ISD::BITREVERSE, MVT::v4i32,   5 },
  { ISD::BITREVERSE, MVT::v8i16,   5 },
  { ISD::BITREVERSE, MVT::v16i8,   5 },
  { ISD::BSWAP,      MVT::v2i64,   1 },
  { ISD::BSWAP,      MVT::v4i32,   1 },
  { ISD::BSWAP,      MVT::v8i16,   1 },
  { ISD::CTLZ,       MVT::v2i64,  23 },
  { ISD::CTLZ,       MVT::v4i32,  18 },
  { ISD::CTLZ,       MVT::v8i16,  14 },
  { ISD::CTLZ,       MVT::v16i8,   9 },
  { ISD::CTPOP,      MVT::v2i64,   7 },
  { ISD::CTPOP,      MVT::v4i32,  11 },
  { ISD::CTPOP,      MVT::v8i16,   9 },
  { ISD::CTPOP,      MVT::v16i8,   6 },
  { ISD::CTTZ,       MVT::v2i64,  10 },
  { ISD::CTTZ,       MVT::v4i32,  14 },
  { ISD::CTTZ,       MVT::v8i16,  12 },
  { ISD::CTTZ,       MVT::v16i8,   9 }
};
static const CostTblEntry SSE2CostTbl[] = {
  { ISD::ABS,        MVT::v2i64,   4 },
  { ISD::ABS,        MVT::v4i32,   3 },
  { ISD::ABS,        MVT::v8i16,   2 },
  { ISD::ABS,        MVT::v16i8,   2 },
  { ISD::BITREVERSE, MVT::v2i64,  29 },
  { ISD::BITREVERSE, MVT::v4i32,  27 },
  { ISD::BITREVERSE, MVT::v8i16,  27 },
  { ISD::BITREVERSE, MVT::v16i8,  20 },
  { ISD::BSWAP,      MVT::v2i64,   7 },
  { ISD::BSWAP,      MVT::v4i32,   7 },
  { ISD::BSWAP,      MVT::v8i16,   7 },
  { ISD::CTLZ,       MVT::v2i64,  25 },
  { ISD::CTLZ,       MVT::v4i32,  26 },
  { ISD::CTLZ,       MVT::v8i16,  20 },
  { ISD::CTLZ,       MVT::v16i8,  17 },
  { ISD::CTPOP,      MVT::v2i64,  12 },
  { ISD::CTPOP,      MVT::v4i32,  15 },
  { ISD::CTPOP,      MVT::v8i16,  13 },
  { ISD::CTPOP,      MVT::v16i8,  10 },
  { ISD::CTTZ,       MVT::v2i64,  14 },
  { ISD::CTTZ,       MVT::v4i32,  18 },
  { ISD::CTTZ,       MVT::v8i16,  16 },
  { ISD::CTTZ,       MVT::v16i8,  13 },
  { ISD::SADDSAT,    MVT::v8i16,   1 },
  { ISD::SADDSAT,    MVT::v16i8,   1 },
  { ISD::SMAX,       MVT::v8i16,   1 },
  { ISD::SMIN,       MVT::v8i16,   1 },
  { ISD::SSUBSAT,    MVT::v8i16,   1 },
  { ISD::SSUBSAT,    MVT::v16i8,   1 },
  { ISD::UADDSAT,    MVT::v8i16,   1 },
  { ISD::UADDSAT,    MVT::v16i8,   1 },
  { ISD::UMAX,       MVT::v8i16,   2 },
  { ISD::UMAX,       MVT::v16i8,   1 },
  { ISD::UMIN,       MVT::v8i16,   2 },
  { ISD::UMIN,       MVT::v16i8,   1 },
  { ISD::USUBSAT,    MVT::v8i16,   1 },
  { ISD::USUBSAT,    MVT::v16i8,   1 },
  { ISD::FMAXNUM,    MVT::f64,     4 },
  { ISD::FMAXNUM,    MVT::v2f64,   4 },
  { ISD::FSQRT,      MVT::f64,    32 }, // Nehalem from http://www.agner.org/
  { ISD::FSQRT,      MVT::v2f64,  32 }, // Nehalem from http://www.agner.org/
};
static const CostTblEntry SSE1CostTbl[] = {
  { ISD::FMAXNUM,    MVT::f32,     4 },
  { ISD::FMAXNUM,    MVT::v4f32,   4 },
  { ISD::FSQRT,      MVT::f32,    28 }, // Pentium III from http://www.agner.org/
  { ISD::FSQRT,      MVT::v4f32,  56 }, // Pentium III from http://www.agner.org/
};
static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets
  { ISD::CTTZ,       MVT::i64,     1 },
};
static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets
  { ISD::CTTZ,       MVT::i32,     1 },
  { ISD::CTTZ,       MVT::i16,     1 },
  { ISD::CTTZ,       MVT::i8,      1 },
};
static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets
  { ISD::CTLZ,       MVT::i64,     1 },
};
static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets
  { ISD::CTLZ,       MVT::i32,     1 },
  { ISD::CTLZ,       MVT::i16,     1 },
  { ISD::CTLZ,       MVT::i8,      1 },
};
static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets
  { ISD::CTPOP,      MVT::i64,     1 },
};
static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets
  { ISD::CTPOP,      MVT::i32,     1 },
  { ISD::CTPOP,      MVT::i16,     1 },
  { ISD::CTPOP,      MVT::i8,      1 },
};
static const CostTblEntry X64CostTbl[] = { // 64-bit targets
  { ISD::ABS,        MVT::i64,     2 }, // SUB+CMOV
  { ISD::BITREVERSE, MVT::i64,    14 },
  { ISD::BSWAP,      MVT::i64,     1 },
  { ISD::CTLZ,       MVT::i64,     4 }, // BSR+XOR or BSR+XOR+CMOV
  { ISD::CTTZ,       MVT::i64,     3 }, // TEST+BSF+CMOV/BRANCH
  { ISD::CTPOP,      MVT::i64,    10 },
  { ISD::SADDO,      MVT::i64,     1 },
  { ISD::UADDO,      MVT::i64,     1 },
  { ISD::UMULO,      MVT::i64,     2 }, // mulq + seto
};
static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets
  { ISD::ABS,        MVT::i32,     2 }, // SUB+CMOV
  { ISD::ABS,        MVT::i16,     2 }, // SUB+CMOV
  { ISD::BITREVERSE, MVT::i32,    14 },
  { ISD::BITREVERSE, MVT::i16,    14 },
  { ISD::BITREVERSE, MVT::i8,     11 },
  { ISD::BSWAP,      MVT::i32,     1 },
  { ISD::BSWAP,      MVT::i16,     1 }, // ROL
  { ISD::CTLZ,       MVT::i32,     4 }, // BSR+XOR or BSR+XOR+CMOV
  { ISD::CTLZ,       MVT::i16,     4 }, // BSR+XOR or BSR+XOR+CMOV
  { ISD::CTLZ,       MVT::i8,      4 }, // BSR+XOR or BSR+XOR+CMOV
  { ISD::CTTZ,       MVT::i32,     3 }, // TEST+BSF+CMOV/BRANCH
  { ISD::CTTZ,       MVT::i16,     3 }, // TEST+BSF+CMOV/BRANCH
  { ISD::CTTZ,       MVT::i8,      3 }, // TEST+BSF+CMOV/BRANCH
  { ISD::CTPOP,      MVT::i32,     8 },
  { ISD::CTPOP,      MVT::i16,     9 },
  { ISD::CTPOP,      MVT::i8,      7 },
  { ISD::SADDO,      MVT::i32,     1 },
  { ISD::SADDO,      MVT::i16,     1 },
  { ISD::SADDO,      MVT::i8,      1 },
  { ISD::UADDO,      MVT::i32,     1 },
  { ISD::UADDO,      MVT::i16,     1 },
  { ISD::UADDO,      MVT::i8,      1 },
  { ISD::UMULO,      MVT::i32,     2 }, // mul + seto
  { ISD::UMULO,      MVT::i16,     2 },
  { ISD::UMULO,      MVT::i8,      2 },
};

Type *RetTy = ICA.getReturnType();
Type *OpTy = RetTy;
Intrinsic::ID IID = ICA.getID();
unsigned ISD = ISD::DELETED_NODE;
switch (IID) {
default:
  break;
case Intrinsic::abs:
  ISD = ISD::ABS;
  break;
case Intrinsic::bitreverse:
  ISD = ISD::BITREVERSE;
  break;
case Intrinsic::bswap:
  ISD = ISD::BSWAP;
  break;
case Intrinsic::ctlz:
  ISD = ISD::CTLZ;
  break;
case Intrinsic::ctpop:
  ISD = ISD::CTPOP;
  break;
case Intrinsic::cttz:
  ISD = ISD::CTTZ;
  break;
case Intrinsic::maxnum:
case Intrinsic::minnum:
  // FMINNUM has same costs so don't duplicate.
  ISD = ISD::FMAXNUM;
  break;
case Intrinsic::sadd_sat:
  ISD = ISD::SADDSAT;
  break;
case Intrinsic::smax:
  ISD = ISD::SMAX;
  break;
case Intrinsic::smin:
  ISD = ISD::SMIN;
  break;
case Intrinsic::ssub_sat:
  ISD = ISD::SSUBSAT;
  break;
case Intrinsic::uadd_sat:
  ISD = ISD::UADDSAT;
  break;
case Intrinsic::umax:
  ISD = ISD::UMAX;
  break;
case Intrinsic::umin:
  ISD = ISD::UMIN;
  break;
case Intrinsic::usub_sat:
  ISD = ISD::USUBSAT;
  break;
case Intrinsic::sqrt:
  ISD = ISD::FSQRT;
  break;
case Intrinsic::sadd_with_overflow:
case Intrinsic::ssub_with_overflow:
  // SSUBO has same costs so don't duplicate.
  ISD = ISD::SADDO;
  OpTy = RetTy->getContainedType(0);
  break;
case Intrinsic::uadd_with_overflow:
case Intrinsic::usub_with_overflow:
  // USUBO has same costs so don't duplicate.
  ISD = ISD::UADDO;
  OpTy = RetTy->getContainedType(0);
  break;
case Intrinsic::umul_with_overflow:
case Intrinsic::smul_with_overflow:
  // SMULO has same costs so don't duplicate.
  ISD = ISD::UMULO;
  OpTy = RetTy->getContainedType(0);
  break;
}

if (ISD != ISD::DELETED_NODE) {
  // Legalize the type.
  std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy);
  MVT MTy = LT.second;

  // Attempt to lookup cost.
  if (ISD == ISD::BITREVERSE && ST->hasGFNI() && ST->hasSSSE3() &&
      MTy.isVector()) {
    // With PSHUFB the code is very similar for all types. If we have integer
    // byte operations, we just need a GF2P8AFFINEQB for vXi8. For other types
    // we also need a PSHUFB.
    unsigned Cost = MTy.getVectorElementType() == MVT::i8 ? 1 : 2;

    // Without byte operations, we need twice as many GF2P8AFFINEQB and PSHUFB
    // instructions. We also need an extract and an insert.
    if (!(MTy.is128BitVector() || (ST->hasAVX2() && MTy.is256BitVector()) ||
          (ST->hasBWI() && MTy.is512BitVector())))
      Cost = Cost * 2 + 2;

    return LT.first * Cost;
  }

  auto adjustTableCost = [](const CostTblEntry &Entry,
                            InstructionCost LegalizationCost,
                            FastMathFlags FMF) {
    // If there are no NANs to deal with, then these are reduced to a
    // single MIN** or MAX** instruction instead of the MIN/CMP/SELECT that we
    // assume is used in the non-fast case.
    if (Entry.ISD == ISD::FMAXNUM || Entry.ISD == ISD::FMINNUM) {
      if (FMF.noNaNs())
        return LegalizationCost * 1;
    }
    return LegalizationCost * (int)Entry.Cost;
  };

  if (ST->useGLMDivSqrtCosts())
    if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy))
      return adjustTableCost(*Entry, LT.first, ICA.getFlags());

  if (ST->isSLM())
    if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy))
      return adjustTableCost(*Entry, LT.first, ICA.getFlags());

  if (ST->hasCDI())
    if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy))
      return adjustTableCost(*Entry, LT.first, ICA.getFlags());

  if (ST->hasBWI())
    if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
      return adjustTableCost(*Entry, LT.first, ICA.getFlags());

  if (ST->hasAVX512())
    if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
      return adjustTableCost(*Entry, LT.first, ICA.getFlags());

  if (ST->hasXOP())
    if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy))
      return adjustTableCost(*Entry, LT.first, ICA.getFlags());

  if (ST->hasAVX2())
    if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy))
      return adjustTableCost(*Entry, LT.first, ICA.getFlags());

  if (ST->hasAVX())
    if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
      return adjustTableCost(*Entry, LT.first, ICA.getFlags());

  if (ST->hasSSE42())
    if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy))
      return adjustTableCost(*Entry, LT.first, ICA.getFlags());

  if (ST->hasSSE41())
    if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy))
      return adjustTableCost(*Entry, LT.first, ICA.getFlags());

  if (ST->hasSSSE3())
    if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy))
      return adjustTableCost(*Entry, LT.first, ICA.getFlags());

  if (ST->hasSSE2())
    if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
      return adjustTableCost(*Entry, LT.first, ICA.getFlags());

  if (ST->hasSSE1())
    if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy))
      return adjustTableCost(*Entry, LT.first, ICA.getFlags());

  if (ST->hasBMI()) {
    if (ST->is64Bit())
      if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy))
        return adjustTableCost(*Entry, LT.first, ICA.getFlags());

    if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy))
      return adjustTableCost(*Entry, LT.first, ICA.getFlags());
  }

  if (ST->hasLZCNT()) {
    if (ST->is64Bit())
      if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy))
        return adjustTableCost(*Entry, LT.first, ICA.getFlags());

    if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy))
      return adjustTableCost(*Entry, LT.first, ICA.getFlags());
  }

  if (ST->hasPOPCNT()) {
    if (ST->is64Bit())
      if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy))
        return adjustTableCost(*Entry, LT.first, ICA.getFlags());

    if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy))
      return adjustTableCost(*Entry, LT.first, ICA.getFlags());
  }

  if (ISD == ISD::BSWAP && ST->hasMOVBE() && ST->hasFastMOVBE()) {
    if (const Instruction *II = ICA.getInst()) {
      if (II->hasOneUse() && isa<StoreInst>(II->user_back()))
        return TTI::TCC_Free;
      if (auto *LI = dyn_cast<LoadInst>(II->getOperand(0))) {
        if (LI->hasOneUse())
          return TTI::TCC_Free;
      }
    }
  }

  // TODO - add BMI (TZCNT) scalar handling

  if (ST->is64Bit())
    if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy))
      return adjustTableCost(*Entry, LT.first, ICA.getFlags());

  if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy))
    return adjustTableCost(*Entry, LT.first, ICA.getFlags());
}

return BaseT::getIntrinsicInstrCost(ICA, CostKind);
3193}

3195InstructionCost
3196X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
                                TTI::TargetCostKind CostKind) {
if (ICA.isTypeBasedOnly())
  return getTypeBasedIntrinsicInstrCost(ICA, CostKind);

static const CostTblEntry AVX512CostTbl[] = {
  { ISD::ROTL,       MVT::v8i64,   1 },
  { ISD::ROTL,       MVT::v4i64,   1 },
  { ISD::ROTL,       MVT::v2i64,   1 },
  { ISD::ROTL,       MVT::v16i32,  1 },
  { ISD::ROTL,       MVT::v8i32,   1 },
  { ISD::ROTL,       MVT::v4i32,   1 },
  { ISD::ROTR,       MVT::v8i64,   1 },
  { ISD::ROTR,       MVT::v4i64,   1 },
  { ISD::ROTR,       MVT::v2i64,   1 },
  { ISD::ROTR,       MVT::v16i32,  1 },
  { ISD::ROTR,       MVT::v8i32,   1 },
  { ISD::ROTR,       MVT::v4i32,   1 }
};
// XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y))
static const CostTblEntry XOPCostTbl[] = {
  { ISD::ROTL,       MVT::v4i64,   4 },
  { ISD::ROTL,       MVT::v8i32,   4 },
  { ISD::ROTL,       MVT::v16i16,  4 },
  { ISD::ROTL,       MVT::v32i8,   4 },
  { ISD::ROTL,       MVT::v2i64,   1 },
  { ISD::ROTL,       MVT::v4i32,   1 },
  { ISD::ROTL,       MVT::v8i16,   1 },
  { ISD::ROTL,       MVT::v16i8,   1 },
  { ISD::ROTR,       MVT::v4i64,   6 },
  { ISD::ROTR,       MVT::v8i32,   6 },
  { ISD::ROTR,       MVT::v16i16,  6 },
  { ISD::ROTR,       MVT::v32i8,   6 },
  { ISD::ROTR,       MVT::v2i64,   2 },
  { ISD::ROTR,       MVT::v4i32,   2 },
  { ISD::ROTR,       MVT::v8i16,   2 },
  { ISD::ROTR,       MVT::v16i8,   2 }
};
static const CostTblEntry X64CostTbl[] = { // 64-bit targets
  { ISD::ROTL,       MVT::i64,     1 },
  { ISD::ROTR,       MVT::i64,     1 },
  { ISD::FSHL,       MVT::i64,     4 }
};
static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets
  { ISD::ROTL,       MVT::i32,     1 },
  { ISD::ROTL,       MVT::i16,     1 },
  { ISD::ROTL,       MVT::i8,      1 },
  { ISD::ROTR,       MVT::i32,     1 },
  { ISD::ROTR,       MVT::i16,     1 },
  { ISD::ROTR,       MVT::i8,      1 },
  { ISD::FSHL,       MVT::i32,     4 },
  { ISD::FSHL,       MVT::i16,     4 },
  { ISD::FSHL,       MVT::i8,      4 }
};

Intrinsic::ID IID = ICA.getID();
Type *RetTy = ICA.getReturnType();
const SmallVectorImpl<const Value *> &Args = ICA.getArgs();
unsigned ISD = ISD::DELETED_NODE;
switch (IID) {
default:
  break;
case Intrinsic::fshl:
  ISD = ISD::FSHL;
  if (Args[0] == Args[1])
    ISD = ISD::ROTL;
  break;
case Intrinsic::fshr:
  // FSHR has same costs so don't duplicate.
  ISD = ISD::FSHL;
  if (Args[0] == Args[1])
    ISD = ISD::ROTR;
  break;
}

if (ISD != ISD::DELETED_NODE) {
  // Legalize the type.
  std::pair<InstructionCost, MVT> LT =
      TLI->getTypeLegalizationCost(DL, RetTy);
  MVT MTy = LT.second;

  // Attempt to lookup cost.
  if (ST->hasAVX512())
    if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
      return LT.first * Entry->Cost;

  if (ST->hasXOP())
    if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy))
      return LT.first * Entry->Cost;

  if (ST->is64Bit())
    if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy))
      return LT.first * Entry->Cost;

  if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy))
    return LT.first * Entry->Cost;
}

return BaseT::getIntrinsicInstrCost(ICA, CostKind);
3295}

3297InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
                                             unsigned Index) {
static const CostTblEntry SLMCostTbl[] = {
   { ISD::EXTRACT_VECTOR_ELT,       MVT::i8,      4 },
   { ISD::EXTRACT_VECTOR_ELT,       MVT::i16,     4 },
   { ISD::EXTRACT_VECTOR_ELT,       MVT::i32,     4 },
   { ISD::EXTRACT_VECTOR_ELT,       MVT::i64,     7 }
 };

assert(Val->isVectorTy() && "This must be a vector type")((void)0);
Type *ScalarType = Val->getScalarType();
int RegisterFileMoveCost = 0;

// Non-immediate extraction/insertion can be handled as a sequence of
// aliased loads+stores via the stack.
if (Index == -1U && (Opcode == Instruction::ExtractElement ||
                     Opcode == Instruction::InsertElement)) {
  // TODO: On some SSE41+ targets, we expand to cmp+splat+select patterns:
  // inselt N0, N1, N2 --> select (SplatN2 == {0,1,2...}) ? SplatN1 : N0. 

  // TODO: Move this to BasicTTIImpl.h? We'd need better gep + index handling.
  assert(isa<FixedVectorType>(Val) && "Fixed vector type expected")((void)0);
  Align VecAlign = DL.getPrefTypeAlign(Val);
  Align SclAlign = DL.getPrefTypeAlign(ScalarType);

  // Extract - store vector to stack, load scalar.
  if (Opcode == Instruction::ExtractElement) {
    return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0,
                           TTI::TargetCostKind::TCK_RecipThroughput) +
           getMemoryOpCost(Instruction::Load, ScalarType, SclAlign, 0,
                           TTI::TargetCostKind::TCK_RecipThroughput);
  }
  // Insert - store vector to stack, store scalar, load vector.
  if (Opcode == Instruction::InsertElement) {
    return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0,
                           TTI::TargetCostKind::TCK_RecipThroughput) +
           getMemoryOpCost(Instruction::Store, ScalarType, SclAlign, 0,
                           TTI::TargetCostKind::TCK_RecipThroughput) +
           getMemoryOpCost(Instruction::Load, Val, VecAlign, 0,
                           TTI::TargetCostKind::TCK_RecipThroughput);
  }
}

if (Index != -1U && (Opcode14.1
'Opcode' is not equal to ExtractElement
1
'Opcode' is not equal to ExtractElement
1
'Opcode' is not equal to ExtractElement
 == Instruction::ExtractElement ||
15
←
Taking true branch→
                     Opcode14.2
'Opcode' is equal to InsertElement
2
'Opcode' is equal to InsertElement
2
'Opcode' is equal to InsertElement
 == Instruction::InsertElement)) {
  // Legalize the type.
  std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Val);

  // This type is legalized to a scalar type.
  if (!LT.second.isVector())
16
←
Calling 'MVT::isVector'→
20
←
Returning from 'MVT::isVector'→
21
←
Taking false branch→
    return 0;

  // The type may be split. Normalize the index to the new type.
  unsigned NumElts = LT.second.getVectorNumElements();
  unsigned SubNumElts = NumElts;
  Index = Index % NumElts;

  // For >128-bit vectors, we need to extract higher 128-bit subvectors.
  // For inserts, we also need to insert the subvector back.
  if (LT.second.getSizeInBits() > 128) {
22
←
Assuming the condition is true→
23
←
Taking true branch→
    assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector")((void)0);
    unsigned NumSubVecs = LT.second.getSizeInBits() / 128;
    SubNumElts = NumElts / NumSubVecs;
24
←
Value assigned to 'SubNumElts'→
    if (SubNumElts <= Index) {
25
←
Assuming 'SubNumElts' is <= 'Index'→
26
←
Taking true branch→
      RegisterFileMoveCost += (Opcode26.1
'Opcode' is equal to InsertElement
1
'Opcode' is equal to InsertElement
1
'Opcode' is equal to InsertElement
 == Instruction::InsertElement ? 2 : 1);
27
←
'?' condition is true→
      Index %= SubNumElts;
28
←
Division by zero
    }
  }

  if (Index == 0) {
    // Floating point scalars are already located in index #0.
    // Many insertions to #0 can fold away for scalar fp-ops, so let's assume
    // true for all.
    if (ScalarType->isFloatingPointTy())
      return RegisterFileMoveCost;

    // Assume movd/movq XMM -> GPR is relatively cheap on all targets.
    if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement)
      return 1 + RegisterFileMoveCost;
  }

  int ISD = TLI->InstructionOpcodeToISD(Opcode);
  assert(ISD && "Unexpected vector opcode")((void)0);
  MVT MScalarTy = LT.second.getScalarType();
  if (ST->isSLM())
    if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy))
      return Entry->Cost + RegisterFileMoveCost;

  // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets.
  if ((MScalarTy == MVT::i16 && ST->hasSSE2()) ||
      (MScalarTy.isInteger() && ST->hasSSE41()))
    return 1 + RegisterFileMoveCost;

  // Assume insertps is relatively cheap on all targets.
  if (MScalarTy == MVT::f32 && ST->hasSSE41() &&
      Opcode == Instruction::InsertElement)
    return 1 + RegisterFileMoveCost;

  // For extractions we just need to shuffle the element to index 0, which
  // should be very cheap (assume cost = 1). For insertions we need to shuffle
  // the elements to its destination. In both cases we must handle the
  // subvector move(s).
  // If the vector type is already less than 128-bits then don't reduce it.
  // TODO: Under what circumstances should we shuffle using the full width?
  InstructionCost ShuffleCost = 1;
  if (Opcode == Instruction::InsertElement) {
    auto *SubTy = cast<VectorType>(Val);
    EVT VT = TLI->getValueType(DL, Val);
    if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128)
      SubTy = FixedVectorType::get(ScalarType, SubNumElts);
    ShuffleCost =
        getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, None, 0, SubTy);
  }
  int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1;
  return ShuffleCost + IntOrFpCost + RegisterFileMoveCost;
}

// Add to the base cost if we know that the extracted element of a vector is
// destined to be moved to and used in the integer register file.
if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy())
  RegisterFileMoveCost += 1;

return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost;
3420}

3422InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty,
                                                   const APInt &DemandedElts,
                                                   bool Insert,
                                                   bool Extract) {
InstructionCost Cost = 0;

// For insertions, a ISD::BUILD_VECTOR style vector initialization can be much
// cheaper than an accumulation of ISD::INSERT_VECTOR_ELT.
if (Insert) {
  std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
  MVT MScalarTy = LT.second.getScalarType();

  if ((MScalarTy == MVT::i16 && ST->hasSSE2()) ||
      (MScalarTy.isInteger() && ST->hasSSE41()) ||
      (MScalarTy == MVT::f32 && ST->hasSSE41())) {
    // For types we can insert directly, insertion into 128-bit sub vectors is
    // cheap, followed by a cheap chain of concatenations.
    if (LT.second.getSizeInBits() <= 128) {
      Cost +=
          BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false);
    } else {
      // In each 128-lane, if at least one index is demanded but not all
      // indices are demanded and this 128-lane is not the first 128-lane of
      // the legalized-vector, then this 128-lane needs a extracti128; If in
      // each 128-lane, there is at least one demanded index, this 128-lane
      // needs a inserti128.

      // The following cases will help you build a better understanding:
      // Assume we insert several elements into a v8i32 vector in avx2,
      // Case#1: inserting into 1th index needs vpinsrd + inserti128.
      // Case#2: inserting into 5th index needs extracti128 + vpinsrd +
      // inserti128.
      // Case#3: inserting into 4,5,6,7 index needs 4*vpinsrd + inserti128.
      const int CostValue = *LT.first.getValue();
      assert(CostValue >= 0 && "Negative cost!")((void)0);
      unsigned Num128Lanes = LT.second.getSizeInBits() / 128 * CostValue;
      unsigned NumElts = LT.second.getVectorNumElements() * CostValue;
      APInt WidenedDemandedElts = DemandedElts.zextOrSelf(NumElts);
      unsigned Scale = NumElts / Num128Lanes;
      // We iterate each 128-lane, and check if we need a
      // extracti128/inserti128 for this 128-lane.
      for (unsigned I = 0; I < NumElts; I += Scale) {
        APInt Mask = WidenedDemandedElts.getBitsSet(NumElts, I, I + Scale);
        APInt MaskedDE = Mask & WidenedDemandedElts;
        unsigned Population = MaskedDE.countPopulation();
        Cost += (Population > 0 && Population != Scale &&
                 I % LT.second.getVectorNumElements() != 0);
        Cost += Population > 0;
      }
      Cost += DemandedElts.countPopulation();

      // For vXf32 cases, insertion into the 0'th index in each v4f32
      // 128-bit vector is free.
      // NOTE: This assumes legalization widens vXf32 vectors.
      if (MScalarTy == MVT::f32)
        for (unsigned i = 0, e = cast<FixedVectorType>(Ty)->getNumElements();
             i < e; i += 4)
          if (DemandedElts[i])
            Cost--;
    }
  } else if (LT.second.isVector()) {
    // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded
    // integer element as a SCALAR_TO_VECTOR, then we build the vector as a
    // series of UNPCK followed by CONCAT_VECTORS - all of these can be
    // considered cheap.
    if (Ty->isIntOrIntVectorTy())
      Cost += DemandedElts.countPopulation();

    // Get the smaller of the legalized or original pow2-extended number of
    // vector elements, which represents the number of unpacks we'll end up
    // performing.
    unsigned NumElts = LT.second.getVectorNumElements();
    unsigned Pow2Elts =
        PowerOf2Ceil(cast<FixedVectorType>(Ty)->getNumElements());
    Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first;
  }
}

// TODO: Use default extraction for now, but we should investigate extending this
// to handle repeated subvector extraction.
if (Extract)
  Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract);

return Cost;
3506}

3508InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
                                          MaybeAlign Alignment,
                                          unsigned AddressSpace,
                                          TTI::TargetCostKind CostKind,
                                          const Instruction *I) {
// TODO: Handle other cost kinds.
if (CostKind != TTI::TCK_RecipThroughput) {
  if (auto *SI = dyn_cast_or_null<StoreInst>(I)) {
    // Store instruction with index and scale costs 2 Uops.
    // Check the preceding GEP to identify non-const indices.
    if (auto *GEP = dyn_cast<GetElementPtrInst>(SI->getPointerOperand())) {
      if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); }))
        return TTI::TCC_Basic * 2;
    }
  }
  return TTI::TCC_Basic;
}

assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&((void)0)
       "Invalid Opcode")((void)0);
// Type legalization can't handle structs
if (TLI->getValueType(DL, Src, true) == MVT::Other)
  return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
                                CostKind);

// Legalize the type.
std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);

auto *VTy = dyn_cast<FixedVectorType>(Src);

// Handle the simple case of non-vectors.
// NOTE: this assumes that legalization never creates vector from scalars!
if (!VTy || !LT.second.isVector())
  // Each load/store unit costs 1.
  return LT.first * 1;

bool IsLoad = Opcode == Instruction::Load;

Type *EltTy = VTy->getElementType();

const int EltTyBits = DL.getTypeSizeInBits(EltTy);

InstructionCost Cost = 0;

// Source of truth: how many elements were there in the original IR vector?
const unsigned SrcNumElt = VTy->getNumElements();

// How far have we gotten?
int NumEltRemaining = SrcNumElt;
// Note that we intentionally capture by-reference, NumEltRemaining changes.
auto NumEltDone = [&]() { return SrcNumElt - NumEltRemaining; };

const int MaxLegalOpSizeBytes = divideCeil(LT.second.getSizeInBits(), 8);

// Note that even if we can store 64 bits of an XMM, we still operate on XMM.
const unsigned XMMBits = 128;
if (XMMBits % EltTyBits != 0)
  // Vector size must be a multiple of the element size. I.e. no padding.
  return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
                                CostKind);
const int NumEltPerXMM = XMMBits / EltTyBits;

auto *XMMVecTy = FixedVectorType::get(EltTy, NumEltPerXMM);

for (int CurrOpSizeBytes = MaxLegalOpSizeBytes, SubVecEltsLeft = 0;
     NumEltRemaining > 0; CurrOpSizeBytes /= 2) {
  // How many elements would a single op deal with at once?
  if ((8 * CurrOpSizeBytes) % EltTyBits != 0)
    // Vector size must be a multiple of the element size. I.e. no padding.
    return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
                                  CostKind);
  int CurrNumEltPerOp = (8 * CurrOpSizeBytes) / EltTyBits;

  assert(CurrOpSizeBytes > 0 && CurrNumEltPerOp > 0 && "How'd we get here?")((void)0);
  assert((((NumEltRemaining * EltTyBits) < (2 * 8 * CurrOpSizeBytes)) ||((void)0)
          (CurrOpSizeBytes == MaxLegalOpSizeBytes)) &&((void)0)
         "Unless we haven't halved the op size yet, "((void)0)
         "we have less than two op's sized units of work left.")((void)0);

  auto *CurrVecTy = CurrNumEltPerOp > NumEltPerXMM
                        ? FixedVectorType::get(EltTy, CurrNumEltPerOp)
                        : XMMVecTy;

  assert(CurrVecTy->getNumElements() % CurrNumEltPerOp == 0 &&((void)0)
         "After halving sizes, the vector elt count is no longer a multiple "((void)0)
         "of number of elements per operation?")((void)0);
  auto *CoalescedVecTy =
      CurrNumEltPerOp == 1
          ? CurrVecTy
          : FixedVectorType::get(
                IntegerType::get(Src->getContext(),
                                 EltTyBits * CurrNumEltPerOp),
                CurrVecTy->getNumElements() / CurrNumEltPerOp);
  assert(DL.getTypeSizeInBits(CoalescedVecTy) ==((void)0)
             DL.getTypeSizeInBits(CurrVecTy) &&((void)0)
         "coalesciing elements doesn't change vector width.")((void)0);

  while (NumEltRemaining > 0) {
    assert(SubVecEltsLeft >= 0 && "Subreg element count overconsumtion?")((void)0);

    // Can we use this vector size, as per the remaining element count?
    // Iff the vector is naturally aligned, we can do a wide load regardless.
    if (NumEltRemaining < CurrNumEltPerOp &&
        (!IsLoad || Alignment.valueOrOne() < CurrOpSizeBytes) &&
        CurrOpSizeBytes != 1)
      break; // Try smalled vector size.

    bool Is0thSubVec = (NumEltDone() % LT.second.getVectorNumElements()) == 0;

    // If we have fully processed the previous reg, we need to replenish it.
    if (SubVecEltsLeft == 0) {
      SubVecEltsLeft += CurrVecTy->getNumElements();
      // And that's free only for the 0'th subvector of a legalized vector.
      if (!Is0thSubVec)
        Cost += getShuffleCost(IsLoad ? TTI::ShuffleKind::SK_InsertSubvector
                                      : TTI::ShuffleKind::SK_ExtractSubvector,
                               VTy, None, NumEltDone(), CurrVecTy);
    }

    // While we can directly load/store ZMM, YMM, and 64-bit halves of XMM,
    // for smaller widths (32/16/8) we have to insert/extract them separately.
    // Again, it's free for the 0'th subreg (if op is 32/64 bit wide,
    // but let's pretend that it is also true for 16/8 bit wide ops...)
    if (CurrOpSizeBytes <= 32 / 8 && !Is0thSubVec) {
      int NumEltDoneInCurrXMM = NumEltDone() % NumEltPerXMM;
      assert(NumEltDoneInCurrXMM % CurrNumEltPerOp == 0 && "")((void)0);
      int CoalescedVecEltIdx = NumEltDoneInCurrXMM / CurrNumEltPerOp;
      APInt DemandedElts =
          APInt::getBitsSet(CoalescedVecTy->getNumElements(),
                            CoalescedVecEltIdx, CoalescedVecEltIdx + 1);
      assert(DemandedElts.countPopulation() == 1 && "Inserting single value")((void)0);
      Cost += getScalarizationOverhead(CoalescedVecTy, DemandedElts, IsLoad,
                                       !IsLoad);
    }

    // This isn't exactly right. We're using slow unaligned 32-byte accesses
    // as a proxy for a double-pumped AVX memory interface such as on
    // Sandybridge.
    if (CurrOpSizeBytes == 32 && ST->isUnalignedMem32Slow())
      Cost += 2;
    else
      Cost += 1;

    SubVecEltsLeft -= CurrNumEltPerOp;
    NumEltRemaining -= CurrNumEltPerOp;
    Alignment = commonAlignment(Alignment.valueOrOne(), CurrOpSizeBytes);
  }
}

assert(NumEltRemaining <= 0 && "Should have processed all the elements.")((void)0);

return Cost;
3660}

3662InstructionCost
3663X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, Align Alignment,
                                unsigned AddressSpace,
                                TTI::TargetCostKind CostKind) {
bool IsLoad = (Instruction::Load == Opcode);
bool IsStore = (Instruction::Store == Opcode);

auto *SrcVTy = dyn_cast<FixedVectorType>(SrcTy);
if (!SrcVTy)
  // To calculate scalar take the regular cost, without mask
  return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace, CostKind);

unsigned NumElem = SrcVTy->getNumElements();
auto *MaskTy =
    FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem);
if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) ||
    (IsStore && !isLegalMaskedStore(SrcVTy, Alignment))) {
  // Scalarization
  APInt DemandedElts = APInt::getAllOnesValue(NumElem);
  InstructionCost MaskSplitCost =
      getScalarizationOverhead(MaskTy, DemandedElts, false, true);
  InstructionCost ScalarCompareCost = getCmpSelInstrCost(
      Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr,
      CmpInst::BAD_ICMP_PREDICATE, CostKind);
  InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind);
  InstructionCost MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost);
  InstructionCost ValueSplitCost =
      getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore);
  InstructionCost MemopCost =
      NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(),
                                       Alignment, AddressSpace, CostKind);
  return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost;
}

// Legalize the type.
std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy);
auto VT = TLI->getValueType(DL, SrcVTy);
InstructionCost Cost = 0;
if (VT.isSimple() && LT.second != VT.getSimpleVT() &&
    LT.second.getVectorNumElements() == NumElem)
  // Promotion requires extend/truncate for data and a shuffle for mask.
  Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, None, 0, nullptr) +
          getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, None, 0, nullptr);

else if (LT.first * LT.second.getVectorNumElements() > NumElem) {
  auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(),
                                         LT.second.getVectorNumElements());
  // Expanding requires fill mask with zeroes
  Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, None, 0, MaskTy);
}

// Pre-AVX512 - each maskmov load costs 2 + store costs ~8.
if (!ST->hasAVX512())
  return Cost + LT.first * (IsLoad ? 2 : 8);

// AVX-512 masked load/store is cheapper
return Cost + LT.first;
3719}

3721InstructionCost X86TTIImpl::getAddressComputationCost(Type *Ty,
                                                    ScalarEvolution *SE,
                                                    const SCEV *Ptr) {
// Address computations in vectorized code with non-consecutive addresses will
// likely result in more instructions compared to scalar code where the
// computation can more often be merged into the index mode. The resulting
// extra micro-ops can significantly decrease throughput.
const unsigned NumVectorInstToHideOverhead = 10;

// Cost modeling of Strided Access Computation is hidden by the indexing
// modes of X86 regardless of the stride value. We dont believe that there
// is a difference between constant strided access in gerenal and constant
// strided value which is less than or equal to 64.
// Even in the case of (loop invariant) stride whose value is not known at
// compile time, the address computation will not incur more than one extra
// ADD instruction.
if (Ty->isVectorTy() && SE) {
  if (!BaseT::isStridedAccess(Ptr))
    return NumVectorInstToHideOverhead;
  if (!BaseT::getConstantStrideStep(SE, Ptr))
    return 1;
}

return BaseT::getAddressComputationCost(Ty, SE, Ptr);
3745}

3747InstructionCost
3748X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy,
                                     Optional<FastMathFlags> FMF,
                                     TTI::TargetCostKind CostKind) {
if (TTI::requiresOrderedReduction(FMF))
  return BaseT::getArithmeticReductionCost(Opcode, ValTy, FMF, CostKind);

// We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
// and make it as the cost.

static const CostTblEntry SLMCostTblNoPairWise[] = {
  { ISD::FADD,  MVT::v2f64,   3 },
  { ISD::ADD,   MVT::v2i64,   5 },
};

static const CostTblEntry SSE2CostTblNoPairWise[] = {
  { ISD::FADD,  MVT::v2f64,   2 },
  { ISD::FADD,  MVT::v2f32,   2 },
  { ISD::FADD,  MVT::v4f32,   4 },
  { ISD::ADD,   MVT::v2i64,   2 },      // The data reported by the IACA tool is "1.6".
  { ISD::ADD,   MVT::v2i32,   2 }, // FIXME: chosen to be less than v4i32
  { ISD::ADD,   MVT::v4i32,   3 },      // The data reported by the IACA tool is "3.3".
  { ISD::ADD,   MVT::v2i16,   2 },      // The data reported by the IACA tool is "4.3".
  { ISD::ADD,   MVT::v4i16,   3 },      // The data reported by the IACA tool is "4.3".
  { ISD::ADD,   MVT::v8i16,   4 },      // The data reported by the IACA tool is "4.3".
  { ISD::ADD,   MVT::v2i8,    2 },
  { ISD::ADD,   MVT::v4i8,    2 },
  { ISD::ADD,   MVT::v8i8,    2 },
  { ISD::ADD,   MVT::v16i8,   3 },
};

static const CostTblEntry AVX1CostTblNoPairWise[] = {
  { ISD::FADD,  MVT::v4f64,   3 },
  { ISD::FADD,  MVT::v4f32,   3 },
  { ISD::FADD,  MVT::v8f32,   4 },
  { ISD::ADD,   MVT::v2i64,   1 },      // The data reported by the IACA tool is "1.5".
  { ISD::ADD,   MVT::v4i64,   3 },
  { ISD::ADD,   MVT::v8i32,   5 },
  { ISD::ADD,   MVT::v16i16,  5 },
  { ISD::ADD,   MVT::v32i8,   4 },
};

int ISD = TLI->InstructionOpcodeToISD(Opcode);
assert(ISD && "Invalid opcode")((void)0);

// Before legalizing the type, give a chance to look up illegal narrow types
// in the table.
// FIXME: Is there a better way to do this?
EVT VT = TLI->getValueType(DL, ValTy);
if (VT.isSimple()) {
  MVT MTy = VT.getSimpleVT();
  if (ST->isSLM())
    if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy))
      return Entry->Cost;

  if (ST->hasAVX())
    if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy))
      return Entry->Cost;

  if (ST->hasSSE2())
    if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy))
      return Entry->Cost;
}

std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);

MVT MTy = LT.second;

auto *ValVTy = cast<FixedVectorType>(ValTy);

// Special case: vXi8 mul reductions are performed as vXi16.
if (ISD == ISD::MUL && MTy.getScalarType() == MVT::i8) {
  auto *WideSclTy = IntegerType::get(ValVTy->getContext(), 16);
  auto *WideVecTy = FixedVectorType::get(WideSclTy, ValVTy->getNumElements());
  return getCastInstrCost(Instruction::ZExt, WideVecTy, ValTy,
                          TargetTransformInfo::CastContextHint::None,
                          CostKind) +
         getArithmeticReductionCost(Opcode, WideVecTy, FMF, CostKind);
}

InstructionCost ArithmeticCost = 0;
if (LT.first != 1 && MTy.isVector() &&
    MTy.getVectorNumElements() < ValVTy->getNumElements()) {
  // Type needs to be split. We need LT.first - 1 arithmetic ops.
  auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(),
                                          MTy.getVectorNumElements());
  ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind);
  ArithmeticCost *= LT.first - 1;
}

if (ST->isSLM())
  if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy))
    return ArithmeticCost + Entry->Cost;

if (ST->hasAVX())
  if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy))
    return ArithmeticCost + Entry->Cost;

if (ST->hasSSE2())
  if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy))
    return ArithmeticCost + Entry->Cost;

// FIXME: These assume a naive kshift+binop lowering, which is probably
// conservative in most cases.
static const CostTblEntry AVX512BoolReduction[] = {
  { ISD::AND,  MVT::v2i1,   3 },
  { ISD::AND,  MVT::v4i1,   5 },
  { ISD::AND,  MVT::v8i1,   7 },
  { ISD::AND,  MVT::v16i1,  9 },
  { ISD::AND,  MVT::v32i1, 11 },
  { ISD::AND,  MVT::v64i1, 13 },
  { ISD::OR,   MVT::v2i1,   3 },
  { ISD::OR,   MVT::v4i1,   5 },
  { ISD::OR,   MVT::v8i1,   7 },
  { ISD::OR,   MVT::v16i1,  9 },
  { ISD::OR,   MVT::v32i1, 11 },
  { ISD::OR,   MVT::v64i1, 13 },
};

static const CostTblEntry AVX2BoolReduction[] = {
  { ISD::AND,  MVT::v16i16,  2 }, // vpmovmskb + cmp
  { ISD::AND,  MVT::v32i8,   2 }, // vpmovmskb + cmp
  { ISD::OR,   MVT::v16i16,  2 }, // vpmovmskb + cmp
  { ISD::OR,   MVT::v32i8,   2 }, // vpmovmskb + cmp
};

static const CostTblEntry AVX1BoolReduction[] = {
  { ISD::AND,  MVT::v4i64,   2 }, // vmovmskpd + cmp
  { ISD::AND,  MVT::v8i32,   2 }, // vmovmskps + cmp
  { ISD::AND,  MVT::v16i16,  4 }, // vextractf128 + vpand + vpmovmskb + cmp
  { ISD::AND,  MVT::v32i8,   4 }, // vextractf128 + vpand + vpmovmskb + cmp
  { ISD::OR,   MVT::v4i64,   2 }, // vmovmskpd + cmp
  { ISD::OR,   MVT::v8i32,   2 }, // vmovmskps + cmp
  { ISD::OR,   MVT::v16i16,  4 }, // vextractf128 + vpor + vpmovmskb + cmp
  { ISD::OR,   MVT::v32i8,   4 }, // vextractf128 + vpor + vpmovmskb + cmp
};

static const CostTblEntry SSE2BoolReduction[] = {
  { ISD::AND,  MVT::v2i64,   2 }, // movmskpd + cmp
  { ISD::AND,  MVT::v4i32,   2 }, // movmskps + cmp
  { ISD::AND,  MVT::v8i16,   2 }, // pmovmskb + cmp
  { ISD::AND,  MVT::v16i8,   2 }, // pmovmskb + cmp
  { ISD::OR,   MVT::v2i64,   2 }, // movmskpd + cmp
  { ISD::OR,   MVT::v4i32,   2 }, // movmskps + cmp
  { ISD::OR,   MVT::v8i16,   2 }, // pmovmskb + cmp
  { ISD::OR,   MVT::v16i8,   2 }, // pmovmskb + cmp
};

// Handle bool allof/anyof patterns.
if (ValVTy->getElementType()->isIntegerTy(1)) {
  InstructionCost ArithmeticCost = 0;
  if (LT.first != 1 && MTy.isVector() &&
      MTy.getVectorNumElements() < ValVTy->getNumElements()) {
    // Type needs to be split. We need LT.first - 1 arithmetic ops.
    auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(),
                                            MTy.getVectorNumElements());
    ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind);
    ArithmeticCost *= LT.first - 1;
  }

  if (ST->hasAVX512())
    if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy))
      return ArithmeticCost + Entry->Cost;
  if (ST->hasAVX2())
    if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy))
      return ArithmeticCost + Entry->Cost;
  if (ST->hasAVX())
    if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy))
      return ArithmeticCost + Entry->Cost;
  if (ST->hasSSE2())
    if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy))
      return ArithmeticCost + Entry->Cost;

  return BaseT::getArithmeticReductionCost(Opcode, ValVTy, FMF, CostKind);
}

unsigned NumVecElts = ValVTy->getNumElements();
unsigned ScalarSize = ValVTy->getScalarSizeInBits();

// Special case power of 2 reductions where the scalar type isn't changed
// by type legalization.
if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits())
  return BaseT::getArithmeticReductionCost(Opcode, ValVTy, FMF, CostKind);

InstructionCost ReductionCost = 0;

auto *Ty = ValVTy;
if (LT.first != 1 && MTy.isVector() &&
    MTy.getVectorNumElements() < ValVTy->getNumElements()) {
  // Type needs to be split. We need LT.first - 1 arithmetic ops.
  Ty = FixedVectorType::get(ValVTy->getElementType(),
                            MTy.getVectorNumElements());
  ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind);
  ReductionCost *= LT.first - 1;
  NumVecElts = MTy.getVectorNumElements();
}

// Now handle reduction with the legal type, taking into account size changes
// at each level.
while (NumVecElts > 1) {
  // Determine the size of the remaining vector we need to reduce.
  unsigned Size = NumVecElts * ScalarSize;
  NumVecElts /= 2;
  // If we're reducing from 256/512 bits, use an extract_subvector.
  if (Size > 128) {
    auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts);
    ReductionCost +=
        getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy);
    Ty = SubTy;
  } else if (Size == 128) {
    // Reducing from 128 bits is a permute of v2f64/v2i64.
    FixedVectorType *ShufTy;
    if (ValVTy->isFloatingPointTy())
      ShufTy =
          FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2);
    else
      ShufTy =
          FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2);
    ReductionCost +=
        getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr);
  } else if (Size == 64) {
    // Reducing from 64 bits is a shuffle of v4f32/v4i32.
    FixedVectorType *ShufTy;
    if (ValVTy->isFloatingPointTy())
      ShufTy =
          FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4);
    else
      ShufTy =
          FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4);
    ReductionCost +=
        getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr);
  } else {
    // Reducing from smaller size is a shift by immediate.
    auto *ShiftTy = FixedVectorType::get(
        Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size);
    ReductionCost += getArithmeticInstrCost(
        Instruction::LShr, ShiftTy, CostKind,
        TargetTransformInfo::OK_AnyValue,
        TargetTransformInfo::OK_UniformConstantValue,
        TargetTransformInfo::OP_None, TargetTransformInfo::OP_None);
  }

  // Add the arithmetic op for this level.
  ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind);
}

// Add the final extract element to the cost.
return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0);
3995}

3997InstructionCost X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy,
                                        bool IsUnsigned) {
std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);

MVT MTy = LT.second;

int ISD;
if (Ty->isIntOrIntVectorTy()) {
  ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN;
} else {
  assert(Ty->isFPOrFPVectorTy() &&((void)0)
         "Expected float point or integer vector type.")((void)0);
  ISD = ISD::FMINNUM;
}

static const CostTblEntry SSE1CostTbl[] = {
  {ISD::FMINNUM, MVT::v4f32, 1},
};

static const CostTblEntry SSE2CostTbl[] = {
  {ISD::FMINNUM, MVT::v2f64, 1},
  {ISD::SMIN,    MVT::v8i16, 1},
  {ISD::UMIN,    MVT::v16i8, 1},
};

static const CostTblEntry SSE41CostTbl[] = {
  {ISD::SMIN,    MVT::v4i32, 1},
  {ISD::UMIN,    MVT::v4i32, 1},
  {ISD::UMIN,    MVT::v8i16, 1},
  {ISD::SMIN,    MVT::v16i8, 1},
};

static const CostTblEntry SSE42CostTbl[] = {
  {ISD::UMIN,    MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd
};

static const CostTblEntry AVX1CostTbl[] = {
  {ISD::FMINNUM, MVT::v8f32,  1},
  {ISD::FMINNUM, MVT::v4f64,  1},
  {ISD::SMIN,    MVT::v8i32,  3},
  {ISD::UMIN,    MVT::v8i32,  3},
  {ISD::SMIN,    MVT::v16i16, 3},
  {ISD::UMIN,    MVT::v16i16, 3},
  {ISD::SMIN,    MVT::v32i8,  3},
  {ISD::UMIN,    MVT::v32i8,  3},
};

static const CostTblEntry AVX2CostTbl[] = {
  {ISD::SMIN,    MVT::v8i32,  1},
  {ISD::UMIN,    MVT::v8i32,  1},
  {ISD::SMIN,    MVT::v16i16, 1},
  {ISD::UMIN,    MVT::v16i16, 1},
  {ISD::SMIN,    MVT::v32i8,  1},
  {ISD::UMIN,    MVT::v32i8,  1},
};

static const CostTblEntry AVX512CostTbl[] = {
  {ISD::FMINNUM, MVT::v16f32, 1},
  {ISD::FMINNUM, MVT::v8f64,  1},
  {ISD::SMIN,    MVT::v2i64,  1},
  {ISD::UMIN,    MVT::v2i64,  1},
  {ISD::SMIN,    MVT::v4i64,  1},
  {ISD::UMIN,    MVT::v4i64,  1},
  {ISD::SMIN,    MVT::v8i64,  1},
  {ISD::UMIN,    MVT::v8i64,  1},
  {ISD::SMIN,    MVT::v16i32, 1},
  {ISD::UMIN,    MVT::v16i32, 1},
};

static const CostTblEntry AVX512BWCostTbl[] = {
  {ISD::SMIN,    MVT::v32i16, 1},
  {ISD::UMIN,    MVT::v32i16, 1},
  {ISD::SMIN,    MVT::v64i8,  1},
  {ISD::UMIN,    MVT::v64i8,  1},
};

// If we have a native MIN/MAX instruction for this type, use it.
if (ST->hasBWI())
  if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
    return LT.first * Entry->Cost;

if (ST->hasAVX512())
  if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
    return LT.first * Entry->Cost;

if (ST->hasAVX2())
  if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy))
    return LT.first * Entry->Cost;

if (ST->hasAVX())
  if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
    return LT.first * Entry->Cost;

if (ST->hasSSE42())
  if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy))
    return LT.first * Entry->Cost;

if (ST->hasSSE41())
  if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy))
    return LT.first * Entry->Cost;

if (ST->hasSSE2())
  if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
    return LT.first * Entry->Cost;

if (ST->hasSSE1())
  if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy))
    return LT.first * Entry->Cost;

unsigned CmpOpcode;
if (Ty->isFPOrFPVectorTy()) {
  CmpOpcode = Instruction::FCmp;
} else {
  assert(Ty->isIntOrIntVectorTy() &&((void)0)
         "expecting floating point or integer type for min/max reduction")((void)0);
  CmpOpcode = Instruction::ICmp;
}

TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput;
// Otherwise fall back to cmp+select.
InstructionCost Result =
    getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CmpInst::BAD_ICMP_PREDICATE,
                       CostKind) +
    getCmpSelInstrCost(Instruction::Select, Ty, CondTy,
                       CmpInst::BAD_ICMP_PREDICATE, CostKind);
return Result;
4123}

4125InstructionCost
4126X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy,
                                 bool IsUnsigned,
                                 TTI::TargetCostKind CostKind) {
std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);

MVT MTy = LT.second;

int ISD;
if (ValTy->isIntOrIntVectorTy()) {
  ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN;
} else {
  assert(ValTy->isFPOrFPVectorTy() &&((void)0)
         "Expected float point or integer vector type.")((void)0);
  ISD = ISD::FMINNUM;
}

// We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
// and make it as the cost.

static const CostTblEntry SSE2CostTblNoPairWise[] = {
    {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw
    {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw
    {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw
};

static const CostTblEntry SSE41CostTblNoPairWise[] = {
    {ISD::SMIN, MVT::v2i16, 3}, // same as sse2
    {ISD::SMIN, MVT::v4i16, 5}, // same as sse2
    {ISD::UMIN, MVT::v2i16, 5}, // same as sse2
    {ISD::UMIN, MVT::v4i16, 7}, // same as sse2
    {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor
    {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax
    {ISD::SMIN, MVT::v2i8,  3}, // pminsb
    {ISD::SMIN, MVT::v4i8,  5}, // pminsb
    {ISD::SMIN, MVT::v8i8,  7}, // pminsb
    {ISD::SMIN, MVT::v16i8, 6},
    {ISD::UMIN, MVT::v2i8,  3}, // same as sse2
    {ISD::UMIN, MVT::v4i8,  5}, // same as sse2
    {ISD::UMIN, MVT::v8i8,  7}, // same as sse2
    {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax
};

static const CostTblEntry AVX1CostTblNoPairWise[] = {
    {ISD::SMIN, MVT::v16i16, 6},
    {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax
    {ISD::SMIN, MVT::v32i8, 8},
    {ISD::UMIN, MVT::v32i8, 8},
};

static const CostTblEntry AVX512BWCostTblNoPairWise[] = {
    {ISD::SMIN, MVT::v32i16, 8},
    {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax
    {ISD::SMIN, MVT::v64i8, 10},
    {ISD::UMIN, MVT::v64i8, 10},
};

// Before legalizing the type, give a chance to look up illegal narrow types
// in the table.
// FIXME: Is there a better way to do this?
EVT VT = TLI->getValueType(DL, ValTy);
if (VT.isSimple()) {
  MVT MTy = VT.getSimpleVT();
  if (ST->hasBWI())
    if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy))
      return Entry->Cost;

  if (ST->hasAVX())
    if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy))
      return Entry->Cost;

  if (ST->hasSSE41())
    if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy))
      return Entry->Cost;

  if (ST->hasSSE2())
    if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy))
      return Entry->Cost;
}

auto *ValVTy = cast<FixedVectorType>(ValTy);
unsigned NumVecElts = ValVTy->getNumElements();

auto *Ty = ValVTy;
InstructionCost MinMaxCost = 0;
if (LT.first != 1 && MTy.isVector() &&
    MTy.getVectorNumElements() < ValVTy->getNumElements()) {
  // Type needs to be split. We need LT.first - 1 operations ops.
  Ty = FixedVectorType::get(ValVTy->getElementType(),
                            MTy.getVectorNumElements());
  auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(),
                                         MTy.getVectorNumElements());
  MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned);
  MinMaxCost *= LT.first - 1;
  NumVecElts = MTy.getVectorNumElements();
}

if (ST->hasBWI())
  if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy))
    return MinMaxCost + Entry->Cost;

if (ST->hasAVX())
  if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy))
    return MinMaxCost + Entry->Cost;

if (ST->hasSSE41())
  if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy))
    return MinMaxCost + Entry->Cost;

if (ST->hasSSE2())
  if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy))
    return MinMaxCost + Entry->Cost;

unsigned ScalarSize = ValTy->getScalarSizeInBits();

// Special case power of 2 reductions where the scalar type isn't changed
// by type legalization.
if (!isPowerOf2_32(ValVTy->getNumElements()) ||
    ScalarSize != MTy.getScalarSizeInBits())
  return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsUnsigned, CostKind);

// Now handle reduction with the legal type, taking into account size changes
// at each level.
while (NumVecElts > 1) {
  // Determine the size of the remaining vector we need to reduce.
  unsigned Size = NumVecElts * ScalarSize;
  NumVecElts /= 2;
  // If we're reducing from 256/512 bits, use an extract_subvector.
  if (Size > 128) {
    auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts);
    MinMaxCost +=
        getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy);
    Ty = SubTy;
  } else if (Size == 128) {
    // Reducing from 128 bits is a permute of v2f64/v2i64.
    VectorType *ShufTy;
    if (ValTy->isFloatingPointTy())
      ShufTy =
          FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2);
    else
      ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2);
    MinMaxCost +=
        getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr);
  } else if (Size == 64) {
    // Reducing from 64 bits is a shuffle of v4f32/v4i32.
    FixedVectorType *ShufTy;
    if (ValTy->isFloatingPointTy())
      ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4);
    else
      ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4);
    MinMaxCost +=
        getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr);
  } else {
    // Reducing from smaller size is a shift by immediate.
    auto *ShiftTy = FixedVectorType::get(
        Type::getIntNTy(ValTy->getContext(), Size), 128 / Size);
    MinMaxCost += getArithmeticInstrCost(
        Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput,
        TargetTransformInfo::OK_AnyValue,
        TargetTransformInfo::OK_UniformConstantValue,
        TargetTransformInfo::OP_None, TargetTransformInfo::OP_None);
  }

  // Add the arithmetic op for this level.
  auto *SubCondTy =
      FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements());
  MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned);
}

// Add the final extract element to the cost.
return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0);
4296}

4298/// Calculate the cost of materializing a 64-bit value. This helper
4299/// method might only calculate a fraction of a larger immediate. Therefore it
4300/// is valid to return a cost of ZERO.
4301InstructionCost X86TTIImpl::getIntImmCost(int64_t Val) {
if (Val == 0)
  return TTI::TCC_Free;

if (isInt<32>(Val))
  return TTI::TCC_Basic;

return 2 * TTI::TCC_Basic;
4309}

4311InstructionCost X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty,
                                        TTI::TargetCostKind CostKind) {
assert(Ty->isIntegerTy())((void)0);

unsigned BitSize = Ty->getPrimitiveSizeInBits();
if (BitSize == 0)
  return ~0U;

// Never hoist constants larger than 128bit, because this might lead to
// incorrect code generation or assertions in codegen.
// Fixme: Create a cost model for types larger than i128 once the codegen
// issues have been fixed.
if (BitSize > 128)
  return TTI::TCC_Free;

if (Imm == 0)
  return TTI::TCC_Free;

// Sign-extend all constants to a multiple of 64-bit.
APInt ImmVal = Imm;
if (BitSize % 64 != 0)
  ImmVal = Imm.sext(alignTo(BitSize, 64));

// Split the constant into 64-bit chunks and calculate the cost for each
// chunk.
InstructionCost Cost = 0;
for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) {
  APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64);
  int64_t Val = Tmp.getSExtValue();
  Cost += getIntImmCost(Val);
}
// We need at least one instruction to materialize the constant.
return std::max<InstructionCost>(1, Cost);
4344}

4346InstructionCost X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
                                            const APInt &Imm, Type *Ty,
                                            TTI::TargetCostKind CostKind,
                                            Instruction *Inst) {
assert(Ty->isIntegerTy())((void)0);

unsigned BitSize = Ty->getPrimitiveSizeInBits();
// There is no cost model for constants with a bit size of 0. Return TCC_Free
// here, so that constant hoisting will ignore this constant.
if (BitSize == 0)
  return TTI::TCC_Free;

unsigned ImmIdx = ~0U;
switch (Opcode) {
default:
  return TTI::TCC_Free;
case Instruction::GetElementPtr:
  // Always hoist the base address of a GetElementPtr. This prevents the
  // creation of new constants for every base constant that gets constant
  // folded with the offset.
  if (Idx == 0)
    return 2 * TTI::TCC_Basic;
  return TTI::TCC_Free;
case Instruction::Store:
  ImmIdx = 0;
  break;
case Instruction::ICmp:
  // This is an imperfect hack to prevent constant hoisting of
  // compares that might be trying to check if a 64-bit value fits in
  // 32-bits. The backend can optimize these cases using a right shift by 32.
  // Ideally we would check the compare predicate here. There also other
  // similar immediates the backend can use shifts for.
  if (Idx == 1 && Imm.getBitWidth() == 64) {
    uint64_t ImmVal = Imm.getZExtValue();
    if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff)
      return TTI::TCC_Free;
  }
  ImmIdx = 1;
  break;
case Instruction::And:
  // We support 64-bit ANDs with immediates with 32-bits of leading zeroes
  // by using a 32-bit operation with implicit zero extension. Detect such
  // immediates here as the normal path expects bit 31 to be sign extended.
  if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue()))
    return TTI::TCC_Free;
  ImmIdx = 1;
  break;
case Instruction::Add:
case Instruction::Sub:
  // For add/sub, we can use the opposite instruction for INT32_MIN.
  if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000)
    return TTI::TCC_Free;
  ImmIdx = 1;
  break;
case Instruction::UDiv:
case Instruction::SDiv:
case Instruction::URem:
case Instruction::SRem:
  // Division by constant is typically expanded later into a different
  // instruction sequence. This completely changes the constants.
  // Report them as "free" to stop ConstantHoist from marking them as opaque.
  return TTI::TCC_Free;
case Instruction::Mul:
case Instruction::Or:
case Instruction::Xor:
  ImmIdx = 1;
  break;
// Always return TCC_Free for the shift value of a shift instruction.
case Instruction::Shl:
case Instruction::LShr:
case Instruction::AShr:
  if (Idx == 1)
    return TTI::TCC_Free;
  break;
case Instruction::Trunc:
case Instruction::ZExt:
case Instruction::SExt:
case Instruction::IntToPtr:
case Instruction::PtrToInt:
case Instruction::BitCast:
case Instruction::PHI:
case Instruction::Call:
case Instruction::Select:
case Instruction::Ret:
case Instruction::Load:
  break;
}

if (Idx == ImmIdx) {
  int NumConstants = divideCeil(BitSize, 64);
  InstructionCost Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind);
  return (Cost <= NumConstants * TTI::TCC_Basic)
             ? static_cast<int>(TTI::TCC_Free)
             : Cost;
}

return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind);
4443}

4445InstructionCost X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
                                              const APInt &Imm, Type *Ty,
                                              TTI::TargetCostKind CostKind) {
assert(Ty->isIntegerTy())((void)0);

unsigned BitSize = Ty->getPrimitiveSizeInBits();
// There is no cost model for constants with a bit size of 0. Return TCC_Free
// here, so that constant hoisting will ignore this constant.
if (BitSize == 0)
  return TTI::TCC_Free;

switch (IID) {
default:
  return TTI::TCC_Free;
case Intrinsic::sadd_with_overflow:
case Intrinsic::uadd_with_overflow:
case Intrinsic::ssub_with_overflow:
case Intrinsic::usub_with_overflow:
case Intrinsic::smul_with_overflow:
case Intrinsic::umul_with_overflow:
  if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue()))
    return TTI::TCC_Free;
  break;
case Intrinsic::experimental_stackmap:
  if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
    return TTI::TCC_Free;
  break;
case Intrinsic::experimental_patchpoint_void:
case Intrinsic::experimental_patchpoint_i64:
  if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
    return TTI::TCC_Free;
  break;
}
return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind);
4479}

4481InstructionCost X86TTIImpl::getCFInstrCost(unsigned Opcode,
                                         TTI::TargetCostKind CostKind,
                                         const Instruction *I) {
if (CostKind != TTI::TCK_RecipThroughput)
  return Opcode == Instruction::PHI ? 0 : 1;
// Branches are assumed to be predicted.
return 0;
4488}

4490int X86TTIImpl::getGatherOverhead() const {
// Some CPUs have more overhead for gather. The specified overhead is relative
// to the Load operation. "2" is the number provided by Intel architects. This
// parameter is used for cost estimation of Gather Op and comparison with
// other alternatives.
// TODO: Remove the explicit hasAVX512()?, That would mean we would only
// enable gather with a -march.
if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather()))
  return 2;

return 1024;
4501}

4503int X86TTIImpl::getScatterOverhead() const {
if (ST->hasAVX512())
  return 2;

return 1024;
4508}

4510// Return an average cost of Gather / Scatter instruction, maybe improved later.
4511// FIXME: Add TargetCostKind support.
4512InstructionCost X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy,
                                          const Value *Ptr, Align Alignment,
                                          unsigned AddressSpace) {

assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost")((void)0);
unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements();

// Try to reduce index size from 64 bit (default for GEP)
// to 32. It is essential for VF 16. If the index can't be reduced to 32, the
// operation will use 16 x 64 indices which do not fit in a zmm and needs
// to split. Also check that the base pointer is the same for all lanes,
// and that there's at most one variable index.
auto getIndexSizeInBits = [](const Value *Ptr, const DataLayout &DL) {
  unsigned IndexSize = DL.getPointerSizeInBits();
  const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
  if (IndexSize < 64 || !GEP)
    return IndexSize;

  unsigned NumOfVarIndices = 0;
  const Value *Ptrs = GEP->getPointerOperand();
  if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs))
    return IndexSize;
  for (unsigned i = 1; i < GEP->getNumOperands(); ++i) {
    if (isa<Constant>(GEP->getOperand(i)))
      continue;
    Type *IndxTy = GEP->getOperand(i)->getType();
    if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy))
      IndxTy = IndexVTy->getElementType();
    if ((IndxTy->getPrimitiveSizeInBits() == 64 &&
        !isa<SExtInst>(GEP->getOperand(i))) ||
       ++NumOfVarIndices > 1)
      return IndexSize; // 64
  }
  return (unsigned)32;
};

// Trying to reduce IndexSize to 32 bits for vector 16.
// By default the IndexSize is equal to pointer size.
unsigned IndexSize = (ST->hasAVX512() && VF >= 16)
                         ? getIndexSizeInBits(Ptr, DL)
                         : DL.getPointerSizeInBits();

auto *IndexVTy = FixedVectorType::get(
    IntegerType::get(SrcVTy->getContext(), IndexSize), VF);
std::pair<InstructionCost, MVT> IdxsLT =
    TLI->getTypeLegalizationCost(DL, IndexVTy);
std::pair<InstructionCost, MVT> SrcLT =
    TLI->getTypeLegalizationCost(DL, SrcVTy);
InstructionCost::CostType SplitFactor =
    *std::max(IdxsLT.first, SrcLT.first).getValue();
if (SplitFactor > 1) {
  // Handle splitting of vector of pointers
  auto *SplitSrcTy =
      FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor);
  return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment,
                                       AddressSpace);
}

// The gather / scatter cost is given by Intel architects. It is a rough
// number since we are looking at one instruction in a time.
const int GSOverhead = (Opcode == Instruction::Load)
                           ? getGatherOverhead()
                           : getScatterOverhead();
return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(),
                                         MaybeAlign(Alignment), AddressSpace,
                                         TTI::TCK_RecipThroughput);
4578}

4580/// Return the cost of full scalarization of gather / scatter operation.
4581///
4582/// Opcode - Load or Store instruction.
4583/// SrcVTy - The type of the data vector that should be gathered or scattered.
4584/// VariableMask - The mask is non-constant at compile time.
4585/// Alignment - Alignment for one element.
4586/// AddressSpace - pointer[s] address space.
4587///
4588/// FIXME: Add TargetCostKind support.
4589InstructionCost X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy,
                                          bool VariableMask, Align Alignment,
                                          unsigned AddressSpace) {
unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements();
APInt DemandedElts = APInt::getAllOnesValue(VF);
TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput;

InstructionCost MaskUnpackCost = 0;
if (VariableMask) {
  auto *MaskTy =
      FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF);
  MaskUnpackCost =
      getScalarizationOverhead(MaskTy, DemandedElts, false, true);
  InstructionCost ScalarCompareCost = getCmpSelInstrCost(
      Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), nullptr,
      CmpInst::BAD_ICMP_PREDICATE, CostKind);
  InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind);
  MaskUnpackCost += VF * (BranchCost + ScalarCompareCost);
}

// The cost of the scalar loads/stores.
InstructionCost MemoryOpCost =
    VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(),
                         MaybeAlign(Alignment), AddressSpace, CostKind);

InstructionCost InsertExtractCost = 0;
if (Opcode == Instruction::Load)
  for (unsigned i = 0; i < VF; ++i)
    // Add the cost of inserting each scalar load into the vector
    InsertExtractCost +=
      getVectorInstrCost(Instruction::InsertElement, SrcVTy, i);
else
  for (unsigned i = 0; i < VF; ++i)
    // Add the cost of extracting each element out of the data vector
    InsertExtractCost +=
      getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i);

return MemoryOpCost + MaskUnpackCost + InsertExtractCost;
4627}

4629/// Calculate the cost of Gather / Scatter operation
4630InstructionCost X86TTIImpl::getGatherScatterOpCost(
  unsigned Opcode, Type *SrcVTy, const Value *Ptr, bool VariableMask,
  Align Alignment, TTI::TargetCostKind CostKind,
  const Instruction *I = nullptr) {
if (CostKind != TTI::TCK_RecipThroughput) {
  if ((Opcode == Instruction::Load &&
       isLegalMaskedGather(SrcVTy, Align(Alignment))) ||
      (Opcode == Instruction::Store &&
       isLegalMaskedScatter(SrcVTy, Align(Alignment))))
    return 1;
  return BaseT::getGatherScatterOpCost(Opcode, SrcVTy, Ptr, VariableMask,
                                       Alignment, CostKind, I);
}

assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter")((void)0);
PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType());
if (!PtrTy && Ptr->getType()->isVectorTy())
  PtrTy = dyn_cast<PointerType>(
      cast<VectorType>(Ptr->getType())->getElementType());
assert(PtrTy && "Unexpected type for Ptr argument")((void)0);
unsigned AddressSpace = PtrTy->getAddressSpace();

if ((Opcode == Instruction::Load &&
     !isLegalMaskedGather(SrcVTy, Align(Alignment))) ||
    (Opcode == Instruction::Store &&
     !isLegalMaskedScatter(SrcVTy, Align(Alignment))))
  return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment,
                         AddressSpace);

return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace);
4660}

4662bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1,
                             TargetTransformInfo::LSRCost &C2) {
  // X86 specific here are "instruction number 1st priority".
  return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost,
                  C1.NumIVMuls, C1.NumBaseAdds,
                  C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
         std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost,
                  C2.NumIVMuls, C2.NumBaseAdds,
                  C2.ScaleCost, C2.ImmCost, C2.SetupCost);
4671}

4673bool X86TTIImpl::canMacroFuseCmp() {
return ST->hasMacroFusion() || ST->hasBranchFusion();
4675}

4677bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment) {
if (!ST->hasAVX())
  return false;

// The backend can't handle a single element vector.
if (isa<VectorType>(DataTy) &&
    cast<FixedVectorType>(DataTy)->getNumElements() == 1)
  return false;
Type *ScalarTy = DataTy->getScalarType();

if (ScalarTy->isPointerTy())
  return true;

if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy())
  return true;

if (!ScalarTy->isIntegerTy())
  return false;

unsigned IntWidth = ScalarTy->getIntegerBitWidth();
return IntWidth == 32 || IntWidth == 64 ||
       ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI());
4699}

4701bool X86TTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment) {
return isLegalMaskedLoad(DataType, Alignment);
4703}

4705bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) {
unsigned DataSize = DL.getTypeStoreSize(DataType);
// The only supported nontemporal loads are for aligned vectors of 16 or 32
// bytes.  Note that 32-byte nontemporal vector loads are supported by AVX2
// (the equivalent stores only require AVX).
if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32))
  return DataSize == 16 ?  ST->hasSSE1() : ST->hasAVX2();

return false;
4714}

4716bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) {
unsigned DataSize = DL.getTypeStoreSize(DataType);

// SSE4A supports nontemporal stores of float and double at arbitrary
// alignment.
if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy()))
  return true;

// Besides the SSE4A subtarget exception above, only aligned stores are
// available nontemporaly on any other subtarget.  And only stores with a size
// of 4..32 bytes (powers of 2, only) are permitted.
if (Alignment < DataSize || DataSize < 4 || DataSize > 32 ||
    !isPowerOf2_32(DataSize))
  return false;

// 32-byte vector nontemporal stores are supported by AVX (the equivalent
// loads require AVX2).
if (DataSize == 32)
  return ST->hasAVX();
else if (DataSize == 16)
  return ST->hasSSE1();
return true;
4738}

4740bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) {
if (!isa<VectorType>(DataTy))
  return false;

if (!ST->hasAVX512())
  return false;

// The backend can't handle a single element vector.
if (cast<FixedVectorType>(DataTy)->getNumElements() == 1)
  return false;

Type *ScalarTy = cast<VectorType>(DataTy)->getElementType();

if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy())
  return true;

if (!ScalarTy->isIntegerTy())
  return false;

unsigned IntWidth = ScalarTy->getIntegerBitWidth();
return IntWidth == 32 || IntWidth == 64 ||
       ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2());
4762}

4764bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) {
return isLegalMaskedExpandLoad(DataTy);
4766}

4768bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, Align Alignment) {
// Some CPUs have better gather performance than others.
// TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only
// enable gather with a -march.
if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2())))
  return false;

// This function is called now in two cases: from the Loop Vectorizer
// and from the Scalarizer.
// When the Loop Vectorizer asks about legality of the feature,
// the vectorization factor is not calculated yet. The Loop Vectorizer
// sends a scalar type and the decision is based on the width of the
// scalar element.
// Later on, the cost model will estimate usage this intrinsic based on
// the vector type.
// The Scalarizer asks again about legality. It sends a vector type.
// In this case we can reject non-power-of-2 vectors.
// We also reject single element vectors as the type legalizer can't
// scalarize it.
if (auto *DataVTy = dyn_cast<FixedVectorType>(DataTy)) {
  unsigned NumElts = DataVTy->getNumElements();
  if (NumElts == 1)
    return false;
  // Gather / Scatter for vector 2 is not profitable on KNL / SKX
  // Vector-4 of gather/scatter instruction does not exist on KNL.
  // We can extend it to 8 elements, but zeroing upper bits of
  // the mask vector will add more instructions. Right now we give the scalar
  // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter
  // instruction is better in the VariableMask case.
  if (ST->hasAVX512() && (NumElts == 2 || (NumElts == 4 && !ST->hasVLX())))
    return false;
}
Type *ScalarTy = DataTy->getScalarType();
if (ScalarTy->isPointerTy())
  return true;

if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy())
  return true;

if (!ScalarTy->isIntegerTy())
  return false;

unsigned IntWidth = ScalarTy->getIntegerBitWidth();
return IntWidth == 32 || IntWidth == 64;
4812}

4814bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, Align Alignment) {
// AVX2 doesn't support scatter
if (!ST->hasAVX512())
  return false;
return isLegalMaskedGather(DataType, Alignment);
4819}

4821bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) {
EVT VT = TLI->getValueType(DL, DataType);
return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT);
4824}

4826bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) {
return false;
4828}

4830bool X86TTIImpl::areInlineCompatible(const Function *Caller,
                                   const Function *Callee) const {
const TargetMachine &TM = getTLI()->getTargetMachine();

// Work this as a subsetting of subtarget features.
const FeatureBitset &CallerBits =
    TM.getSubtargetImpl(*Caller)->getFeatureBits();
const FeatureBitset &CalleeBits =
    TM.getSubtargetImpl(*Callee)->getFeatureBits();

FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList;
FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList;
return (RealCallerBits & RealCalleeBits) == RealCalleeBits;
4843}

4845bool X86TTIImpl::areFunctionArgsABICompatible(
  const Function *Caller, const Function *Callee,
  SmallPtrSetImpl<Argument *> &Args) const {
if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args))
  return false;

// If we get here, we know the target features match. If one function
// considers 512-bit vectors legal and the other does not, consider them
// incompatible.
const TargetMachine &TM = getTLI()->getTargetMachine();

if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() ==
    TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs())
  return true;

// Consider the arguments compatible if they aren't vectors or aggregates.
// FIXME: Look at the size of vectors.
// FIXME: Look at the element types of aggregates to see if there are vectors.
// FIXME: The API of this function seems intended to allow arguments
// to be removed from the set, but the caller doesn't check if the set
// becomes empty so that may not work in practice.
return llvm::none_of(Args, [](Argument *A) {
  auto *EltTy = cast<PointerType>(A->getType())->getElementType();
  return EltTy->isVectorTy() || EltTy->isAggregateType();
});
4870}

4872X86TTIImpl::TTI::MemCmpExpansionOptions
4873X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
TTI::MemCmpExpansionOptions Options;
Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize);
Options.NumLoadsPerBlock = 2;
// All GPR and vector loads can be unaligned.
Options.AllowOverlappingLoads = true;
if (IsZeroCmp) {
  // Only enable vector loads for equality comparison. Right now the vector
  // version is not as fast for three way compare (see #33329).
  const unsigned PreferredWidth = ST->getPreferVectorWidth();
  if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64);
  if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32);
  if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16);
}
if (ST->is64Bit()) {
  Options.LoadSizes.push_back(8);
}
Options.LoadSizes.push_back(4);
Options.LoadSizes.push_back(2);
Options.LoadSizes.push_back(1);
return Options;
4894}

4896bool X86TTIImpl::enableInterleavedAccessVectorization() {
// TODO: We expect this to be beneficial regardless of arch,
// but there are currently some unexplained performance artifacts on Atom.
// As a temporary solution, disable on Atom.
return !(ST->isAtom());
4901}

4903// Get estimation for interleaved load/store operations for AVX2.
4904// \p Factor is the interleaved-access factor (stride) - number of
4905// (interleaved) elements in the group.
4906// \p Indices contains the indices for a strided load: when the
4907// interleaved load has gaps they indicate which elements are used.
4908// If Indices is empty (or if the number of indices is equal to the size
4909// of the interleaved-access as given in \p Factor) the access has no gaps.
4910//
4911// As opposed to AVX-512, AVX2 does not have generic shuffles that allow
4912// computing the cost using a generic formula as a function of generic
4913// shuffles. We therefore use a lookup table instead, filled according to
4914// the instruction sequences that codegen currently generates.
4915InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2(
  unsigned Opcode, FixedVectorType *VecTy, unsigned Factor,
  ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace,
  TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) {

if (UseMaskForCond || UseMaskForGaps)
  return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
                                           Alignment, AddressSpace, CostKind,
                                           UseMaskForCond, UseMaskForGaps);

// We currently Support only fully-interleaved groups, with no gaps.
// TODO: Support also strided loads (interleaved-groups with gaps).
if (Indices.size() && Indices.size() != Factor)
  return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
                                           Alignment, AddressSpace, CostKind);

// VecTy for interleave memop is <VF*Factor x Elt>.
// So, for VF=4, Interleave Factor = 3, Element type = i32 we have
// VecTy = <12 x i32>.
MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second;

// This function can be called with VecTy=<6xi128>, Factor=3, in which case
// the VF=2, while v2i128 is an unsupported MVT vector type
// (see MachineValueType.h::getVectorVT()).
if (!LegalVT.isVector())
  return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
                                           Alignment, AddressSpace, CostKind);

unsigned VF = VecTy->getNumElements() / Factor;
Type *ScalarTy = VecTy->getElementType();
// Deduplicate entries, model floats/pointers as appropriately-sized integers.
if (!ScalarTy->isIntegerTy())
  ScalarTy =
      Type::getIntNTy(ScalarTy->getContext(), DL.getTypeSizeInBits(ScalarTy));

// Get the cost of all the memory operations.
InstructionCost MemOpCosts = getMemoryOpCost(
    Opcode, VecTy, MaybeAlign(Alignment), AddressSpace, CostKind);

auto *VT = FixedVectorType::get(ScalarTy, VF);
EVT ETy = TLI->getValueType(DL, VT);
if (!ETy.isSimple())
  return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
                                           Alignment, AddressSpace, CostKind);

// TODO: Complete for other data-types and strides.
// Each combination of Stride, element bit width and VF results in a different
// sequence; The cost tables are therefore accessed with:
// Factor (stride) and VectorType=VFxiN.
// The Cost accounts only for the shuffle sequence;
// The cost of the loads/stores is accounted for separately.
//
static const CostTblEntry AVX2InterleavedLoadTbl[] = {
    {2, MVT::v4i64, 6}, // (load 8i64 and) deinterleave into 2 x 4i64

    {3, MVT::v2i8, 10},  // (load 6i8 and) deinterleave into 3 x 2i8
    {3, MVT::v4i8, 4},   // (load 12i8 and) deinterleave into 3 x 4i8
    {3, MVT::v8i8, 9},   // (load 24i8 and) deinterleave into 3 x 8i8
    {3, MVT::v16i8, 11}, // (load 48i8 and) deinterleave into 3 x 16i8
    {3, MVT::v32i8, 13}, // (load 96i8 and) deinterleave into 3 x 32i8

    {3, MVT::v8i32, 17}, // (load 24i32 and) deinterleave into 3 x 8i32

    {4, MVT::v2i8, 12},  // (load 8i8 and) deinterleave into 4 x 2i8
    {4, MVT::v4i8, 4},   // (load 16i8 and) deinterleave into 4 x 4i8
    {4, MVT::v8i8, 20},  // (load 32i8 and) deinterleave into 4 x 8i8
    {4, MVT::v16i8, 39}, // (load 64i8 and) deinterleave into 4 x 16i8
    {4, MVT::v32i8, 80}, // (load 128i8 and) deinterleave into 4 x 32i8

    {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32
};

static const CostTblEntry AVX2InterleavedStoreTbl[] = {
    {2, MVT::v4i64, 6}, // interleave 2 x 4i64 into 8i64 (and store)

    {3, MVT::v2i8, 7},   // interleave 3 x 2i8 into 6i8 (and store)
    {3, MVT::v4i8, 8},   // interleave 3 x 4i8 into 12i8 (and store)
    {3, MVT::v8i8, 11},  // interleave 3 x 8i8 into 24i8 (and store)
    {3, MVT::v16i8, 11}, // interleave 3 x 16i8 into 48i8 (and store)
    {3, MVT::v32i8, 13}, // interleave 3 x 32i8 into 96i8 (and store)

    {4, MVT::v2i8, 12},  // interleave 4 x 2i8 into 8i8 (and store)
    {4, MVT::v4i8, 9},   // interleave 4 x 4i8 into 16i8 (and store)
    {4, MVT::v8i8, 10},  // interleave 4 x 8i8 into 32i8 (and store)
    {4, MVT::v16i8, 10}, // interleave 4 x 16i8 into 64i8 (and store)
    {4, MVT::v32i8, 12}  // interleave 4 x 32i8 into 128i8 (and store)
};

if (Opcode == Instruction::Load) {
  if (const auto *Entry =
          CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT()))
    return MemOpCosts + Entry->Cost;
} else {
  assert(Opcode == Instruction::Store &&((void)0)
         "Expected Store Instruction at this  point")((void)0);
  if (const auto *Entry =
          CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT()))
    return MemOpCosts + Entry->Cost;
}

return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
                                         Alignment, AddressSpace, CostKind);
5017}

5019// Get estimation for interleaved load/store operations and strided load.
5020// \p Indices contains indices for strided load.
5021// \p Factor - the factor of interleaving.
5022// AVX-512 provides 3-src shuffles that significantly reduces the cost.
5023InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX512(
  unsigned Opcode, FixedVectorType *VecTy, unsigned Factor,
  ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace,
  TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) {

if (UseMaskForCond || UseMaskForGaps)
  return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
                                           Alignment, AddressSpace, CostKind,
                                           UseMaskForCond, UseMaskForGaps);

// VecTy for interleave memop is <VF*Factor x Elt>.
// So, for VF=4, Interleave Factor = 3, Element type = i32 we have
// VecTy = <12 x i32>.

// Calculate the number of memory operations (NumOfMemOps), required
// for load/store the VecTy.
MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second;
unsigned VecTySize = DL.getTypeStoreSize(VecTy);
unsigned LegalVTSize = LegalVT.getStoreSize();
unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize;

// Get the cost of one memory operation.
auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(),
                                           LegalVT.getVectorNumElements());
InstructionCost MemOpCost = getMemoryOpCost(
    Opcode, SingleMemOpTy, MaybeAlign(Alignment), AddressSpace, CostKind);

unsigned VF = VecTy->getNumElements() / Factor;
MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF);

if (Opcode == Instruction::Load) {
  // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl)
  // contain the cost of the optimized shuffle sequence that the
  // X86InterleavedAccess pass will generate.
  // The cost of loads and stores are computed separately from the table.

  // X86InterleavedAccess support only the following interleaved-access group.
  static const CostTblEntry AVX512InterleavedLoadTbl[] = {
      {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8
      {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8
      {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8
  };

  if (const auto *Entry =
          CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT))
    return NumOfMemOps * MemOpCost + Entry->Cost;
  //If an entry does not exist, fallback to the default implementation.

  // Kind of shuffle depends on number of loaded values.
  // If we load the entire data in one register, we can use a 1-src shuffle.
  // Otherwise, we'll merge 2 sources in each operation.
  TTI::ShuffleKind ShuffleKind =
      (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc;

  InstructionCost ShuffleCost =
      getShuffleCost(ShuffleKind, SingleMemOpTy, None, 0, nullptr);

  unsigned NumOfLoadsInInterleaveGrp =
      Indices.size() ? Indices.size() : Factor;
  auto *ResultTy = FixedVectorType::get(VecTy->getElementType(),
                                        VecTy->getNumElements() / Factor);
  InstructionCost NumOfResults =
      getTLI()->getTypeLegalizationCost(DL, ResultTy).first *
      NumOfLoadsInInterleaveGrp;

  // About a half of the loads may be folded in shuffles when we have only
  // one result. If we have more than one result, we do not fold loads at all.
  unsigned NumOfUnfoldedLoads =
      NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2;

  // Get a number of shuffle operations per result.
  unsigned NumOfShufflesPerResult =
      std::max((unsigned)1, (unsigned)(NumOfMemOps - 1));

  // The SK_MergeTwoSrc shuffle clobbers one of src operands.
  // When we have more than one destination, we need additional instructions
  // to keep sources.
  InstructionCost NumOfMoves = 0;
  if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc)
    NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2;

  InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost +
                         NumOfUnfoldedLoads * MemOpCost + NumOfMoves;

  return Cost;
}

// Store.
assert(Opcode == Instruction::Store &&((void)0)
       "Expected Store Instruction at this  point")((void)0);
// X86InterleavedAccess support only the following interleaved-access group.
static const CostTblEntry AVX512InterleavedStoreTbl[] = {
    {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store)
    {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store)
    {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store)

    {4, MVT::v8i8, 10},  // interleave 4 x 8i8  into 32i8  (and store)
    {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8  (and store)
    {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store)
    {4, MVT::v64i8, 24}  // interleave 4 x 32i8 into 256i8 (and store)
};

if (const auto *Entry =
        CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT))
  return NumOfMemOps * MemOpCost + Entry->Cost;
//If an entry does not exist, fallback to the default implementation.

// There is no strided stores meanwhile. And store can't be folded in
// shuffle.
unsigned NumOfSources = Factor; // The number of values to be merged.
InstructionCost ShuffleCost =
    getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, None, 0, nullptr);
unsigned NumOfShufflesPerStore = NumOfSources - 1;

// The SK_MergeTwoSrc shuffle clobbers one of src operands.
// We need additional instructions to keep sources.
unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2;
InstructionCost Cost =
    NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) +
    NumOfMoves;
return Cost;
5144}

5146InstructionCost X86TTIImpl::getInterleavedMemoryOpCost(
  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
  bool UseMaskForCond, bool UseMaskForGaps) {
auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) {
  Type *EltTy = cast<VectorType>(VecTy)->getElementType();
  if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) ||
      EltTy->isIntegerTy(32) || EltTy->isPointerTy())
    return true;
  if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8))
    return HasBW;
  return false;
};
if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI()))
  return getInterleavedMemoryOpCostAVX512(
      Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment,
      AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps);
if (ST->hasAVX2())
1
Taking false branch→
  return getInterleavedMemoryOpCostAVX2(
      Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment,
      AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps);

return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
2
←
Calling 'BasicTTIImplBase::getInterleavedMemoryOpCost'→
                                         Alignment, AddressSpace, CostKind,
                                         UseMaskForCond, UseMaskForGaps);
5171}

←

/usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/CodeGen/BasicTTIImpl.h

→

1//===- BasicTTIImpl.h -------------------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// This file provides a helper that implements much of the TTI interface in
11/// terms of the target-independent code generator and TargetLowering
12/// interfaces.
13//
14//===----------------------------------------------------------------------===//

16#ifndef LLVM_CODEGEN_BASICTTIIMPL_H
17#define LLVM_CODEGEN_BASICTTIIMPL_H

19#include "llvm/ADT/APInt.h"
20#include "llvm/ADT/ArrayRef.h"
21#include "llvm/ADT/BitVector.h"
22#include "llvm/ADT/SmallPtrSet.h"
23#include "llvm/ADT/SmallVector.h"
24#include "llvm/Analysis/LoopInfo.h"
25#include "llvm/Analysis/TargetTransformInfo.h"
26#include "llvm/Analysis/TargetTransformInfoImpl.h"
27#include "llvm/CodeGen/ISDOpcodes.h"
28#include "llvm/CodeGen/TargetLowering.h"
29#include "llvm/CodeGen/TargetSubtargetInfo.h"
30#include "llvm/CodeGen/ValueTypes.h"
31#include "llvm/IR/BasicBlock.h"
32#include "llvm/IR/Constant.h"
33#include "llvm/IR/Constants.h"
34#include "llvm/IR/DataLayout.h"
35#include "llvm/IR/DerivedTypes.h"
36#include "llvm/IR/InstrTypes.h"
37#include "llvm/IR/Instruction.h"
38#include "llvm/IR/Instructions.h"
39#include "llvm/IR/Intrinsics.h"
40#include "llvm/IR/Operator.h"
41#include "llvm/IR/Type.h"
42#include "llvm/IR/Value.h"
43#include "llvm/Support/Casting.h"
44#include "llvm/Support/CommandLine.h"
45#include "llvm/Support/ErrorHandling.h"
46#include "llvm/Support/MachineValueType.h"
47#include "llvm/Support/MathExtras.h"
48#include "llvm/Target/TargetMachine.h"
49#include <algorithm>
50#include <cassert>
51#include <cstdint>
52#include <limits>
53#include <utility>

55namespace llvm {

57class Function;
58class GlobalValue;
59class LLVMContext;
60class ScalarEvolution;
61class SCEV;
62class TargetMachine;

64extern cl::opt<unsigned> PartialUnrollingThreshold;

66/// Base class which can be used to help build a TTI implementation.
67///
68/// This class provides as much implementation of the TTI interface as is
69/// possible using the target independent parts of the code generator.
70///
71/// In order to subclass it, your class must implement a getST() method to
72/// return the subtarget, and a getTLI() method to return the target lowering.
73/// We need these methods implemented in the derived class so that this class
74/// doesn't have to duplicate storage for them.
75template <typename T>
76class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
77private:
using BaseT = TargetTransformInfoImplCRTPBase<T>;
using TTI = TargetTransformInfo;

/// Helper function to access this as a T.
T *thisT() { return static_cast<T *>(this); }

/// Estimate a cost of Broadcast as an extract and sequence of insert
/// operations.
InstructionCost getBroadcastShuffleOverhead(FixedVectorType *VTy) {
  InstructionCost Cost = 0;
  // Broadcast cost is equal to the cost of extracting the zero'th element
  // plus the cost of inserting it into every element of the result vector.
  Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, VTy, 0);

  for (int i = 0, e = VTy->getNumElements(); i < e; ++i) {
    Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, VTy, i);
  }
  return Cost;
}

/// Estimate a cost of shuffle as a sequence of extract and insert
/// operations.
InstructionCost getPermuteShuffleOverhead(FixedVectorType *VTy) {
  InstructionCost Cost = 0;
  // Shuffle cost is equal to the cost of extracting element from its argument
  // plus the cost of inserting them onto the result vector.

  // e.g. <4 x float> has a mask of <0,5,2,7> i.e we need to extract from
  // index 0 of first vector, index 1 of second vector,index 2 of first
  // vector and finally index 3 of second vector and insert them at index
  // <0,1,2,3> of result vector.
  for (int i = 0, e = VTy->getNumElements(); i < e; ++i) {
    Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, VTy, i);
    Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, VTy, i);
  }
  return Cost;
}

/// Estimate a cost of subvector extraction as a sequence of extract and
/// insert operations.
InstructionCost getExtractSubvectorOverhead(VectorType *VTy, int Index,
                                     FixedVectorType *SubVTy) {
  assert(VTy && SubVTy &&((void)0)
         "Can only extract subvectors from vectors")((void)0);
  int NumSubElts = SubVTy->getNumElements();
  assert((!isa<FixedVectorType>(VTy) ||((void)0)
          (Index + NumSubElts) <=((void)0)
              (int)cast<FixedVectorType>(VTy)->getNumElements()) &&((void)0)
         "SK_ExtractSubvector index out of range")((void)0);

  InstructionCost Cost = 0;
  // Subvector extraction cost is equal to the cost of extracting element from
  // the source type plus the cost of inserting them into the result vector
  // type.
  for (int i = 0; i != NumSubElts; ++i) {
    Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, VTy,
                                        i + Index);
    Cost +=
        thisT()->getVectorInstrCost(Instruction::InsertElement, SubVTy, i);
  }
  return Cost;
}

/// Estimate a cost of subvector insertion as a sequence of extract and
/// insert operations.
InstructionCost getInsertSubvectorOverhead(VectorType *VTy, int Index,
                                    FixedVectorType *SubVTy) {
  assert(VTy && SubVTy &&((void)0)
         "Can only insert subvectors into vectors")((void)0);
  int NumSubElts = SubVTy->getNumElements();
  assert((!isa<FixedVectorType>(VTy) ||((void)0)
          (Index + NumSubElts) <=((void)0)
              (int)cast<FixedVectorType>(VTy)->getNumElements()) &&((void)0)
         "SK_InsertSubvector index out of range")((void)0);

  InstructionCost Cost = 0;
  // Subvector insertion cost is equal to the cost of extracting element from
  // the source type plus the cost of inserting them into the result vector
  // type.
  for (int i = 0; i != NumSubElts; ++i) {
    Cost +=
        thisT()->getVectorInstrCost(Instruction::ExtractElement, SubVTy, i);
    Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, VTy,
                                        i + Index);
  }
  return Cost;
}

/// Local query method delegates up to T which *must* implement this!
const TargetSubtargetInfo *getST() const {
  return static_cast<const T *>(this)->getST();
}

/// Local query method delegates up to T which *must* implement this!
const TargetLoweringBase *getTLI() const {
  return static_cast<const T *>(this)->getTLI();
}

static ISD::MemIndexedMode getISDIndexedMode(TTI::MemIndexedMode M) {
  switch (M) {
    case TTI::MIM_Unindexed:
      return ISD::UNINDEXED;
    case TTI::MIM_PreInc:
      return ISD::PRE_INC;
    case TTI::MIM_PreDec:
      return ISD::PRE_DEC;
    case TTI::MIM_PostInc:
      return ISD::POST_INC;
    case TTI::MIM_PostDec:
      return ISD::POST_DEC;
  }
  llvm_unreachable("Unexpected MemIndexedMode")__builtin_unreachable();
}

InstructionCost getCommonMaskedMemoryOpCost(unsigned Opcode, Type *DataTy,
                                            Align Alignment,
                                            bool VariableMask,
                                            bool IsGatherScatter,
                                            TTI::TargetCostKind CostKind) {
  auto *VT = cast<FixedVectorType>(DataTy);
  // Assume the target does not have support for gather/scatter operations
  // and provide a rough estimate.
  //
  // First, compute the cost of the individual memory operations.
  InstructionCost AddrExtractCost =
      IsGatherScatter
          ? getVectorInstrCost(Instruction::ExtractElement,
                               FixedVectorType::get(
                                   PointerType::get(VT->getElementType(), 0),
                                   VT->getNumElements()),
                               -1)
          : 0;
  InstructionCost LoadCost =
      VT->getNumElements() *
      (AddrExtractCost +
       getMemoryOpCost(Opcode, VT->getElementType(), Alignment, 0, CostKind));

  // Next, compute the cost of packing the result in a vector.
  InstructionCost PackingCost = getScalarizationOverhead(
      VT, Opcode != Instruction::Store, Opcode == Instruction::Store);

  InstructionCost ConditionalCost = 0;
  if (VariableMask) {
    // Compute the cost of conditionally executing the memory operations with
    // variable masks. This includes extracting the individual conditions, a
    // branches and PHIs to combine the results.
    // NOTE: Estimating the cost of conditionally executing the memory
    // operations accurately is quite difficult and the current solution
    // provides a very rough estimate only.
    ConditionalCost =
        VT->getNumElements() *
        (getVectorInstrCost(
             Instruction::ExtractElement,
             FixedVectorType::get(Type::getInt1Ty(DataTy->getContext()),
                                  VT->getNumElements()),
             -1) +
         getCFInstrCost(Instruction::Br, CostKind) +
         getCFInstrCost(Instruction::PHI, CostKind));
  }

  return LoadCost + PackingCost + ConditionalCost;
}

241protected:
explicit BasicTTIImplBase(const TargetMachine *TM, const DataLayout &DL)
    : BaseT(DL) {}
virtual ~BasicTTIImplBase() = default;

using TargetTransformInfoImplBase::DL;

248public:
/// \name Scalar TTI Implementations
/// @{
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth,
                                    unsigned AddressSpace, Align Alignment,
                                    bool *Fast) const {
  EVT E = EVT::getIntegerVT(Context, BitWidth);
  return getTLI()->allowsMisalignedMemoryAccesses(
      E, AddressSpace, Alignment, MachineMemOperand::MONone, Fast);
}

bool hasBranchDivergence() { return false; }

bool useGPUDivergenceAnalysis() { return false; }

bool isSourceOfDivergence(const Value *V) { return false; }

bool isAlwaysUniform(const Value *V) { return false; }

unsigned getFlatAddressSpace() {
  // Return an invalid address space.
  return -1;
}

bool collectFlatAddressOperands(SmallVectorImpl<int> &OpIndexes,
                                Intrinsic::ID IID) const {
  return false;
}

bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const {
  return getTLI()->getTargetMachine().isNoopAddrSpaceCast(FromAS, ToAS);
}

unsigned getAssumedAddrSpace(const Value *V) const {
  return getTLI()->getTargetMachine().getAssumedAddrSpace(V);
}

Value *rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV,
                                        Value *NewV) const {
  return nullptr;
}

bool isLegalAddImmediate(int64_t imm) {
  return getTLI()->isLegalAddImmediate(imm);
}

bool isLegalICmpImmediate(int64_t imm) {
  return getTLI()->isLegalICmpImmediate(imm);
}

bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
                           bool HasBaseReg, int64_t Scale,
                           unsigned AddrSpace, Instruction *I = nullptr) {
  TargetLoweringBase::AddrMode AM;
  AM.BaseGV = BaseGV;
  AM.BaseOffs = BaseOffset;
  AM.HasBaseReg = HasBaseReg;
  AM.Scale = Scale;
  return getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace, I);
}

bool isIndexedLoadLegal(TTI::MemIndexedMode M, Type *Ty,
                        const DataLayout &DL) const {
  EVT VT = getTLI()->getValueType(DL, Ty);
  return getTLI()->isIndexedLoadLegal(getISDIndexedMode(M), VT);
}

bool isIndexedStoreLegal(TTI::MemIndexedMode M, Type *Ty,
                         const DataLayout &DL) const {
  EVT VT = getTLI()->getValueType(DL, Ty);
  return getTLI()->isIndexedStoreLegal(getISDIndexedMode(M), VT);
}

bool isLSRCostLess(TTI::LSRCost C1, TTI::LSRCost C2) {
  return TargetTransformInfoImplBase::isLSRCostLess(C1, C2);
}

bool isNumRegsMajorCostOfLSR() {
  return TargetTransformInfoImplBase::isNumRegsMajorCostOfLSR();
}

bool isProfitableLSRChainElement(Instruction *I) {
  return TargetTransformInfoImplBase::isProfitableLSRChainElement(I);
}

InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
                                     int64_t BaseOffset, bool HasBaseReg,
                                     int64_t Scale, unsigned AddrSpace) {
  TargetLoweringBase::AddrMode AM;
  AM.BaseGV = BaseGV;
  AM.BaseOffs = BaseOffset;
  AM.HasBaseReg = HasBaseReg;
  AM.Scale = Scale;
  return getTLI()->getScalingFactorCost(DL, AM, Ty, AddrSpace);
}

bool isTruncateFree(Type *Ty1, Type *Ty2) {
  return getTLI()->isTruncateFree(Ty1, Ty2);
}

bool isProfitableToHoist(Instruction *I) {
  return getTLI()->isProfitableToHoist(I);
}

bool useAA() const { return getST()->useAA(); }

bool isTypeLegal(Type *Ty) {
  EVT VT = getTLI()->getValueType(DL, Ty);
  return getTLI()->isTypeLegal(VT);
}

InstructionCost getRegUsageForType(Type *Ty) {
  InstructionCost Val = getTLI()->getTypeLegalizationCost(DL, Ty).first;
  assert(Val >= 0 && "Negative cost!")((void)0);
  return Val;
}

InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr,
                           ArrayRef<const Value *> Operands) {
  return BaseT::getGEPCost(PointeeType, Ptr, Operands);
}

unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
                                          unsigned &JumpTableSize,
                                          ProfileSummaryInfo *PSI,
                                          BlockFrequencyInfo *BFI) {
  /// Try to find the estimated number of clusters. Note that the number of
  /// clusters identified in this function could be different from the actual
  /// numbers found in lowering. This function ignore switches that are
  /// lowered with a mix of jump table / bit test / BTree. This function was
  /// initially intended to be used when estimating the cost of switch in
  /// inline cost heuristic, but it's a generic cost model to be used in other
  /// places (e.g., in loop unrolling).
  unsigned N = SI.getNumCases();
  const TargetLoweringBase *TLI = getTLI();
  const DataLayout &DL = this->getDataLayout();

  JumpTableSize = 0;
  bool IsJTAllowed = TLI->areJTsAllowed(SI.getParent()->getParent());

  // Early exit if both a jump table and bit test are not allowed.
  if (N < 1 || (!IsJTAllowed && DL.getIndexSizeInBits(0u) < N))
    return N;

  APInt MaxCaseVal = SI.case_begin()->getCaseValue()->getValue();
  APInt MinCaseVal = MaxCaseVal;
  for (auto CI : SI.cases()) {
    const APInt &CaseVal = CI.getCaseValue()->getValue();
    if (CaseVal.sgt(MaxCaseVal))
      MaxCaseVal = CaseVal;
    if (CaseVal.slt(MinCaseVal))
      MinCaseVal = CaseVal;
  }

  // Check if suitable for a bit test
  if (N <= DL.getIndexSizeInBits(0u)) {
    SmallPtrSet<const BasicBlock *, 4> Dests;
    for (auto I : SI.cases())
      Dests.insert(I.getCaseSuccessor());

    if (TLI->isSuitableForBitTests(Dests.size(), N, MinCaseVal, MaxCaseVal,
                                   DL))
      return 1;
  }

  // Check if suitable for a jump table.
  if (IsJTAllowed) {
    if (N < 2 || N < TLI->getMinimumJumpTableEntries())
      return N;
    uint64_t Range =
        (MaxCaseVal - MinCaseVal)
            .getLimitedValue(std::numeric_limits<uint64_t>::max() - 1) + 1;
    // Check whether a range of clusters is dense enough for a jump table
    if (TLI->isSuitableForJumpTable(&SI, N, Range, PSI, BFI)) {
      JumpTableSize = Range;
      return 1;
    }
  }
  return N;
}

bool shouldBuildLookupTables() {
  const TargetLoweringBase *TLI = getTLI();
  return TLI->isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
         TLI->isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
}

bool shouldBuildRelLookupTables() const {
  const TargetMachine &TM = getTLI()->getTargetMachine();
  // If non-PIC mode, do not generate a relative lookup table.
  if (!TM.isPositionIndependent())
    return false;

  /// Relative lookup table entries consist of 32-bit offsets.
  /// Do not generate relative lookup tables for large code models
  /// in 64-bit achitectures where 32-bit offsets might not be enough.
  if (TM.getCodeModel() == CodeModel::Medium ||
      TM.getCodeModel() == CodeModel::Large)
    return false;

  Triple TargetTriple = TM.getTargetTriple();
  if (!TargetTriple.isArch64Bit())
    return false;

  // TODO: Triggers issues on aarch64 on darwin, so temporarily disable it
  // there.
  if (TargetTriple.getArch() == Triple::aarch64 && TargetTriple.isOSDarwin())
    return false;

  return true;
}

bool haveFastSqrt(Type *Ty) {
  const TargetLoweringBase *TLI = getTLI();
  EVT VT = TLI->getValueType(DL, Ty);
  return TLI->isTypeLegal(VT) &&
         TLI->isOperationLegalOrCustom(ISD::FSQRT, VT);
}

bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) {
  return true;
}

InstructionCost getFPOpCost(Type *Ty) {
  // Check whether FADD is available, as a proxy for floating-point in
  // general.
  const TargetLoweringBase *TLI = getTLI();
  EVT VT = TLI->getValueType(DL, Ty);
  if (TLI->isOperationLegalOrCustomOrPromote(ISD::FADD, VT))
    return TargetTransformInfo::TCC_Basic;
  return TargetTransformInfo::TCC_Expensive;
}

unsigned getInliningThresholdMultiplier() { return 1; }
unsigned adjustInliningThreshold(const CallBase *CB) { return 0; }

int getInlinerVectorBonusPercent() { return 150; }

void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
                             TTI::UnrollingPreferences &UP) {
  // This unrolling functionality is target independent, but to provide some
  // motivation for its intended use, for x86:

  // According to the Intel 64 and IA-32 Architectures Optimization Reference
  // Manual, Intel Core models and later have a loop stream detector (and
  // associated uop queue) that can benefit from partial unrolling.
  // The relevant requirements are:
  //  - The loop must have no more than 4 (8 for Nehalem and later) branches
  //    taken, and none of them may be calls.
  //  - The loop can have no more than 18 (28 for Nehalem and later) uops.

  // According to the Software Optimization Guide for AMD Family 15h
  // Processors, models 30h-4fh (Steamroller and later) have a loop predictor
  // and loop buffer which can benefit from partial unrolling.
  // The relevant requirements are:
  //  - The loop must have fewer than 16 branches
  //  - The loop must have less than 40 uops in all executed loop branches

  // The number of taken branches in a loop is hard to estimate here, and
  // benchmarking has revealed that it is better not to be conservative when
  // estimating the branch count. As a result, we'll ignore the branch limits
  // until someone finds a case where it matters in practice.

  unsigned MaxOps;
  const TargetSubtargetInfo *ST = getST();
  if (PartialUnrollingThreshold.getNumOccurrences() > 0)
    MaxOps = PartialUnrollingThreshold;
  else if (ST->getSchedModel().LoopMicroOpBufferSize > 0)
    MaxOps = ST->getSchedModel().LoopMicroOpBufferSize;
  else
    return;

  // Scan the loop: don't unroll loops with calls.
  for (BasicBlock *BB : L->blocks()) {
    for (Instruction &I : *BB) {
      if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
        if (const Function *F = cast<CallBase>(I).getCalledFunction()) {
          if (!thisT()->isLoweredToCall(F))
            continue;
        }

        return;
      }
    }
  }

  // Enable runtime and partial unrolling up to the specified size.
  // Enable using trip count upper bound to unroll loops.
  UP.Partial = UP.Runtime = UP.UpperBound = true;
  UP.PartialThreshold = MaxOps;

  // Avoid unrolling when optimizing for size.
  UP.OptSizeThreshold = 0;
  UP.PartialOptSizeThreshold = 0;

  // Set number of instructions optimized when "back edge"
  // becomes "fall through" to default value of 2.
  UP.BEInsns = 2;
}

void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
                           TTI::PeelingPreferences &PP) {
  PP.PeelCount = 0;
  PP.AllowPeeling = true;
  PP.AllowLoopNestsPeeling = false;
  PP.PeelProfiledIterations = true;
}

bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE,
                              AssumptionCache &AC,
                              TargetLibraryInfo *LibInfo,
                              HardwareLoopInfo &HWLoopInfo) {
  return BaseT::isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
}

bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE,
                                 AssumptionCache &AC, TargetLibraryInfo *TLI,
                                 DominatorTree *DT,
                                 const LoopAccessInfo *LAI) {
  return BaseT::preferPredicateOverEpilogue(L, LI, SE, AC, TLI, DT, LAI);
}

bool emitGetActiveLaneMask() {
  return BaseT::emitGetActiveLaneMask();
}

Optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
                                             IntrinsicInst &II) {
  return BaseT::instCombineIntrinsic(IC, II);
}

Optional<Value *> simplifyDemandedUseBitsIntrinsic(InstCombiner &IC,
                                                   IntrinsicInst &II,
                                                   APInt DemandedMask,
                                                   KnownBits &Known,
                                                   bool &KnownBitsComputed) {
  return BaseT::simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
                                                 KnownBitsComputed);
}

Optional<Value *> simplifyDemandedVectorEltsIntrinsic(
    InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
    APInt &UndefElts2, APInt &UndefElts3,
    std::function<void(Instruction *, unsigned, APInt, APInt &)>
        SimplifyAndSetOp) {
  return BaseT::simplifyDemandedVectorEltsIntrinsic(
      IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
      SimplifyAndSetOp);
}

InstructionCost getInstructionLatency(const Instruction *I) {
  if (isa<LoadInst>(I))
    return getST()->getSchedModel().DefaultLoadLatency;

  return BaseT::getInstructionLatency(I);
}

virtual Optional<unsigned>
getCacheSize(TargetTransformInfo::CacheLevel Level) const {
  return Optional<unsigned>(
    getST()->getCacheSize(static_cast<unsigned>(Level)));
}

virtual Optional<unsigned>
getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const {
  Optional<unsigned> TargetResult =
      getST()->getCacheAssociativity(static_cast<unsigned>(Level));

  if (TargetResult)
    return TargetResult;

  return BaseT::getCacheAssociativity(Level);
}

virtual unsigned getCacheLineSize() const {
  return getST()->getCacheLineSize();
}

virtual unsigned getPrefetchDistance() const {
  return getST()->getPrefetchDistance();
}

virtual unsigned getMinPrefetchStride(unsigned NumMemAccesses,
                                      unsigned NumStridedMemAccesses,
                                      unsigned NumPrefetches,
                                      bool HasCall) const {
  return getST()->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
                                       NumPrefetches, HasCall);
}

virtual unsigned getMaxPrefetchIterationsAhead() const {
  return getST()->getMaxPrefetchIterationsAhead();
}

virtual bool enableWritePrefetching() const {
  return getST()->enableWritePrefetching();
}

/// @}

/// \name Vector TTI Implementations
/// @{

TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
  return TypeSize::getFixed(32);
}

Optional<unsigned> getMaxVScale() const { return None; }

/// Estimate the overhead of scalarizing an instruction. Insert and Extract
/// are set if the demanded result elements need to be inserted and/or
/// extracted from vectors.
InstructionCost getScalarizationOverhead(VectorType *InTy,
                                         const APInt &DemandedElts,
                                         bool Insert, bool Extract) {
  /// FIXME: a bitfield is not a reasonable abstraction for talking about
  /// which elements are needed from a scalable vector
  auto *Ty = cast<FixedVectorType>(InTy);

  assert(DemandedElts.getBitWidth() == Ty->getNumElements() &&((void)0)
         "Vector size mismatch")((void)0);

  InstructionCost Cost = 0;

  for (int i = 0, e = Ty->getNumElements(); i < e; ++i) {
    if (!DemandedElts[i])
      continue;
    if (Insert)
      Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, Ty, i);
    if (Extract)
      Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, Ty, i);
  }

  return Cost;
}

/// Helper wrapper for the DemandedElts variant of getScalarizationOverhead.
InstructionCost getScalarizationOverhead(VectorType *InTy, bool Insert,
                                         bool Extract) {
  auto *Ty = cast<FixedVectorType>(InTy);

  APInt DemandedElts = APInt::getAllOnesValue(Ty->getNumElements());
  return thisT()->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract);
}

/// Estimate the overhead of scalarizing an instructions unique
/// non-constant operands. The (potentially vector) types to use for each of
/// argument are passes via Tys.
InstructionCost getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
                                                 ArrayRef<Type *> Tys) {
  assert(Args.size() == Tys.size() && "Expected matching Args and Tys")((void)0);

  InstructionCost Cost = 0;
  SmallPtrSet<const Value*, 4> UniqueOperands;
  for (int I = 0, E = Args.size(); I != E; I++) {
    // Disregard things like metadata arguments.
    const Value *A = Args[I];
    Type *Ty = Tys[I];
    if (!Ty->isIntOrIntVectorTy() && !Ty->isFPOrFPVectorTy() &&
        !Ty->isPtrOrPtrVectorTy())
      continue;

    if (!isa<Constant>(A) && UniqueOperands.insert(A).second) {
      if (auto *VecTy = dyn_cast<VectorType>(Ty))
        Cost += getScalarizationOverhead(VecTy, false, true);
    }
  }

  return Cost;
}

/// Estimate the overhead of scalarizing the inputs and outputs of an
/// instruction, with return type RetTy and arguments Args of type Tys. If
/// Args are unknown (empty), then the cost associated with one argument is
/// added as a heuristic.
InstructionCost getScalarizationOverhead(VectorType *RetTy,
                                         ArrayRef<const Value *> Args,
                                         ArrayRef<Type *> Tys) {
  InstructionCost Cost = getScalarizationOverhead(RetTy, true, false);
  if (!Args.empty())
    Cost += getOperandsScalarizationOverhead(Args, Tys);
  else
    // When no information on arguments is provided, we add the cost
    // associated with one argument as a heuristic.
    Cost += getScalarizationOverhead(RetTy, false, true);

  return Cost;
}

unsigned getMaxInterleaveFactor(unsigned VF) { return 1; }

InstructionCost getArithmeticInstrCost(
    unsigned Opcode, Type *Ty,
    TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput,
    TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
    TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
    TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
    TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
    ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
    const Instruction *CxtI = nullptr) {
  // Check if any of the operands are vector operands.
  const TargetLoweringBase *TLI = getTLI();
  int ISD = TLI->InstructionOpcodeToISD(Opcode);
  assert(ISD && "Invalid opcode")((void)0);

  // TODO: Handle more cost kinds.
  if (CostKind != TTI::TCK_RecipThroughput)
    return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind,
                                         Opd1Info, Opd2Info,
                                         Opd1PropInfo, Opd2PropInfo,
                                         Args, CxtI);

  std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);

  bool IsFloat = Ty->isFPOrFPVectorTy();
  // Assume that floating point arithmetic operations cost twice as much as
  // integer operations.
  InstructionCost OpCost = (IsFloat ? 2 : 1);

  if (TLI->isOperationLegalOrPromote(ISD, LT.second)) {
    // The operation is legal. Assume it costs 1.
    // TODO: Once we have extract/insert subvector cost we need to use them.
    return LT.first * OpCost;
  }

  if (!TLI->isOperationExpand(ISD, LT.second)) {
    // If the operation is custom lowered, then assume that the code is twice
    // as expensive.
    return LT.first * 2 * OpCost;
  }

  // An 'Expand' of URem and SRem is special because it may default
  // to expanding the operation into a sequence of sub-operations
  // i.e. X % Y -> X-(X/Y)*Y.
  if (ISD == ISD::UREM || ISD == ISD::SREM) {
    bool IsSigned = ISD == ISD::SREM;
    if (TLI->isOperationLegalOrCustom(IsSigned ? ISD::SDIVREM : ISD::UDIVREM,
                                      LT.second) ||
        TLI->isOperationLegalOrCustom(IsSigned ? ISD::SDIV : ISD::UDIV,
                                      LT.second)) {
      unsigned DivOpc = IsSigned ? Instruction::SDiv : Instruction::UDiv;
      InstructionCost DivCost = thisT()->getArithmeticInstrCost(
          DivOpc, Ty, CostKind, Opd1Info, Opd2Info, Opd1PropInfo,
          Opd2PropInfo);
      InstructionCost MulCost =
          thisT()->getArithmeticInstrCost(Instruction::Mul, Ty, CostKind);
      InstructionCost SubCost =
          thisT()->getArithmeticInstrCost(Instruction::Sub, Ty, CostKind);
      return DivCost + MulCost + SubCost;
    }
  }

  // We cannot scalarize scalable vectors, so return Invalid.
  if (isa<ScalableVectorType>(Ty))
    return InstructionCost::getInvalid();

  // Else, assume that we need to scalarize this op.
  // TODO: If one of the types get legalized by splitting, handle this
  // similarly to what getCastInstrCost() does.
  if (auto *VTy = dyn_cast<FixedVectorType>(Ty)) {
    InstructionCost Cost = thisT()->getArithmeticInstrCost(
        Opcode, VTy->getScalarType(), CostKind, Opd1Info, Opd2Info,
        Opd1PropInfo, Opd2PropInfo, Args, CxtI);
    // Return the cost of multiple scalar invocation plus the cost of
    // inserting and extracting the values.
    SmallVector<Type *> Tys(Args.size(), Ty);
    return getScalarizationOverhead(VTy, Args, Tys) +
           VTy->getNumElements() * Cost;
  }

  // We don't know anything about this scalar instruction.
  return OpCost;
}

TTI::ShuffleKind improveShuffleKindFromMask(TTI::ShuffleKind Kind,
                                            ArrayRef<int> Mask) const {
  int Limit = Mask.size() * 2;
  if (Mask.empty() ||
      // Extra check required by isSingleSourceMaskImpl function (called by
      // ShuffleVectorInst::isSingleSourceMask).
      any_of(Mask, [Limit](int I) { return I >= Limit; }))
    return Kind;
  switch (Kind) {
  case TTI::SK_PermuteSingleSrc:
    if (ShuffleVectorInst::isReverseMask(Mask))
      return TTI::SK_Reverse;
    if (ShuffleVectorInst::isZeroEltSplatMask(Mask))
      return TTI::SK_Broadcast;
    break;
  case TTI::SK_PermuteTwoSrc:
    if (ShuffleVectorInst::isSelectMask(Mask))
      return TTI::SK_Select;
    if (ShuffleVectorInst::isTransposeMask(Mask))
      return TTI::SK_Transpose;
    break;
  case TTI::SK_Select:
  case TTI::SK_Reverse:
  case TTI::SK_Broadcast:
  case TTI::SK_Transpose:
  case TTI::SK_InsertSubvector:
  case TTI::SK_ExtractSubvector:
  case TTI::SK_Splice:
    break;
  }
  return Kind;
}

InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp,
                               ArrayRef<int> Mask, int Index,
                               VectorType *SubTp) {

  switch (improveShuffleKindFromMask(Kind, Mask)) {
  case TTI::SK_Broadcast:
    return getBroadcastShuffleOverhead(cast<FixedVectorType>(Tp));
  case TTI::SK_Select:
  case TTI::SK_Splice:
  case TTI::SK_Reverse:
  case TTI::SK_Transpose:
  case TTI::SK_PermuteSingleSrc:
  case TTI::SK_PermuteTwoSrc:
    return getPermuteShuffleOverhead(cast<FixedVectorType>(Tp));
  case TTI::SK_ExtractSubvector:
    return getExtractSubvectorOverhead(Tp, Index,
                                       cast<FixedVectorType>(SubTp));
  case TTI::SK_InsertSubvector:
    return getInsertSubvectorOverhead(Tp, Index,
                                      cast<FixedVectorType>(SubTp));
  }
  llvm_unreachable("Unknown TTI::ShuffleKind")__builtin_unreachable();
}

InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
                                 TTI::CastContextHint CCH,
                                 TTI::TargetCostKind CostKind,
                                 const Instruction *I = nullptr) {
  if (BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I) == 0)
    return 0;

  const TargetLoweringBase *TLI = getTLI();
  int ISD = TLI->InstructionOpcodeToISD(Opcode);
  assert(ISD && "Invalid opcode")((void)0);
  std::pair<InstructionCost, MVT> SrcLT =
      TLI->getTypeLegalizationCost(DL, Src);
  std::pair<InstructionCost, MVT> DstLT =
      TLI->getTypeLegalizationCost(DL, Dst);

  TypeSize SrcSize = SrcLT.second.getSizeInBits();
  TypeSize DstSize = DstLT.second.getSizeInBits();
  bool IntOrPtrSrc = Src->isIntegerTy() || Src->isPointerTy();
  bool IntOrPtrDst = Dst->isIntegerTy() || Dst->isPointerTy();

  switch (Opcode) {
  default:
    break;
  case Instruction::Trunc:
    // Check for NOOP conversions.
    if (TLI->isTruncateFree(SrcLT.second, DstLT.second))
      return 0;
    LLVM_FALLTHROUGH[[gnu::fallthrough]];
  case Instruction::BitCast:
    // Bitcast between types that are legalized to the same type are free and
    // assume int to/from ptr of the same size is also free.
    if (SrcLT.first == DstLT.first && IntOrPtrSrc == IntOrPtrDst &&
        SrcSize == DstSize)
      return 0;
    break;
  case Instruction::FPExt:
    if (I && getTLI()->isExtFree(I))
      return 0;
    break;
  case Instruction::ZExt:
    if (TLI->isZExtFree(SrcLT.second, DstLT.second))
      return 0;
    LLVM_FALLTHROUGH[[gnu::fallthrough]];
  case Instruction::SExt:
    if (I && getTLI()->isExtFree(I))
      return 0;

    // If this is a zext/sext of a load, return 0 if the corresponding
    // extending load exists on target and the result type is legal.
    if (CCH == TTI::CastContextHint::Normal) {
      EVT ExtVT = EVT::getEVT(Dst);
      EVT LoadVT = EVT::getEVT(Src);
      unsigned LType =
        ((Opcode == Instruction::ZExt) ? ISD::ZEXTLOAD : ISD::SEXTLOAD);
      if (DstLT.first == SrcLT.first &&
          TLI->isLoadExtLegal(LType, ExtVT, LoadVT))
        return 0;
    }
    break;
  case Instruction::AddrSpaceCast:
    if (TLI->isFreeAddrSpaceCast(Src->getPointerAddressSpace(),
                                 Dst->getPointerAddressSpace()))
      return 0;
    break;
  }

  auto *SrcVTy = dyn_cast<VectorType>(Src);
  auto *DstVTy = dyn_cast<VectorType>(Dst);

  // If the cast is marked as legal (or promote) then assume low cost.
  if (SrcLT.first == DstLT.first &&
      TLI->isOperationLegalOrPromote(ISD, DstLT.second))
    return SrcLT.first;

  // Handle scalar conversions.
  if (!SrcVTy && !DstVTy) {
    // Just check the op cost. If the operation is legal then assume it costs
    // 1.
    if (!TLI->isOperationExpand(ISD, DstLT.second))
      return 1;

    // Assume that illegal scalar instruction are expensive.
    return 4;
  }

  // Check vector-to-vector casts.
  if (DstVTy && SrcVTy) {
    // If the cast is between same-sized registers, then the check is simple.
    if (SrcLT.first == DstLT.first && SrcSize == DstSize) {

      // Assume that Zext is done using AND.
      if (Opcode == Instruction::ZExt)
        return SrcLT.first;

      // Assume that sext is done using SHL and SRA.
      if (Opcode == Instruction::SExt)
        return SrcLT.first * 2;

      // Just check the op cost. If the operation is legal then assume it
      // costs
      // 1 and multiply by the type-legalization overhead.
      if (!TLI->isOperationExpand(ISD, DstLT.second))
        return SrcLT.first * 1;
    }

    // If we are legalizing by splitting, query the concrete TTI for the cost
    // of casting the original vector twice. We also need to factor in the
    // cost of the split itself. Count that as 1, to be consistent with
    // TLI->getTypeLegalizationCost().
    bool SplitSrc =
        TLI->getTypeAction(Src->getContext(), TLI->getValueType(DL, Src)) ==
        TargetLowering::TypeSplitVector;
    bool SplitDst =
        TLI->getTypeAction(Dst->getContext(), TLI->getValueType(DL, Dst)) ==
        TargetLowering::TypeSplitVector;
    if ((SplitSrc || SplitDst) && SrcVTy->getElementCount().isVector() &&
        DstVTy->getElementCount().isVector()) {
      Type *SplitDstTy = VectorType::getHalfElementsVectorType(DstVTy);
      Type *SplitSrcTy = VectorType::getHalfElementsVectorType(SrcVTy);
      T *TTI = static_cast<T *>(this);
      // If both types need to be split then the split is free.
      InstructionCost SplitCost =
          (!SplitSrc || !SplitDst) ? TTI->getVectorSplitCost() : 0;
      return SplitCost +
             (2 * TTI->getCastInstrCost(Opcode, SplitDstTy, SplitSrcTy, CCH,
                                        CostKind, I));
    }

    // Scalarization cost is Invalid, can't assume any num elements.
    if (isa<ScalableVectorType>(DstVTy))
      return InstructionCost::getInvalid();

    // In other cases where the source or destination are illegal, assume
    // the operation will get scalarized.
    unsigned Num = cast<FixedVectorType>(DstVTy)->getNumElements();
    InstructionCost Cost = thisT()->getCastInstrCost(
        Opcode, Dst->getScalarType(), Src->getScalarType(), CCH, CostKind, I);

    // Return the cost of multiple scalar invocation plus the cost of
    // inserting and extracting the values.
    return getScalarizationOverhead(DstVTy, true, true) + Num * Cost;
  }

  // We already handled vector-to-vector and scalar-to-scalar conversions.
  // This
  // is where we handle bitcast between vectors and scalars. We need to assume
  //  that the conversion is scalarized in one way or another.
  if (Opcode == Instruction::BitCast) {
    // Illegal bitcasts are done by storing and loading from a stack slot.
    return (SrcVTy ? getScalarizationOverhead(SrcVTy, false, true) : 0) +
           (DstVTy ? getScalarizationOverhead(DstVTy, true, false) : 0);
  }

  llvm_unreachable("Unhandled cast")__builtin_unreachable();
}

InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst,
                                         VectorType *VecTy, unsigned Index) {
  return thisT()->getVectorInstrCost(Instruction::ExtractElement, VecTy,
                                     Index) +
         thisT()->getCastInstrCost(Opcode, Dst, VecTy->getElementType(),
                                   TTI::CastContextHint::None,
                                   TTI::TCK_RecipThroughput);
}

InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
                               const Instruction *I = nullptr) {
  return BaseT::getCFInstrCost(Opcode, CostKind, I);
}

InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
                                   CmpInst::Predicate VecPred,
                                   TTI::TargetCostKind CostKind,
                                   const Instruction *I = nullptr) {
  const TargetLoweringBase *TLI = getTLI();
  int ISD = TLI->InstructionOpcodeToISD(Opcode);
  assert(ISD && "Invalid opcode")((void)0);

  // TODO: Handle other cost kinds.
  if (CostKind != TTI::TCK_RecipThroughput)
    return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind,
                                     I);

  // Selects on vectors are actually vector selects.
  if (ISD == ISD::SELECT) {
    assert(CondTy && "CondTy must exist")((void)0);
    if (CondTy->isVectorTy())
      ISD = ISD::VSELECT;
  }
  std::pair<InstructionCost, MVT> LT =
      TLI->getTypeLegalizationCost(DL, ValTy);

  if (!(ValTy->isVectorTy() && !LT.second.isVector()) &&
      !TLI->isOperationExpand(ISD, LT.second)) {
    // The operation is legal. Assume it costs 1. Multiply
    // by the type-legalization overhead.
    return LT.first * 1;
  }

  // Otherwise, assume that the cast is scalarized.
  // TODO: If one of the types get legalized by splitting, handle this
  // similarly to what getCastInstrCost() does.
  if (auto *ValVTy = dyn_cast<VectorType>(ValTy)) {
    unsigned Num = cast<FixedVectorType>(ValVTy)->getNumElements();
    if (CondTy)
      CondTy = CondTy->getScalarType();
    InstructionCost Cost = thisT()->getCmpSelInstrCost(
        Opcode, ValVTy->getScalarType(), CondTy, VecPred, CostKind, I);

    // Return the cost of multiple scalar invocation plus the cost of
    // inserting and extracting the values.
    return getScalarizationOverhead(ValVTy, true, false) + Num * Cost;
  }

  // Unknown scalar opcode.
  return 1;
}

InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
                                   unsigned Index) {
  std::pair<InstructionCost, MVT> LT =
      getTLI()->getTypeLegalizationCost(DL, Val->getScalarType());

  return LT.first;
}

InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src,
                                MaybeAlign Alignment, unsigned AddressSpace,
                                TTI::TargetCostKind CostKind,
                                const Instruction *I = nullptr) {
  assert(!Src->isVoidTy() && "Invalid type")((void)0);
  // Assume types, such as structs, are expensive.
  if (getTLI()->getValueType(DL, Src,  true) == MVT::Other)
    return 4;
  std::pair<InstructionCost, MVT> LT =
      getTLI()->getTypeLegalizationCost(DL, Src);

  // Assuming that all loads of legal types cost 1.
  InstructionCost Cost = LT.first;
  if (CostKind != TTI::TCK_RecipThroughput)
    return Cost;

  if (Src->isVectorTy() &&
      // In practice it's not currently possible to have a change in lane
      // length for extending loads or truncating stores so both types should
      // have the same scalable property.
      TypeSize::isKnownLT(Src->getPrimitiveSizeInBits(),
                          LT.second.getSizeInBits())) {
    // This is a vector load that legalizes to a larger type than the vector
    // itself. Unless the corresponding extending load or truncating store is
    // legal, then this will scalarize.
    TargetLowering::LegalizeAction LA = TargetLowering::Expand;
    EVT MemVT = getTLI()->getValueType(DL, Src);
    if (Opcode == Instruction::Store)
      LA = getTLI()->getTruncStoreAction(LT.second, MemVT);
    else
      LA = getTLI()->getLoadExtAction(ISD::EXTLOAD, LT.second, MemVT);

    if (LA != TargetLowering::Legal && LA != TargetLowering::Custom) {
      // This is a vector load/store for some illegal type that is scalarized.
      // We must account for the cost of building or decomposing the vector.
      Cost += getScalarizationOverhead(cast<VectorType>(Src),
                                       Opcode != Instruction::Store,
                                       Opcode == Instruction::Store);
    }
  }

  return Cost;
}

InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *DataTy,
                                      Align Alignment, unsigned AddressSpace,
                                      TTI::TargetCostKind CostKind) {
  return getCommonMaskedMemoryOpCost(Opcode, DataTy, Alignment, true, false,
                                     CostKind);
}

InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
                                       const Value *Ptr, bool VariableMask,
                                       Align Alignment,
                                       TTI::TargetCostKind CostKind,
                                       const Instruction *I = nullptr) {
  return getCommonMaskedMemoryOpCost(Opcode, DataTy, Alignment, VariableMask,
                                     true, CostKind);
}

InstructionCost getInterleavedMemoryOpCost(
    unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
    Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
    bool UseMaskForCond = false, bool UseMaskForGaps = false) {
  auto *VT = cast<FixedVectorType>(VecTy);
3
←
'VecTy' is a 'FixedVectorType'→

  unsigned NumElts = VT->getNumElements();
  assert(Factor > 1 && NumElts % Factor == 0 && "Invalid interleave factor")((void)0);

  unsigned NumSubElts = NumElts / Factor;
  auto *SubVT = FixedVectorType::get(VT->getElementType(), NumSubElts);

  // Firstly, the cost of load/store operation.
  InstructionCost Cost;
  if (UseMaskForCond || UseMaskForGaps)
4
←
Assuming 'UseMaskForCond' is false→
5
←
Assuming 'UseMaskForGaps' is false→
6
←
Taking false branch→
    Cost = thisT()->getMaskedMemoryOpCost(Opcode, VecTy, Alignment,
                                          AddressSpace, CostKind);
  else
    Cost = thisT()->getMemoryOpCost(Opcode, VecTy, Alignment, AddressSpace,
                                    CostKind);

  // Legalize the vector type, and get the legalized and unlegalized type
  // sizes.
  MVT VecTyLT = getTLI()->getTypeLegalizationCost(DL, VecTy).second;
  unsigned VecTySize = thisT()->getDataLayout().getTypeStoreSize(VecTy);
  unsigned VecTyLTSize = VecTyLT.getStoreSize();

  // Scale the cost of the memory operation by the fraction of legalized
  // instructions that will actually be used. We shouldn't account for the
  // cost of dead instructions since they will be removed.
  //
  // E.g., An interleaved load of factor 8:
  //       %vec = load <16 x i64>, <16 x i64>* %ptr
  //       %v0 = shufflevector %vec, undef, <0, 8>
  //
  // If <16 x i64> is legalized to 8 v2i64 loads, only 2 of the loads will be
  // used (those corresponding to elements [0:1] and [8:9] of the unlegalized
  // type). The other loads are unused.
  //
  // We only scale the cost of loads since interleaved store groups aren't
  // allowed to have gaps.
  if (Opcode == Instruction::Load && VecTySize > VecTyLTSize) {
7
←
Assuming 'Opcode' is equal to Load→
8
←
Assuming 'VecTySize' is <= 'VecTyLTSize'→
9
←
Taking false branch→
    // The number of loads of a legal type it will take to represent a load
    // of the unlegalized vector type.
    unsigned NumLegalInsts = divideCeil(VecTySize, VecTyLTSize);

    // The number of elements of the unlegalized type that correspond to a
    // single legal instruction.
    unsigned NumEltsPerLegalInst = divideCeil(NumElts, NumLegalInsts);

    // Determine which legal instructions will be used.
    BitVector UsedInsts(NumLegalInsts, false);
    for (unsigned Index : Indices)
      for (unsigned Elt = 0; Elt < NumSubElts; ++Elt)
        UsedInsts.set((Index + Elt * Factor) / NumEltsPerLegalInst);

    // Scale the cost of the load by the fraction of legal instructions that
    // will be used.
    Cost *= UsedInsts.count() / NumLegalInsts;
  }

  // Then plus the cost of interleave operation.
  if (Opcode9.1
'Opcode' is equal to Load
1
'Opcode' is equal to Load
1
'Opcode' is equal to Load
 == Instruction::Load) {
10
←
Taking true branch→
    // The interleave cost is similar to extract sub vectors' elements
    // from the wide vector, and insert them into sub vectors.
    //
    // E.g. An interleaved load of factor 2 (with one member of index 0):
    //      %vec = load <8 x i32>, <8 x i32>* %ptr
    //      %v0 = shuffle %vec, undef, <0, 2, 4, 6>         ; Index 0
    // The cost is estimated as extract elements at 0, 2, 4, 6 from the
    // <8 x i32> vector and insert them into a <4 x i32> vector.

    assert(Indices.size() <= Factor &&((void)0)
           "Interleaved memory op has too many members")((void)0);

    for (unsigned Index : Indices) {
11
←
Assuming '__begin3' is equal to '__end3'→
      assert(Index < Factor && "Invalid index for interleaved memory op")((void)0);

      // Extract elements from loaded vector for each sub vector.
      for (unsigned i = 0; i < NumSubElts; i++)
        Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, VT,
                                            Index + i * Factor);
    }

    InstructionCost InsSubCost = 0;
    for (unsigned i = 0; i < NumSubElts; i++)
12
←
Assuming 'i' is < 'NumSubElts'→
13
←
Loop condition is true.  Entering loop body→
      InsSubCost +=
          thisT()->getVectorInstrCost(Instruction::InsertElement, SubVT, i);
14
←
Calling 'X86TTIImpl::getVectorInstrCost'→

    Cost += Indices.size() * InsSubCost;
  } else {
    // The interleave cost is extract all elements from sub vectors, and
    // insert them into the wide vector.
    //
    // E.g. An interleaved store of factor 2:
    //      %v0_v1 = shuffle %v0, %v1, <0, 4, 1, 5, 2, 6, 3, 7>
    //      store <8 x i32> %interleaved.vec, <8 x i32>* %ptr
    // The cost is estimated as extract all elements from both <4 x i32>
    // vectors and insert into the <8 x i32> vector.

    InstructionCost ExtSubCost = 0;
    for (unsigned i = 0; i < NumSubElts; i++)
      ExtSubCost +=
          thisT()->getVectorInstrCost(Instruction::ExtractElement, SubVT, i);
    Cost += ExtSubCost * Factor;

    for (unsigned i = 0; i < NumElts; i++)
      Cost += static_cast<T *>(this)
                  ->getVectorInstrCost(Instruction::InsertElement, VT, i);
  }

  if (!UseMaskForCond)
    return Cost;

  Type *I8Type = Type::getInt8Ty(VT->getContext());
  auto *MaskVT = FixedVectorType::get(I8Type, NumElts);
  SubVT = FixedVectorType::get(I8Type, NumSubElts);

  // The Mask shuffling cost is extract all the elements of the Mask
  // and insert each of them Factor times into the wide vector:
  //
  // E.g. an interleaved group with factor 3:
  //    %mask = icmp ult <8 x i32> %vec1, %vec2
  //    %interleaved.mask = shufflevector <8 x i1> %mask, <8 x i1> undef,
  //        <24 x i32> <0,0,0,1,1,1,2,2,2,3,3,3,4,4,4,5,5,5,6,6,6,7,7,7>
  // The cost is estimated as extract all mask elements from the <8xi1> mask
  // vector and insert them factor times into the <24xi1> shuffled mask
  // vector.
  for (unsigned i = 0; i < NumSubElts; i++)
    Cost +=
        thisT()->getVectorInstrCost(Instruction::ExtractElement, SubVT, i);

  for (unsigned i = 0; i < NumElts; i++)
    Cost +=
        thisT()->getVectorInstrCost(Instruction::InsertElement, MaskVT, i);

  // The Gaps mask is invariant and created outside the loop, therefore the
  // cost of creating it is not accounted for here. However if we have both
  // a MaskForGaps and some other mask that guards the execution of the
  // memory access, we need to account for the cost of And-ing the two masks
  // inside the loop.
  if (UseMaskForGaps)
    Cost += thisT()->getArithmeticInstrCost(BinaryOperator::And, MaskVT,
                                            CostKind);

  return Cost;
}

/// Get intrinsic cost based on arguments.
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
                                      TTI::TargetCostKind CostKind) {
  // Check for generically free intrinsics.
  if (BaseT::getIntrinsicInstrCost(ICA, CostKind) == 0)
    return 0;

  // Assume that target intrinsics are cheap.
  Intrinsic::ID IID = ICA.getID();
  if (Function::isTargetIntrinsic(IID))
    return TargetTransformInfo::TCC_Basic;

  if (ICA.isTypeBasedOnly())
    return getTypeBasedIntrinsicInstrCost(ICA, CostKind);

  Type *RetTy = ICA.getReturnType();

  ElementCount RetVF =
      (RetTy->isVectorTy() ? cast<VectorType>(RetTy)->getElementCount()
                           : ElementCount::getFixed(1));
  const IntrinsicInst *I = ICA.getInst();
  const SmallVectorImpl<const Value *> &Args = ICA.getArgs();
  FastMathFlags FMF = ICA.getFlags();
  switch (IID) {
  default:
    break;

  case Intrinsic::cttz:
    // FIXME: If necessary, this should go in target-specific overrides.
    if (RetVF.isScalar() && getTLI()->isCheapToSpeculateCttz())
      return TargetTransformInfo::TCC_Basic;
    break;

  case Intrinsic::ctlz:
    // FIXME: If necessary, this should go in target-specific overrides.
    if (RetVF.isScalar() && getTLI()->isCheapToSpeculateCtlz())
      return TargetTransformInfo::TCC_Basic;
    break;

  case Intrinsic::memcpy:
    return thisT()->getMemcpyCost(ICA.getInst());

  case Intrinsic::masked_scatter: {
    const Value *Mask = Args[3];
    bool VarMask = !isa<Constant>(Mask);
    Align Alignment = cast<ConstantInt>(Args[2])->getAlignValue();
    return thisT()->getGatherScatterOpCost(Instruction::Store,
                                           ICA.getArgTypes()[0], Args[1],
                                           VarMask, Alignment, CostKind, I);
  }
  case Intrinsic::masked_gather: {
    const Value *Mask = Args[2];
    bool VarMask = !isa<Constant>(Mask);
    Align Alignment = cast<ConstantInt>(Args[1])->getAlignValue();
    return thisT()->getGatherScatterOpCost(Instruction::Load, RetTy, Args[0],
                                           VarMask, Alignment, CostKind, I);
  }
  case Intrinsic::experimental_stepvector: {
    if (isa<ScalableVectorType>(RetTy))
      return BaseT::getIntrinsicInstrCost(ICA, CostKind);
    // The cost of materialising a constant integer vector.
    return TargetTransformInfo::TCC_Basic;
  }
  case Intrinsic::experimental_vector_extract: {
    // FIXME: Handle case where a scalable vector is extracted from a scalable
    // vector
    if (isa<ScalableVectorType>(RetTy))
      return BaseT::getIntrinsicInstrCost(ICA, CostKind);
    unsigned Index = cast<ConstantInt>(Args[1])->getZExtValue();
    return thisT()->getShuffleCost(TTI::SK_ExtractSubvector,
                                   cast<VectorType>(Args[0]->getType()), None,
                                   Index, cast<VectorType>(RetTy));
  }
  case Intrinsic::experimental_vector_insert: {
    // FIXME: Handle case where a scalable vector is inserted into a scalable
    // vector
    if (isa<ScalableVectorType>(Args[1]->getType()))
      return BaseT::getIntrinsicInstrCost(ICA, CostKind);
    unsigned Index = cast<ConstantInt>(Args[2])->getZExtValue();
    return thisT()->getShuffleCost(
        TTI::SK_InsertSubvector, cast<VectorType>(Args[0]->getType()), None,
        Index, cast<VectorType>(Args[1]->getType()));
  }
  case Intrinsic::experimental_vector_reverse: {
    return thisT()->getShuffleCost(TTI::SK_Reverse,
                                   cast<VectorType>(Args[0]->getType()), None,
                                   0, cast<VectorType>(RetTy));
  }
  case Intrinsic::experimental_vector_splice: {
    unsigned Index = cast<ConstantInt>(Args[2])->getZExtValue();
    return thisT()->getShuffleCost(TTI::SK_Splice,
                                   cast<VectorType>(Args[0]->getType()), None,
                                   Index, cast<VectorType>(RetTy));
  }
  case Intrinsic::vector_reduce_add:
  case Intrinsic::vector_reduce_mul:
  case Intrinsic::vector_reduce_and:
  case Intrinsic::vector_reduce_or:
  case Intrinsic::vector_reduce_xor:
  case Intrinsic::vector_reduce_smax:
  case Intrinsic::vector_reduce_smin:
  case Intrinsic::vector_reduce_fmax:
  case Intrinsic::vector_reduce_fmin:
  case Intrinsic::vector_reduce_umax:
  case Intrinsic::vector_reduce_umin: {
    IntrinsicCostAttributes Attrs(IID, RetTy, Args[0]->getType(), FMF, I, 1);
    return getTypeBasedIntrinsicInstrCost(Attrs, CostKind);
  }
  case Intrinsic::vector_reduce_fadd:
  case Intrinsic::vector_reduce_fmul: {
    IntrinsicCostAttributes Attrs(
        IID, RetTy, {Args[0]->getType(), Args[1]->getType()}, FMF, I, 1);
    return getTypeBasedIntrinsicInstrCost(Attrs, CostKind);
  }
  case Intrinsic::fshl:
  case Intrinsic::fshr: {
    if (isa<ScalableVectorType>(RetTy))
      return BaseT::getIntrinsicInstrCost(ICA, CostKind);
    const Value *X = Args[0];
    const Value *Y = Args[1];
    const Value *Z = Args[2];
    TTI::OperandValueProperties OpPropsX, OpPropsY, OpPropsZ, OpPropsBW;
    TTI::OperandValueKind OpKindX = TTI::getOperandInfo(X, OpPropsX);
    TTI::OperandValueKind OpKindY = TTI::getOperandInfo(Y, OpPropsY);
    TTI::OperandValueKind OpKindZ = TTI::getOperandInfo(Z, OpPropsZ);
    TTI::OperandValueKind OpKindBW = TTI::OK_UniformConstantValue;
    OpPropsBW = isPowerOf2_32(RetTy->getScalarSizeInBits()) ? TTI::OP_PowerOf2
                                                            : TTI::OP_None;
    // fshl: (X << (Z % BW)) | (Y >> (BW - (Z % BW)))
    // fshr: (X << (BW - (Z % BW))) | (Y >> (Z % BW))
    InstructionCost Cost = 0;
    Cost +=
        thisT()->getArithmeticInstrCost(BinaryOperator::Or, RetTy, CostKind);
    Cost +=
        thisT()->getArithmeticInstrCost(BinaryOperator::Sub, RetTy, CostKind);
    Cost += thisT()->getArithmeticInstrCost(
        BinaryOperator::Shl, RetTy, CostKind, OpKindX, OpKindZ, OpPropsX);
    Cost += thisT()->getArithmeticInstrCost(
        BinaryOperator::LShr, RetTy, CostKind, OpKindY, OpKindZ, OpPropsY);
    // Non-constant shift amounts requires a modulo.
    if (OpKindZ != TTI::OK_UniformConstantValue &&
        OpKindZ != TTI::OK_NonUniformConstantValue)
      Cost += thisT()->getArithmeticInstrCost(BinaryOperator::URem, RetTy,
                                              CostKind, OpKindZ, OpKindBW,
                                              OpPropsZ, OpPropsBW);
    // For non-rotates (X != Y) we must add shift-by-zero handling costs.
    if (X != Y) {
      Type *CondTy = RetTy->getWithNewBitWidth(1);
      Cost +=
          thisT()->getCmpSelInstrCost(BinaryOperator::ICmp, RetTy, CondTy,
                                      CmpInst::BAD_ICMP_PREDICATE, CostKind);
      Cost +=
          thisT()->getCmpSelInstrCost(BinaryOperator::Select, RetTy, CondTy,
                                      CmpInst::BAD_ICMP_PREDICATE, CostKind);
    }
    return Cost;
  }
  }

  // Assume that we need to scalarize this intrinsic.
  // Compute the scalarization overhead based on Args for a vector
  // intrinsic.
  InstructionCost ScalarizationCost = InstructionCost::getInvalid();
  if (RetVF.isVector() && !RetVF.isScalable()) {
    ScalarizationCost = 0;
    if (!RetTy->isVoidTy())
      ScalarizationCost +=
          getScalarizationOverhead(cast<VectorType>(RetTy), true, false);
    ScalarizationCost +=
        getOperandsScalarizationOverhead(Args, ICA.getArgTypes());
  }

  IntrinsicCostAttributes Attrs(IID, RetTy, ICA.getArgTypes(), FMF, I,
                                ScalarizationCost);
  return thisT()->getTypeBasedIntrinsicInstrCost(Attrs, CostKind);
}

/// Get intrinsic cost based on argument types.
/// If ScalarizationCostPassed is std::numeric_limits<unsigned>::max(), the
/// cost of scalarizing the arguments and the return value will be computed
/// based on types.
InstructionCost
getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
                               TTI::TargetCostKind CostKind) {
  Intrinsic::ID IID = ICA.getID();
  Type *RetTy = ICA.getReturnType();
  const SmallVectorImpl<Type *> &Tys = ICA.getArgTypes();
  FastMathFlags FMF = ICA.getFlags();
  InstructionCost ScalarizationCostPassed = ICA.getScalarizationCost();
  bool SkipScalarizationCost = ICA.skipScalarizationCost();

  VectorType *VecOpTy = nullptr;
  if (!Tys.empty()) {
    // The vector reduction operand is operand 0 except for fadd/fmul.
    // Their operand 0 is a scalar start value, so the vector op is operand 1.
    unsigned VecTyIndex = 0;
    if (IID == Intrinsic::vector_reduce_fadd ||
        IID == Intrinsic::vector_reduce_fmul)
      VecTyIndex = 1;
    assert(Tys.size() > VecTyIndex && "Unexpected IntrinsicCostAttributes")((void)0);
    VecOpTy = dyn_cast<VectorType>(Tys[VecTyIndex]);
  }

  // Library call cost - other than size, make it expensive.
  unsigned SingleCallCost = CostKind == TTI::TCK_CodeSize ? 1 : 10;
  SmallVector<unsigned, 2> ISDs;
  switch (IID) {
  default: {
    // Scalable vectors cannot be scalarized, so return Invalid.
    if (isa<ScalableVectorType>(RetTy) || any_of(Tys, [](const Type *Ty) {
          return isa<ScalableVectorType>(Ty);
        }))
      return InstructionCost::getInvalid();

    // Assume that we need to scalarize this intrinsic.
    InstructionCost ScalarizationCost =
        SkipScalarizationCost ? ScalarizationCostPassed : 0;
    unsigned ScalarCalls = 1;
    Type *ScalarRetTy = RetTy;
    if (auto *RetVTy = dyn_cast<VectorType>(RetTy)) {
      if (!SkipScalarizationCost)
        ScalarizationCost = getScalarizationOverhead(RetVTy, true, false);
      ScalarCalls = std::max(ScalarCalls,
                             cast<FixedVectorType>(RetVTy)->getNumElements());
      ScalarRetTy = RetTy->getScalarType();
    }
    SmallVector<Type *, 4> ScalarTys;
    for (unsigned i = 0, ie = Tys.size(); i != ie; ++i) {
      Type *Ty = Tys[i];
      if (auto *VTy = dyn_cast<VectorType>(Ty)) {
        if (!SkipScalarizationCost)
          ScalarizationCost += getScalarizationOverhead(VTy, false, true);
        ScalarCalls = std::max(ScalarCalls,
                               cast<FixedVectorType>(VTy)->getNumElements());
        Ty = Ty->getScalarType();
      }
      ScalarTys.push_back(Ty);
    }
    if (ScalarCalls == 1)
      return 1; // Return cost of a scalar intrinsic. Assume it to be cheap.

    IntrinsicCostAttributes ScalarAttrs(IID, ScalarRetTy, ScalarTys, FMF);
    InstructionCost ScalarCost =
        thisT()->getIntrinsicInstrCost(ScalarAttrs, CostKind);

    return ScalarCalls * ScalarCost + ScalarizationCost;
  }
  // Look for intrinsics that can be lowered directly or turned into a scalar
  // intrinsic call.
  case Intrinsic::sqrt:
    ISDs.push_back(ISD::FSQRT);
    break;
  case Intrinsic::sin:
    ISDs.push_back(ISD::FSIN);
    break;
  case Intrinsic::cos:
    ISDs.push_back(ISD::FCOS);
    break;
  case Intrinsic::exp:
    ISDs.push_back(ISD::FEXP);
    break;
  case Intrinsic::exp2:
    ISDs.push_back(ISD::FEXP2);
    break;
  case Intrinsic::log:
    ISDs.push_back(ISD::FLOG);
    break;
  case Intrinsic::log10:
    ISDs.push_back(ISD::FLOG10);
    break;
  case Intrinsic::log2:
    ISDs.push_back(ISD::FLOG2);
    break;
  case Intrinsic::fabs:
    ISDs.push_back(ISD::FABS);
    break;
  case Intrinsic::canonicalize:
    ISDs.push_back(ISD::FCANONICALIZE);
    break;
  case Intrinsic::minnum:
    ISDs.push_back(ISD::FMINNUM);
    break;
  case Intrinsic::maxnum:
    ISDs.push_back(ISD::FMAXNUM);
    break;
  case Intrinsic::minimum:
    ISDs.push_back(ISD::FMINIMUM);
    break;
  case Intrinsic::maximum:
    ISDs.push_back(ISD::FMAXIMUM);
    break;
  case Intrinsic::copysign:
    ISDs.push_back(ISD::FCOPYSIGN);
    break;
  case Intrinsic::floor:
    ISDs.push_back(ISD::FFLOOR);
    break;
  case Intrinsic::ceil:
    ISDs.push_back(ISD::FCEIL);
    break;
  case Intrinsic::trunc:
    ISDs.push_back(ISD::FTRUNC);
    break;
  case Intrinsic::nearbyint:
    ISDs.push_back(ISD::FNEARBYINT);
    break;
  case Intrinsic::rint:
    ISDs.push_back(ISD::FRINT);
    break;
  case Intrinsic::round:
    ISDs.push_back(ISD::FROUND);
    break;
  case Intrinsic::roundeven:
    ISDs.push_back(ISD::FROUNDEVEN);
    break;
  case Intrinsic::pow:
    ISDs.push_back(ISD::FPOW);
    break;
  case Intrinsic::fma:
    ISDs.push_back(ISD::FMA);
    break;
  case Intrinsic::fmuladd:
    ISDs.push_back(ISD::FMA);
    break;
  case Intrinsic::experimental_constrained_fmuladd:
    ISDs.push_back(ISD::STRICT_FMA);
    break;
  // FIXME: We should return 0 whenever getIntrinsicCost == TCC_Free.
  case Intrinsic::lifetime_start:
  case Intrinsic::lifetime_end:
  case Intrinsic::sideeffect:
  case Intrinsic::pseudoprobe:
  case Intrinsic::arithmetic_fence:
    return 0;
  case Intrinsic::masked_store: {
    Type *Ty = Tys[0];
    Align TyAlign = thisT()->DL.getABITypeAlign(Ty);
    return thisT()->getMaskedMemoryOpCost(Instruction::Store, Ty, TyAlign, 0,
                                          CostKind);
  }
  case Intrinsic::masked_load: {
    Type *Ty = RetTy;
    Align TyAlign = thisT()->DL.getABITypeAlign(Ty);
    return thisT()->getMaskedMemoryOpCost(Instruction::Load, Ty, TyAlign, 0,
                                          CostKind);
  }
  case Intrinsic::vector_reduce_add:
    return thisT()->getArithmeticReductionCost(Instruction::Add, VecOpTy,
                                               None, CostKind);
  case Intrinsic::vector_reduce_mul:
    return thisT()->getArithmeticReductionCost(Instruction::Mul, VecOpTy,
                                               None, CostKind);
  case Intrinsic::vector_reduce_and:
    return thisT()->getArithmeticReductionCost(Instruction::And, VecOpTy,
                                               None, CostKind);
  case Intrinsic::vector_reduce_or:
    return thisT()->getArithmeticReductionCost(Instruction::Or, VecOpTy, None,
                                               CostKind);
  case Intrinsic::vector_reduce_xor:
    return thisT()->getArithmeticReductionCost(Instruction::Xor, VecOpTy,
                                               None, CostKind);
  case Intrinsic::vector_reduce_fadd:
    return thisT()->getArithmeticReductionCost(Instruction::FAdd, VecOpTy,
                                               FMF, CostKind);
  case Intrinsic::vector_reduce_fmul:
    return thisT()->getArithmeticReductionCost(Instruction::FMul, VecOpTy,
                                               FMF, CostKind);
  case Intrinsic::vector_reduce_smax:
  case Intrinsic::vector_reduce_smin:
  case Intrinsic::vector_reduce_fmax:
  case Intrinsic::vector_reduce_fmin:
    return thisT()->getMinMaxReductionCost(
        VecOpTy, cast<VectorType>(CmpInst::makeCmpResultType(VecOpTy)),
        /*IsUnsigned=*/false, CostKind);
  case Intrinsic::vector_reduce_umax:
  case Intrinsic::vector_reduce_umin:
    return thisT()->getMinMaxReductionCost(
        VecOpTy, cast<VectorType>(CmpInst::makeCmpResultType(VecOpTy)),
        /*IsUnsigned=*/true, CostKind);
  case Intrinsic::abs:
  case Intrinsic::smax:
  case Intrinsic::smin:
  case Intrinsic::umax:
  case Intrinsic::umin: {
    // abs(X) = select(icmp(X,0),X,sub(0,X))
    // minmax(X,Y) = select(icmp(X,Y),X,Y)
    Type *CondTy = RetTy->getWithNewBitWidth(1);
    InstructionCost Cost = 0;
    // TODO: Ideally getCmpSelInstrCost would accept an icmp condition code.
    Cost +=
        thisT()->getCmpSelInstrCost(BinaryOperator::ICmp, RetTy, CondTy,
                                    CmpInst::BAD_ICMP_PREDICATE, CostKind);
    Cost +=
        thisT()->getCmpSelInstrCost(BinaryOperator::Select, RetTy, CondTy,
                                    CmpInst::BAD_ICMP_PREDICATE, CostKind);
    // TODO: Should we add an OperandValueProperties::OP_Zero property?
    if (IID == Intrinsic::abs)
      Cost += thisT()->getArithmeticInstrCost(
          BinaryOperator::Sub, RetTy, CostKind, TTI::OK_UniformConstantValue);
    return Cost;
  }
  case Intrinsic::sadd_sat:
  case Intrinsic::ssub_sat: {
    Type *CondTy = RetTy->getWithNewBitWidth(1);

    Type *OpTy = StructType::create({RetTy, CondTy});
    Intrinsic::ID OverflowOp = IID == Intrinsic::sadd_sat
                                   ? Intrinsic::sadd_with_overflow
                                   : Intrinsic::ssub_with_overflow;

    // SatMax -> Overflow && SumDiff < 0
    // SatMin -> Overflow && SumDiff >= 0
    InstructionCost Cost = 0;
    IntrinsicCostAttributes Attrs(OverflowOp, OpTy, {RetTy, RetTy}, FMF,
                                  nullptr, ScalarizationCostPassed);
    Cost += thisT()->getIntrinsicInstrCost(Attrs, CostKind);
    Cost +=
        thisT()->getCmpSelInstrCost(BinaryOperator::ICmp, RetTy, CondTy,
                                    CmpInst::BAD_ICMP_PREDICATE, CostKind);
    Cost += 2 * thisT()->getCmpSelInstrCost(
                    BinaryOperator::Select, RetTy, CondTy,
                    CmpInst::BAD_ICMP_PREDICATE, CostKind);
    return Cost;
  }
  case Intrinsic::uadd_sat:
  case Intrinsic::usub_sat: {
    Type *CondTy = RetTy->getWithNewBitWidth(1);

    Type *OpTy = StructType::create({RetTy, CondTy});
    Intrinsic::ID OverflowOp = IID == Intrinsic::uadd_sat
                                   ? Intrinsic::uadd_with_overflow
                                   : Intrinsic::usub_with_overflow;

    InstructionCost Cost = 0;
    IntrinsicCostAttributes Attrs(OverflowOp, OpTy, {RetTy, RetTy}, FMF,
                                  nullptr, ScalarizationCostPassed);
    Cost += thisT()->getIntrinsicInstrCost(Attrs, CostKind);
    Cost +=
        thisT()->getCmpSelInstrCost(BinaryOperator::Select, RetTy, CondTy,
                                    CmpInst::BAD_ICMP_PREDICATE, CostKind);
    return Cost;
  }
  case Intrinsic::smul_fix:
  case Intrinsic::umul_fix: {
    unsigned ExtSize = RetTy->getScalarSizeInBits() * 2;
    Type *ExtTy = RetTy->getWithNewBitWidth(ExtSize);

    unsigned ExtOp =
        IID == Intrinsic::smul_fix ? Instruction::SExt : Instruction::ZExt;
    TTI::CastContextHint CCH = TTI::CastContextHint::None;

    InstructionCost Cost = 0;
    Cost += 2 * thisT()->getCastInstrCost(ExtOp, ExtTy, RetTy, CCH, CostKind);
    Cost +=
        thisT()->getArithmeticInstrCost(Instruction::Mul, ExtTy, CostKind);
    Cost += 2 * thisT()->getCastInstrCost(Instruction::Trunc, RetTy, ExtTy,
                                          CCH, CostKind);
    Cost += thisT()->getArithmeticInstrCost(Instruction::LShr, RetTy,
                                            CostKind, TTI::OK_AnyValue,
                                            TTI::OK_UniformConstantValue);
    Cost += thisT()->getArithmeticInstrCost(Instruction::Shl, RetTy, CostKind,
                                            TTI::OK_AnyValue,
                                            TTI::OK_UniformConstantValue);
    Cost += thisT()->getArithmeticInstrCost(Instruction::Or, RetTy, CostKind);
    return Cost;
  }
  case Intrinsic::sadd_with_overflow:
  case Intrinsic::ssub_with_overflow: {
    Type *SumTy = RetTy->getContainedType(0);
    Type *OverflowTy = RetTy->getContainedType(1);
    unsigned Opcode = IID == Intrinsic::sadd_with_overflow
                          ? BinaryOperator::Add
                          : BinaryOperator::Sub;

    //   LHSSign -> LHS >= 0
    //   RHSSign -> RHS >= 0
    //   SumSign -> Sum >= 0
    //
    //   Add:
    //   Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
    //   Sub:
    //   Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
    InstructionCost Cost = 0;
    Cost += thisT()->getArithmeticInstrCost(Opcode, SumTy, CostKind);
    Cost += 3 * thisT()->getCmpSelInstrCost(
                    Instruction::ICmp, SumTy, OverflowTy,
                    CmpInst::BAD_ICMP_PREDICATE, CostKind);
    Cost += 2 * thisT()->getCmpSelInstrCost(
                    Instruction::Select, OverflowTy, OverflowTy,
                    CmpInst::BAD_ICMP_PREDICATE, CostKind);
    Cost += thisT()->getArithmeticInstrCost(BinaryOperator::And, OverflowTy,
                                            CostKind);
    return Cost;
  }
  case Intrinsic::uadd_with_overflow:
  case Intrinsic::usub_with_overflow: {
    Type *SumTy = RetTy->getContainedType(0);
    Type *OverflowTy = RetTy->getContainedType(1);
    unsigned Opcode = IID == Intrinsic::uadd_with_overflow
                          ? BinaryOperator::Add
                          : BinaryOperator::Sub;

    InstructionCost Cost = 0;
    Cost += thisT()->getArithmeticInstrCost(Opcode, SumTy, CostKind);
    Cost +=
        thisT()->getCmpSelInstrCost(BinaryOperator::ICmp, SumTy, OverflowTy,
                                    CmpInst::BAD_ICMP_PREDICATE, CostKind);
    return Cost;
  }
  case Intrinsic::smul_with_overflow:
  case Intrinsic::umul_with_overflow: {
    Type *MulTy = RetTy->getContainedType(0);
    Type *OverflowTy = RetTy->getContainedType(1);
    unsigned ExtSize = MulTy->getScalarSizeInBits() * 2;
    Type *ExtTy = MulTy->getWithNewBitWidth(ExtSize);

    unsigned ExtOp =
        IID == Intrinsic::smul_fix ? Instruction::SExt : Instruction::ZExt;
    TTI::CastContextHint CCH = TTI::CastContextHint::None;

    InstructionCost Cost = 0;
    Cost += 2 * thisT()->getCastInstrCost(ExtOp, ExtTy, MulTy, CCH, CostKind);
    Cost +=
        thisT()->getArithmeticInstrCost(Instruction::Mul, ExtTy, CostKind);
    Cost += 2 * thisT()->getCastInstrCost(Instruction::Trunc, MulTy, ExtTy,
                                          CCH, CostKind);
    Cost += thisT()->getArithmeticInstrCost(Instruction::LShr, MulTy,
                                            CostKind, TTI::OK_AnyValue,
                                            TTI::OK_UniformConstantValue);

    if (IID == Intrinsic::smul_with_overflow)
      Cost += thisT()->getArithmeticInstrCost(Instruction::AShr, MulTy,
                                              CostKind, TTI::OK_AnyValue,
                                              TTI::OK_UniformConstantValue);

    Cost +=
        thisT()->getCmpSelInstrCost(BinaryOperator::ICmp, MulTy, OverflowTy,
                                    CmpInst::BAD_ICMP_PREDICATE, CostKind);
    return Cost;
  }
  case Intrinsic::ctpop:
    ISDs.push_back(ISD::CTPOP);
    // In case of legalization use TCC_Expensive. This is cheaper than a
    // library call but still not a cheap instruction.
    SingleCallCost = TargetTransformInfo::TCC_Expensive;
    break;
  case Intrinsic::ctlz:
    ISDs.push_back(ISD::CTLZ);
    break;
  case Intrinsic::cttz:
    ISDs.push_back(ISD::CTTZ);
    break;
  case Intrinsic::bswap:
    ISDs.push_back(ISD::BSWAP);
    break;
  case Intrinsic::bitreverse:
    ISDs.push_back(ISD::BITREVERSE);
    break;
  }

  const TargetLoweringBase *TLI = getTLI();
  std::pair<InstructionCost, MVT> LT =
      TLI->getTypeLegalizationCost(DL, RetTy);

  SmallVector<InstructionCost, 2> LegalCost;
  SmallVector<InstructionCost, 2> CustomCost;
  for (unsigned ISD : ISDs) {
    if (TLI->isOperationLegalOrPromote(ISD, LT.second)) {
      if (IID == Intrinsic::fabs && LT.second.isFloatingPoint() &&
          TLI->isFAbsFree(LT.second)) {
        return 0;
      }

      // The operation is legal. Assume it costs 1.
      // If the type is split to multiple registers, assume that there is some
      // overhead to this.
      // TODO: Once we have extract/insert subvector cost we need to use them.
      if (LT.first > 1)
        LegalCost.push_back(LT.first * 2);
      else
        LegalCost.push_back(LT.first * 1);
    } else if (!TLI->isOperationExpand(ISD, LT.second)) {
      // If the operation is custom lowered then assume
      // that the code is twice as expensive.
      CustomCost.push_back(LT.first * 2);
    }
  }

  auto *MinLegalCostI = std::min_element(LegalCost.begin(), LegalCost.end());
  if (MinLegalCostI != LegalCost.end())
    return *MinLegalCostI;

  auto MinCustomCostI =
      std::min_element(CustomCost.begin(), CustomCost.end());
  if (MinCustomCostI != CustomCost.end())
    return *MinCustomCostI;

  // If we can't lower fmuladd into an FMA estimate the cost as a floating
  // point mul followed by an add.
  if (IID == Intrinsic::fmuladd)
    return thisT()->getArithmeticInstrCost(BinaryOperator::FMul, RetTy,
                                           CostKind) +
           thisT()->getArithmeticInstrCost(BinaryOperator::FAdd, RetTy,
                                           CostKind);
  if (IID == Intrinsic::experimental_constrained_fmuladd) {
    IntrinsicCostAttributes FMulAttrs(
      Intrinsic::experimental_constrained_fmul, RetTy, Tys);
    IntrinsicCostAttributes FAddAttrs(
      Intrinsic::experimental_constrained_fadd, RetTy, Tys);
    return thisT()->getIntrinsicInstrCost(FMulAttrs, CostKind) +
           thisT()->getIntrinsicInstrCost(FAddAttrs, CostKind);
  }

  // Else, assume that we need to scalarize this intrinsic. For math builtins
  // this will emit a costly libcall, adding call overhead and spills. Make it
  // very expensive.
  if (auto *RetVTy = dyn_cast<VectorType>(RetTy)) {
    // Scalable vectors cannot be scalarized, so return Invalid.
    if (isa<ScalableVectorType>(RetTy) || any_of(Tys, [](const Type *Ty) {
          return isa<ScalableVectorType>(Ty);
        }))
      return InstructionCost::getInvalid();

    InstructionCost ScalarizationCost =
        SkipScalarizationCost ? ScalarizationCostPassed
                              : getScalarizationOverhead(RetVTy, true, false);

    unsigned ScalarCalls = cast<FixedVectorType>(RetVTy)->getNumElements();
    SmallVector<Type *, 4> ScalarTys;
    for (unsigned i = 0, ie = Tys.size(); i != ie; ++i) {
      Type *Ty = Tys[i];
      if (Ty->isVectorTy())
        Ty = Ty->getScalarType();
      ScalarTys.push_back(Ty);
    }
    IntrinsicCostAttributes Attrs(IID, RetTy->getScalarType(), ScalarTys, FMF);
    InstructionCost ScalarCost =
        thisT()->getIntrinsicInstrCost(Attrs, CostKind);
    for (unsigned i = 0, ie = Tys.size(); i != ie; ++i) {
      if (auto *VTy = dyn_cast<VectorType>(Tys[i])) {
        if (!ICA.skipScalarizationCost())
          ScalarizationCost += getScalarizationOverhead(VTy, false, true);
        ScalarCalls = std::max(ScalarCalls,
                               cast<FixedVectorType>(VTy)->getNumElements());
      }
    }
    return ScalarCalls * ScalarCost + ScalarizationCost;
  }

  // This is going to be turned into a library call, make it expensive.
  return SingleCallCost;
}

/// Compute a cost of the given call instruction.
///
/// Compute the cost of calling function F with return type RetTy and
/// argument types Tys. F might be nullptr, in this case the cost of an
/// arbitrary call with the specified signature will be returned.
/// This is used, for instance,  when we estimate call of a vector
/// counterpart of the given function.
/// \param F Called function, might be nullptr.
/// \param RetTy Return value types.
/// \param Tys Argument types.
/// \returns The cost of Call instruction.
InstructionCost
getCallInstrCost(Function *F, Type *RetTy, ArrayRef<Type *> Tys,
                 TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency) {
  return 10;
}

unsigned getNumberOfParts(Type *Tp) {
  std::pair<InstructionCost, MVT> LT =
      getTLI()->getTypeLegalizationCost(DL, Tp);
  return *LT.first.getValue();
}

InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *,
                                          const SCEV *) {
  return 0;
}

/// Try to calculate arithmetic and shuffle op costs for reduction intrinsics.
/// We're assuming that reduction operation are performing the following way:
///
/// %val1 = shufflevector<n x t> %val, <n x t> %undef,
/// <n x i32> <i32 n/2, i32 n/2 + 1, ..., i32 n, i32 undef, ..., i32 undef>
///            \----------------v-------------/  \----------v------------/
///                            n/2 elements               n/2 elements
/// %red1 = op <n x t> %val, <n x t> val1
/// After this operation we have a vector %red1 where only the first n/2
/// elements are meaningful, the second n/2 elements are undefined and can be
/// dropped. All other operations are actually working with the vector of
/// length n/2, not n, though the real vector length is still n.
/// %val2 = shufflevector<n x t> %red1, <n x t> %undef,
/// <n x i32> <i32 n/4, i32 n/4 + 1, ..., i32 n/2, i32 undef, ..., i32 undef>
///            \----------------v-------------/  \----------v------------/
///                            n/4 elements               3*n/4 elements
/// %red2 = op <n x t> %red1, <n x t> val2  - working with the vector of
/// length n/2, the resulting vector has length n/4 etc.
///
/// The cost model should take into account that the actual length of the
/// vector is reduced on each iteration.
InstructionCost getTreeReductionCost(unsigned Opcode, VectorType *Ty,
                                     TTI::TargetCostKind CostKind) {
  Type *ScalarTy = Ty->getElementType();
  unsigned NumVecElts = cast<FixedVectorType>(Ty)->getNumElements();
  if ((Opcode == Instruction::Or || Opcode == Instruction::And) &&
      ScalarTy == IntegerType::getInt1Ty(Ty->getContext()) &&
      NumVecElts >= 2) {
    // Or reduction for i1 is represented as:
    // %val = bitcast <ReduxWidth x i1> to iReduxWidth
    // %res = cmp ne iReduxWidth %val, 0
    // And reduction for i1 is represented as:
    // %val = bitcast <ReduxWidth x i1> to iReduxWidth
    // %res = cmp eq iReduxWidth %val, 11111
    Type *ValTy = IntegerType::get(Ty->getContext(), NumVecElts);
    return thisT()->getCastInstrCost(Instruction::BitCast, ValTy, Ty,
                                     TTI::CastContextHint::None, CostKind) +
           thisT()->getCmpSelInstrCost(Instruction::ICmp, ValTy,
                                       CmpInst::makeCmpResultType(ValTy),
                                       CmpInst::BAD_ICMP_PREDICATE, CostKind);
  }
  unsigned NumReduxLevels = Log2_32(NumVecElts);
  InstructionCost ArithCost = 0;
  InstructionCost ShuffleCost = 0;
  std::pair<InstructionCost, MVT> LT =
      thisT()->getTLI()->getTypeLegalizationCost(DL, Ty);
  unsigned LongVectorCount = 0;
  unsigned MVTLen =
      LT.second.isVector() ? LT.second.getVectorNumElements() : 1;
  while (NumVecElts > MVTLen) {
    NumVecElts /= 2;
    VectorType *SubTy = FixedVectorType::get(ScalarTy, NumVecElts);
    ShuffleCost += thisT()->getShuffleCost(TTI::SK_ExtractSubvector, Ty, None,
                                           NumVecElts, SubTy);
    ArithCost += thisT()->getArithmeticInstrCost(Opcode, SubTy, CostKind);
    Ty = SubTy;
    ++LongVectorCount;
  }

  NumReduxLevels -= LongVectorCount;

  // The minimal length of the vector is limited by the real length of vector
  // operations performed on the current platform. That's why several final
  // reduction operations are performed on the vectors with the same
  // architecture-dependent length.

  // By default reductions need one shuffle per reduction level.
  ShuffleCost += NumReduxLevels * thisT()->getShuffleCost(
                                   TTI::SK_PermuteSingleSrc, Ty, None, 0, Ty);
  ArithCost += NumReduxLevels * thisT()->getArithmeticInstrCost(Opcode, Ty);
  return ShuffleCost + ArithCost +
         thisT()->getVectorInstrCost(Instruction::ExtractElement, Ty, 0);
}

/// Try to calculate the cost of performing strict (in-order) reductions,
/// which involves doing a sequence of floating point additions in lane
/// order, starting with an initial value. For example, consider a scalar
/// initial value 'InitVal' of type float and a vector of type <4 x float>:
///
///   Vector = <float %v0, float %v1, float %v2, float %v3>
///
///   %add1 = %InitVal + %v0
///   %add2 = %add1 + %v1
///   %add3 = %add2 + %v2
///   %add4 = %add3 + %v3
///
/// As a simple estimate we can say the cost of such a reduction is 4 times
/// the cost of a scalar FP addition. We can only estimate the costs for
/// fixed-width vectors here because for scalable vectors we do not know the
/// runtime number of operations.
InstructionCost getOrderedReductionCost(unsigned Opcode, VectorType *Ty,
                                        TTI::TargetCostKind CostKind) {
  // Targets must implement a default value for the scalable case, since
  // we don't know how many lanes the vector has.
  if (isa<ScalableVectorType>(Ty))
    return InstructionCost::getInvalid();

  auto *VTy = cast<FixedVectorType>(Ty);
  InstructionCost ExtractCost =
      getScalarizationOverhead(VTy, /*Insert=*/false, /*Extract=*/true);
  InstructionCost ArithCost = thisT()->getArithmeticInstrCost(
      Opcode, VTy->getElementType(), CostKind);
  ArithCost *= VTy->getNumElements();

  return ExtractCost + ArithCost;
}

InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
                                           Optional<FastMathFlags> FMF,
                                           TTI::TargetCostKind CostKind) {
  if (TTI::requiresOrderedReduction(FMF))
    return getOrderedReductionCost(Opcode, Ty, CostKind);
  return getTreeReductionCost(Opcode, Ty, CostKind);
}

/// Try to calculate op costs for min/max reduction operations.
/// \param CondTy Conditional type for the Select instruction.
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy,
                                       bool IsUnsigned,
                                       TTI::TargetCostKind CostKind) {
  Type *ScalarTy = Ty->getElementType();
  Type *ScalarCondTy = CondTy->getElementType();
  unsigned NumVecElts = cast<FixedVectorType>(Ty)->getNumElements();
  unsigned NumReduxLevels = Log2_32(NumVecElts);
  unsigned CmpOpcode;
  if (Ty->isFPOrFPVectorTy()) {
    CmpOpcode = Instruction::FCmp;
  } else {
    assert(Ty->isIntOrIntVectorTy() &&((void)0)
           "expecting floating point or integer type for min/max reduction")((void)0);
    CmpOpcode = Instruction::ICmp;
  }
  InstructionCost MinMaxCost = 0;
  InstructionCost ShuffleCost = 0;
  std::pair<InstructionCost, MVT> LT =
      thisT()->getTLI()->getTypeLegalizationCost(DL, Ty);
  unsigned LongVectorCount = 0;
  unsigned MVTLen =
      LT.second.isVector() ? LT.second.getVectorNumElements() : 1;
  while (NumVecElts > MVTLen) {
    NumVecElts /= 2;
    auto *SubTy = FixedVectorType::get(ScalarTy, NumVecElts);
    CondTy = FixedVectorType::get(ScalarCondTy, NumVecElts);

    ShuffleCost += thisT()->getShuffleCost(TTI::SK_ExtractSubvector, Ty, None,
                                           NumVecElts, SubTy);
    MinMaxCost +=
        thisT()->getCmpSelInstrCost(CmpOpcode, SubTy, CondTy,
                                    CmpInst::BAD_ICMP_PREDICATE, CostKind) +
        thisT()->getCmpSelInstrCost(Instruction::Select, SubTy, CondTy,
                                    CmpInst::BAD_ICMP_PREDICATE, CostKind);
    Ty = SubTy;
    ++LongVectorCount;
  }

  NumReduxLevels -= LongVectorCount;

  // The minimal length of the vector is limited by the real length of vector
  // operations performed on the current platform. That's why several final
  // reduction opertions are perfomed on the vectors with the same
  // architecture-dependent length.
  ShuffleCost += NumReduxLevels * thisT()->getShuffleCost(
                                   TTI::SK_PermuteSingleSrc, Ty, None, 0, Ty);
  MinMaxCost +=
      NumReduxLevels *
      (thisT()->getCmpSelInstrCost(CmpOpcode, Ty, CondTy,
                                   CmpInst::BAD_ICMP_PREDICATE, CostKind) +
       thisT()->getCmpSelInstrCost(Instruction::Select, Ty, CondTy,
                                   CmpInst::BAD_ICMP_PREDICATE, CostKind));
  // The last min/max should be in vector registers and we counted it above.
  // So just need a single extractelement.
  return ShuffleCost + MinMaxCost +
         thisT()->getVectorInstrCost(Instruction::ExtractElement, Ty, 0);
}

InstructionCost getExtendedAddReductionCost(bool IsMLA, bool IsUnsigned,
                                            Type *ResTy, VectorType *Ty,
                                            TTI::TargetCostKind CostKind) {
  // Without any native support, this is equivalent to the cost of
  // vecreduce.add(ext) or if IsMLA vecreduce.add(mul(ext, ext))
  VectorType *ExtTy = VectorType::get(ResTy, Ty);
  InstructionCost RedCost = thisT()->getArithmeticReductionCost(
      Instruction::Add, ExtTy, None, CostKind);
  InstructionCost MulCost = 0;
  InstructionCost ExtCost = thisT()->getCastInstrCost(
      IsUnsigned ? Instruction::ZExt : Instruction::SExt, ExtTy, Ty,
      TTI::CastContextHint::None, CostKind);
  if (IsMLA) {
    MulCost =
        thisT()->getArithmeticInstrCost(Instruction::Mul, ExtTy, CostKind);
    ExtCost *= 2;
  }

  return RedCost + MulCost + ExtCost;
}

InstructionCost getVectorSplitCost() { return 1; }

/// @}
2193};

2195/// Concrete BasicTTIImpl that can be used if no further customization
2196/// is needed.
2197class BasicTTIImpl : public BasicTTIImplBase<BasicTTIImpl> {
using BaseT = BasicTTIImplBase<BasicTTIImpl>;

friend class BasicTTIImplBase<BasicTTIImpl>;

const TargetSubtargetInfo *ST;
const TargetLoweringBase *TLI;

const TargetSubtargetInfo *getST() const { return ST; }
const TargetLoweringBase *getTLI() const { return TLI; }

2208public:
explicit BasicTTIImpl(const TargetMachine *TM, const Function &F);
2210};

2212} // end namespace llvm

2214#endif // LLVM_CODEGEN_BASICTTIIMPL_H

←

/usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Support/MachineValueType.h

1//===- Support/MachineValueType.h - Machine-Level types ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the set of machine-level target independent types which
10// legal values in the code generator use.
11//
12//===----------------------------------------------------------------------===//

14#ifndef LLVM_SUPPORT_MACHINEVALUETYPE_H
15#define LLVM_SUPPORT_MACHINEVALUETYPE_H

17#include "llvm/ADT/Sequence.h"
18#include "llvm/ADT/iterator_range.h"
19#include "llvm/Support/ErrorHandling.h"
20#include "llvm/Support/MathExtras.h"
21#include "llvm/Support/TypeSize.h"
22#include <cassert>

24namespace llvm {

class Type;

/// Machine Value Type. Every type that is supported natively by some
/// processor targeted by LLVM occurs here. This means that any legal value
/// type can be represented by an MVT.
class MVT {
public:
  enum SimpleValueType : uint8_t {
    // clang-format off

    // Simple value types that aren't explicitly part of this enumeration
    // are considered extended value types.
    INVALID_SIMPLE_VALUE_TYPE = 0,

    // If you change this numbering, you must change the values in
    // ValueTypes.td as well!
    Other          =   1,   // This is a non-standard value
    i1             =   2,   // This is a 1 bit integer value
    i8             =   3,   // This is an 8 bit integer value
    i16            =   4,   // This is a 16 bit integer value
    i32            =   5,   // This is a 32 bit integer value
    i64            =   6,   // This is a 64 bit integer value
    i128           =   7,   // This is a 128 bit integer value

    FIRST_INTEGER_VALUETYPE = i1,
    LAST_INTEGER_VALUETYPE  = i128,

    bf16           =   8,   // This is a 16 bit brain floating point value
    f16            =   9,   // This is a 16 bit floating point value
    f32            =  10,   // This is a 32 bit floating point value
    f64            =  11,   // This is a 64 bit floating point value
    f80            =  12,   // This is a 80 bit floating point value
    f128           =  13,   // This is a 128 bit floating point value
    ppcf128        =  14,   // This is a PPC 128-bit floating point value

    FIRST_FP_VALUETYPE = bf16,
    LAST_FP_VALUETYPE  = ppcf128,

    v1i1           =  15,   //    1 x i1
    v2i1           =  16,   //    2 x i1
    v4i1           =  17,   //    4 x i1
    v8i1           =  18,   //    8 x i1
    v16i1          =  19,   //   16 x i1
    v32i1          =  20,   //   32 x i1
    v64i1          =  21,   //   64 x i1
    v128i1         =  22,   //  128 x i1
    v256i1         =  23,   //  256 x i1
    v512i1         =  24,   //  512 x i1
    v1024i1        =  25,   // 1024 x i1

    v1i8           =  26,   //    1 x i8
    v2i8           =  27,   //    2 x i8
    v4i8           =  28,   //    4 x i8
    v8i8           =  29,   //    8 x i8
    v16i8          =  30,   //   16 x i8
    v32i8          =  31,   //   32 x i8
    v64i8          =  32,   //   64 x i8
    v128i8         =  33,   //  128 x i8
    v256i8         =  34,   //  256 x i8
    v512i8         =  35,   //  512 x i8
    v1024i8        =  36,   // 1024 x i8

    v1i16          =  37,   //   1 x i16
    v2i16          =  38,   //   2 x i16
    v3i16          =  39,   //   3 x i16
    v4i16          =  40,   //   4 x i16
    v8i16          =  41,   //   8 x i16
    v16i16         =  42,   //  16 x i16
    v32i16         =  43,   //  32 x i16
    v64i16         =  44,   //  64 x i16
    v128i16        =  45,   // 128 x i16
    v256i16        =  46,   // 256 x i16
    v512i16        =  47,   // 512 x i16

    v1i32          =  48,   //    1 x i32
    v2i32          =  49,   //    2 x i32
    v3i32          =  50,   //    3 x i32
    v4i32          =  51,   //    4 x i32
    v5i32          =  52,   //    5 x i32
    v6i32          =  53,   //    6 x i32
    v7i32          =  54,   //    7 x i32
    v8i32          =  55,   //    8 x i32
    v16i32         =  56,   //   16 x i32
    v32i32         =  57,   //   32 x i32
    v64i32         =  58,   //   64 x i32
    v128i32        =  59,   //  128 x i32
    v256i32        =  60,   //  256 x i32
    v512i32        =  61,   //  512 x i32
    v1024i32       =  62,   // 1024 x i32
    v2048i32       =  63,   // 2048 x i32

    v1i64          =  64,   //   1 x i64
    v2i64          =  65,   //   2 x i64
    v3i64          =  66,   //   3 x i64
    v4i64          =  67,   //   4 x i64
    v8i64          =  68,   //   8 x i64
    v16i64         =  69,   //  16 x i64
    v32i64         =  70,   //  32 x i64
    v64i64         =  71,   //  64 x i64
    v128i64        =  72,   // 128 x i64
    v256i64        =  73,   // 256 x i64

    v1i128         =  74,   //  1 x i128

    FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
    LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i128,

    v1f16          =  75,   //    1 x f16
    v2f16          =  76,   //    2 x f16
    v3f16          =  77,   //    3 x f16
    v4f16          =  78,   //    4 x f16
    v8f16          =  79,   //    8 x f16
    v16f16         =  80,   //   16 x f16
    v32f16         =  81,   //   32 x f16
    v64f16         =  82,   //   64 x f16
    v128f16        =  83,   //  128 x f16
    v256f16        =  84,   //  256 x f16
    v512f16        =  85,   //  256 x f16

    v2bf16         =  86,   //    2 x bf16
    v3bf16         =  87,   //    3 x bf16
    v4bf16         =  88,   //    4 x bf16
    v8bf16         =  89,   //    8 x bf16
    v16bf16        =  90,   //   16 x bf16
    v32bf16        =  91,   //   32 x bf16
    v64bf16        =  92,   //   64 x bf16
    v128bf16       =  93,   //  128 x bf16

    v1f32          =  94,   //    1 x f32
    v2f32          =  95,   //    2 x f32
    v3f32          =  96,   //    3 x f32
    v4f32          =  97,   //    4 x f32
    v5f32          =  98,   //    5 x f32
    v6f32          =  99,   //    6 x f32
    v7f32          = 100,   //    7 x f32
    v8f32          = 101,   //    8 x f32
    v16f32         = 102,   //   16 x f32
    v32f32         = 103,   //   32 x f32
    v64f32         = 104,   //   64 x f32
    v128f32        = 105,   //  128 x f32
    v256f32        = 106,   //  256 x f32
    v512f32        = 107,   //  512 x f32
    v1024f32       = 108,   // 1024 x f32
    v2048f32       = 109,   // 2048 x f32

    v1f64          = 110,   //    1 x f64
    v2f64          = 111,   //    2 x f64
    v3f64          = 112,   //    3 x f64
    v4f64          = 113,   //    4 x f64
    v8f64          = 114,   //    8 x f64
    v16f64         = 115,   //   16 x f64
    v32f64         = 116,   //   32 x f64
    v64f64         = 117,   //   64 x f64
    v128f64        = 118,   //  128 x f64
    v256f64        = 119,   //  256 x f64

    FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE = v1f16,
    LAST_FP_FIXEDLEN_VECTOR_VALUETYPE = v256f64,

    FIRST_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
    LAST_FIXEDLEN_VECTOR_VALUETYPE = v256f64,

    nxv1i1         = 120,   // n x  1 x i1
    nxv2i1         = 121,   // n x  2 x i1
    nxv4i1         = 122,   // n x  4 x i1
    nxv8i1         = 123,   // n x  8 x i1
    nxv16i1        = 124,   // n x 16 x i1
    nxv32i1        = 125,   // n x 32 x i1
    nxv64i1        = 126,   // n x 64 x i1

    nxv1i8         = 127,   // n x  1 x i8
    nxv2i8         = 128,   // n x  2 x i8
    nxv4i8         = 129,   // n x  4 x i8
    nxv8i8         = 130,   // n x  8 x i8
    nxv16i8        = 131,   // n x 16 x i8
    nxv32i8        = 132,   // n x 32 x i8
    nxv64i8        = 133,   // n x 64 x i8

    nxv1i16        = 134,  // n x  1 x i16
    nxv2i16        = 135,  // n x  2 x i16
    nxv4i16        = 136,  // n x  4 x i16
    nxv8i16        = 137,  // n x  8 x i16
    nxv16i16       = 138,  // n x 16 x i16
    nxv32i16       = 139,  // n x 32 x i16

    nxv1i32        = 140,  // n x  1 x i32
    nxv2i32        = 141,  // n x  2 x i32
    nxv4i32        = 142,  // n x  4 x i32
    nxv8i32        = 143,  // n x  8 x i32
    nxv16i32       = 144,  // n x 16 x i32
    nxv32i32       = 145,  // n x 32 x i32

    nxv1i64        = 146,  // n x  1 x i64
    nxv2i64        = 147,  // n x  2 x i64
    nxv4i64        = 148,  // n x  4 x i64
    nxv8i64        = 149,  // n x  8 x i64
    nxv16i64       = 150,  // n x 16 x i64
    nxv32i64       = 151,  // n x 32 x i64

    FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv1i1,
    LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv32i64,

    nxv1f16        = 152,  // n x  1 x f16
    nxv2f16        = 153,  // n x  2 x f16
    nxv4f16        = 154,  // n x  4 x f16
    nxv8f16        = 155,  // n x  8 x f16
    nxv16f16       = 156,  // n x 16 x f16
    nxv32f16       = 157,  // n x 32 x f16

    nxv1bf16       = 158,  // n x  1 x bf16
    nxv2bf16       = 159,  // n x  2 x bf16
    nxv4bf16       = 160,  // n x  4 x bf16
    nxv8bf16       = 161,  // n x  8 x bf16

    nxv1f32        = 162,  // n x  1 x f32
    nxv2f32        = 163,  // n x  2 x f32
    nxv4f32        = 164,  // n x  4 x f32
    nxv8f32        = 165,  // n x  8 x f32
    nxv16f32       = 166,  // n x 16 x f32

    nxv1f64        = 167,  // n x  1 x f64
    nxv2f64        = 168,  // n x  2 x f64
    nxv4f64        = 169,  // n x  4 x f64
    nxv8f64        = 170,  // n x  8 x f64

    FIRST_FP_SCALABLE_VECTOR_VALUETYPE = nxv1f16,
    LAST_FP_SCALABLE_VECTOR_VALUETYPE = nxv8f64,

    FIRST_SCALABLE_VECTOR_VALUETYPE = nxv1i1,
    LAST_SCALABLE_VECTOR_VALUETYPE = nxv8f64,

    FIRST_VECTOR_VALUETYPE = v1i1,
    LAST_VECTOR_VALUETYPE  = nxv8f64,

    x86mmx         = 171,    // This is an X86 MMX value

    Glue           = 172,    // This glues nodes together during pre-RA sched

    isVoid         = 173,    // This has no value

    Untyped        = 174,    // This value takes a register, but has
                             // unspecified type.  The register class
                             // will be determined by the opcode.

    funcref        = 175,    // WebAssembly's funcref type
    externref      = 176,    // WebAssembly's externref type
    x86amx         = 177,    // This is an X86 AMX value
    i64x8          = 178,    // 8 Consecutive GPRs (AArch64)

    FIRST_VALUETYPE =  1,    // This is always the beginning of the list.
    LAST_VALUETYPE = i64x8,  // This always remains at the end of the list.
    VALUETYPE_SIZE = LAST_VALUETYPE + 1,

    // This is the current maximum for LAST_VALUETYPE.
    // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
    // This value must be a multiple of 32.
    MAX_ALLOWED_VALUETYPE = 192,

    // A value of type llvm::TokenTy
    token          = 248,

    // This is MDNode or MDString.
    Metadata       = 249,

    // An int value the size of the pointer of the current
    // target to any address space. This must only be used internal to
    // tblgen. Other than for overloading, we treat iPTRAny the same as iPTR.
    iPTRAny        = 250,

    // A vector with any length and element size. This is used
    // for intrinsics that have overloadings based on vector types.
    // This is only for tblgen's consumption!
    vAny           = 251,

    // Any floating-point or vector floating-point value. This is used
    // for intrinsics that have overloadings based on floating-point types.
    // This is only for tblgen's consumption!
    fAny           = 252,

    // An integer or vector integer value of any bit width. This is
    // used for intrinsics that have overloadings based on integer bit widths.
    // This is only for tblgen's consumption!
    iAny           = 253,

    // An int value the size of the pointer of the current
    // target.  This should only be used internal to tblgen!
    iPTR           = 254,

    // Any type. This is used for intrinsics that have overloadings.
    // This is only for tblgen's consumption!
    Any            = 255

    // clang-format on
  };

  SimpleValueType SimpleTy = INVALID_SIMPLE_VALUE_TYPE;

  constexpr MVT() = default;
  constexpr MVT(SimpleValueType SVT) : SimpleTy(SVT) {}

  bool operator>(const MVT& S)  const { return SimpleTy >  S.SimpleTy; }
  bool operator<(const MVT& S)  const { return SimpleTy <  S.SimpleTy; }
  bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
  bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
  bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
  bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }

  /// Return true if this is a valid simple valuetype.
  bool isValid() const {
    return (SimpleTy >= MVT::FIRST_VALUETYPE &&
            SimpleTy <= MVT::LAST_VALUETYPE);
  }

  /// Return true if this is a FP or a vector FP type.
  bool isFloatingPoint() const {
    return ((SimpleTy >= MVT::FIRST_FP_VALUETYPE &&
             SimpleTy <= MVT::LAST_FP_VALUETYPE) ||
            (SimpleTy >= MVT::FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE &&
             SimpleTy <= MVT::LAST_FP_FIXEDLEN_VECTOR_VALUETYPE) ||
            (SimpleTy >= MVT::FIRST_FP_SCALABLE_VECTOR_VALUETYPE &&
             SimpleTy <= MVT::LAST_FP_SCALABLE_VECTOR_VALUETYPE));
  }

  /// Return true if this is an integer or a vector integer type.
  bool isInteger() const {
    return ((SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE &&
             SimpleTy <= MVT::LAST_INTEGER_VALUETYPE) ||
            (SimpleTy >= MVT::FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE &&
             SimpleTy <= MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE) ||
            (SimpleTy >= MVT::FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE &&
             SimpleTy <= MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE));
  }

  /// Return true if this is an integer, not including vectors.
  bool isScalarInteger() const {
    return (SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE &&
            SimpleTy <= MVT::LAST_INTEGER_VALUETYPE);
  }

  /// Return true if this is a vector value type.
  bool isVector() const {
    return (SimpleTy >= MVT::FIRST_VECTOR_VALUETYPE &&
17
←
Assuming field 'SimpleTy' is >= FIRST_VECTOR_VALUETYPE→
19
←
Returning the value 1, which participates in a condition later→
            SimpleTy <= MVT::LAST_VECTOR_VALUETYPE);
18
←
Assuming field 'SimpleTy' is <= LAST_VECTOR_VALUETYPE→
  }

  /// Return true if this is a vector value type where the
  /// runtime length is machine dependent
  bool isScalableVector() const {
    return (SimpleTy >= MVT::FIRST_SCALABLE_VECTOR_VALUETYPE &&
            SimpleTy <= MVT::LAST_SCALABLE_VECTOR_VALUETYPE);
  }

  bool isFixedLengthVector() const {
    return (SimpleTy >= MVT::FIRST_FIXEDLEN_VECTOR_VALUETYPE &&
            SimpleTy <= MVT::LAST_FIXEDLEN_VECTOR_VALUETYPE);
  }

  /// Return true if this is a 16-bit vector type.
  bool is16BitVector() const {
    return (SimpleTy == MVT::v2i8  || SimpleTy == MVT::v1i16 ||
            SimpleTy == MVT::v16i1 || SimpleTy == MVT::v1f16);
  }

  /// Return true if this is a 32-bit vector type.
  bool is32BitVector() const {
    return (SimpleTy == MVT::v32i1 || SimpleTy == MVT::v4i8   ||
            SimpleTy == MVT::v2i16 || SimpleTy == MVT::v1i32  ||
            SimpleTy == MVT::v2f16 || SimpleTy == MVT::v2bf16 ||
            SimpleTy == MVT::v1f32);
  }

  /// Return true if this is a 64-bit vector type.
  bool is64BitVector() const {
    return (SimpleTy == MVT::v64i1  || SimpleTy == MVT::v8i8  ||
            SimpleTy == MVT::v4i16  || SimpleTy == MVT::v2i32 ||
            SimpleTy == MVT::v1i64  || SimpleTy == MVT::v4f16 ||
            SimpleTy == MVT::v4bf16 ||SimpleTy == MVT::v2f32  ||
            SimpleTy == MVT::v1f64);
  }

  /// Return true if this is a 128-bit vector type.
  bool is128BitVector() const {
    return (SimpleTy == MVT::v128i1 || SimpleTy == MVT::v16i8  ||
            SimpleTy == MVT::v8i16  || SimpleTy == MVT::v4i32  ||
            SimpleTy == MVT::v2i64  || SimpleTy == MVT::v1i128 ||
            SimpleTy == MVT::v8f16  || SimpleTy == MVT::v8bf16 ||
            SimpleTy == MVT::v4f32  || SimpleTy == MVT::v2f64);
  }

  /// Return true if this is a 256-bit vector type.
  bool is256BitVector() const {
    return (SimpleTy == MVT::v16f16 || SimpleTy == MVT::v16bf16 ||
            SimpleTy == MVT::v8f32  || SimpleTy == MVT::v4f64   ||
            SimpleTy == MVT::v32i8  || SimpleTy == MVT::v16i16  ||
            SimpleTy == MVT::v8i32  || SimpleTy == MVT::v4i64   ||
            SimpleTy == MVT::v256i1);
  }

  /// Return true if this is a 512-bit vector type.
  bool is512BitVector() const {
    return (SimpleTy == MVT::v32f16 || SimpleTy == MVT::v32bf16 ||
            SimpleTy == MVT::v16f32 || SimpleTy == MVT::v8f64   ||
            SimpleTy == MVT::v512i1 || SimpleTy == MVT::v64i8   ||
            SimpleTy == MVT::v32i16 || SimpleTy == MVT::v16i32  ||
            SimpleTy == MVT::v8i64);
  }

  /// Return true if this is a 1024-bit vector type.
  bool is1024BitVector() const {
    return (SimpleTy == MVT::v1024i1 || SimpleTy == MVT::v128i8 ||
            SimpleTy == MVT::v64i16  || SimpleTy == MVT::v32i32 ||
            SimpleTy == MVT::v16i64  || SimpleTy == MVT::v64f16 ||
            SimpleTy == MVT::v32f32  || SimpleTy == MVT::v16f64 ||
            SimpleTy == MVT::v64bf16);
  }

  /// Return true if this is a 2048-bit vector type.
  bool is2048BitVector() const {
    return (SimpleTy == MVT::v256i8  || SimpleTy == MVT::v128i16 ||
            SimpleTy == MVT::v64i32  || SimpleTy == MVT::v32i64  ||
            SimpleTy == MVT::v128f16 || SimpleTy == MVT::v64f32  ||
            SimpleTy == MVT::v32f64  || SimpleTy == MVT::v128bf16);
  }

  /// Return true if this is an overloaded type for TableGen.
  bool isOverloaded() const {
    return (SimpleTy == MVT::Any || SimpleTy == MVT::iAny ||
            SimpleTy == MVT::fAny || SimpleTy == MVT::vAny ||
            SimpleTy == MVT::iPTRAny);
  }

  /// Return a vector with the same number of elements as this vector, but
  /// with the element type converted to an integer type with the same
  /// bitwidth.
  MVT changeVectorElementTypeToInteger() const {
    MVT EltTy = getVectorElementType();
    MVT IntTy = MVT::getIntegerVT(EltTy.getSizeInBits());
    MVT VecTy = MVT::getVectorVT(IntTy, getVectorElementCount());
    assert(VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&((void)0)
           "Simple vector VT not representable by simple integer vector VT!")((void)0);
    return VecTy;
  }

  /// Return a VT for a vector type whose attributes match ourselves
  /// with the exception of the element type that is chosen by the caller.
  MVT changeVectorElementType(MVT EltVT) const {
    MVT VecTy = MVT::getVectorVT(EltVT, getVectorElementCount());
    assert(VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&((void)0)
           "Simple vector VT not representable by simple integer vector VT!")((void)0);
    return VecTy;
  }

  /// Return the type converted to an equivalently sized integer or vector
  /// with integer element type. Similar to changeVectorElementTypeToInteger,
  /// but also handles scalars.
  MVT changeTypeToInteger() {
    if (isVector())
      return changeVectorElementTypeToInteger();
    return MVT::getIntegerVT(getSizeInBits());
  }

  /// Return a VT for a vector type with the same element type but
  /// half the number of elements.
  MVT getHalfNumVectorElementsVT() const {
    MVT EltVT = getVectorElementType();
    auto EltCnt = getVectorElementCount();
    assert(EltCnt.isKnownEven() && "Splitting vector, but not in half!")((void)0);
    return getVectorVT(EltVT, EltCnt.divideCoefficientBy(2));
  }

  /// Returns true if the given vector is a power of 2.
  bool isPow2VectorType() const {
    unsigned NElts = getVectorMinNumElements();
    return !(NElts & (NElts - 1));
  }

  /// Widens the length of the given vector MVT up to the nearest power of 2
  /// and returns that type.
  MVT getPow2VectorType() const {
    if (isPow2VectorType())
      return *this;

    ElementCount NElts = getVectorElementCount();
    unsigned NewMinCount = 1 << Log2_32_Ceil(NElts.getKnownMinValue());
    NElts = ElementCount::get(NewMinCount, NElts.isScalable());
    return MVT::getVectorVT(getVectorElementType(), NElts);
  }

  /// If this is a vector, return the element type, otherwise return this.
  MVT getScalarType() const {
    return isVector() ? getVectorElementType() : *this;
  }

  MVT getVectorElementType() const {
    switch (SimpleTy) {
    default:
      llvm_unreachable("Not a vector MVT!")__builtin_unreachable();
    case v1i1:
    case v2i1:
    case v4i1:
    case v8i1:
    case v16i1:
    case v32i1:
    case v64i1:
    case v128i1:
    case v256i1:
    case v512i1:
    case v1024i1:
    case nxv1i1:
    case nxv2i1:
    case nxv4i1:
    case nxv8i1:
    case nxv16i1:
    case nxv32i1:
    case nxv64i1: return i1;
    case v1i8:
    case v2i8:
    case v4i8:
    case v8i8:
    case v16i8:
    case v32i8:
    case v64i8:
    case v128i8:
    case v256i8:
    case v512i8:
    case v1024i8:
    case nxv1i8:
    case nxv2i8:
    case nxv4i8:
    case nxv8i8:
    case nxv16i8:
    case nxv32i8:
    case nxv64i8: return i8;
    case v1i16:
    case v2i16:
    case v3i16:
    case v4i16:
    case v8i16:
    case v16i16:
    case v32i16:
    case v64i16:
    case v128i16:
    case v256i16:
    case v512i16:
    case nxv1i16:
    case nxv2i16:
    case nxv4i16:
    case nxv8i16:
    case nxv16i16:
    case nxv32i16: return i16;
    case v1i32:
    case v2i32:
    case v3i32:
    case v4i32:
    case v5i32:
    case v6i32:
    case v7i32:
    case v8i32:
    case v16i32:
    case v32i32:
    case v64i32:
    case v128i32:
    case v256i32:
    case v512i32:
    case v1024i32:
    case v2048i32:
    case nxv1i32:
    case nxv2i32:
    case nxv4i32:
    case nxv8i32:
    case nxv16i32:
    case nxv32i32: return i32;
    case v1i64:
    case v2i64:
    case v3i64:
    case v4i64:
    case v8i64:
    case v16i64:
    case v32i64:
    case v64i64:
    case v128i64:
    case v256i64:
    case nxv1i64:
    case nxv2i64:
    case nxv4i64:
    case nxv8i64:
    case nxv16i64:
    case nxv32i64: return i64;
    case v1i128: return i128;
    case v1f16:
    case v2f16:
    case v3f16:
    case v4f16:
    case v8f16:
    case v16f16:
    case v32f16:
    case v64f16:
    case v128f16:
    case v256f16:
    case v512f16:
    case nxv1f16:
    case nxv2f16:
    case nxv4f16:
    case nxv8f16:
    case nxv16f16:
    case nxv32f16: return f16;
    case v2bf16:
    case v3bf16:
    case v4bf16:
    case v8bf16:
    case v16bf16:
    case v32bf16:
    case v64bf16:
    case v128bf16:
    case nxv1bf16:
    case nxv2bf16:
    case nxv4bf16:
    case nxv8bf16: return bf16;
    case v1f32:
    case v2f32:
    case v3f32:
    case v4f32:
    case v5f32:
    case v6f32:
    case v7f32:
    case v8f32:
    case v16f32:
    case v32f32:
    case v64f32:
    case v128f32:
    case v256f32:
    case v512f32:
    case v1024f32:
    case v2048f32:
    case nxv1f32:
    case nxv2f32:
    case nxv4f32:
    case nxv8f32:
    case nxv16f32: return f32;
    case v1f64:
    case v2f64:
    case v3f64:
    case v4f64:
    case v8f64:
    case v16f64:
    case v32f64:
    case v64f64:
    case v128f64:
    case v256f64:
    case nxv1f64:
    case nxv2f64:
    case nxv4f64:
    case nxv8f64: return f64;
    }
  }

  /// Given a vector type, return the minimum number of elements it contains.
  unsigned getVectorMinNumElements() const {
    switch (SimpleTy) {
    default:
      llvm_unreachable("Not a vector MVT!")__builtin_unreachable();
    case v2048i32:
    case v2048f32: return 2048;
    case v1024i1:
    case v1024i8:
    case v1024i32:
    case v1024f32: return 1024;
    case v512i1:
    case v512i8:
    case v512i16:
    case v512i32:
    case v512f16:
    case v512f32: return 512;
    case v256i1:
    case v256i8:
    case v256i16:
    case v256f16:
    case v256i32:
    case v256i64:
    case v256f32:
    case v256f64: return 256;
    case v128i1:
    case v128i8:
    case v128i16:
    case v128i32:
    case v128i64:
    case v128f16:
    case v128bf16:
    case v128f32:
    case v128f64: return 128;
    case v64i1:
    case v64i8:
    case v64i16:
    case v64i32:
    case v64i64:
    case v64f16:
    case v64bf16:
    case v64f32:
    case v64f64:
    case nxv64i1:
    case nxv64i8: return 64;
    case v32i1:
    case v32i8:
    case v32i16:
    case v32i32:
    case v32i64:
    case v32f16:
    case v32bf16:
    case v32f32:
    case v32f64:
    case nxv32i1:
    case nxv32i8:
    case nxv32i16:
    case nxv32i32:
    case nxv32i64:
    case nxv32f16: return 32;
    case v16i1:
    case v16i8:
    case v16i16:
    case v16i32:
    case v16i64:
    case v16f16:
    case v16bf16:
    case v16f32:
    case v16f64:
    case nxv16i1:
    case nxv16i8:
    case nxv16i16:
    case nxv16i32:
    case nxv16i64:
    case nxv16f16:
    case nxv16f32: return 16;
    case v8i1:
    case v8i8:
    case v8i16:
    case v8i32:
    case v8i64:
    case v8f16:
    case v8bf16:
    case v8f32:
    case v8f64:
    case nxv8i1:
    case nxv8i8:
    case nxv8i16:
    case nxv8i32:
    case nxv8i64:
    case nxv8f16:
    case nxv8bf16:
    case nxv8f32:
    case nxv8f64: return 8;
    case v7i32:
    case v7f32: return 7;
    case v6i32:
    case v6f32: return 6;
    case v5i32:
    case v5f32: return 5;
    case v4i1:
    case v4i8:
    case v4i16:
    case v4i32:
    case v4i64:
    case v4f16:
    case v4bf16:
    case v4f32:
    case v4f64:
    case nxv4i1:
    case nxv4i8:
    case nxv4i16:
    case nxv4i32:
    case nxv4i64:
    case nxv4f16:
    case nxv4bf16:
    case nxv4f32:
    case nxv4f64: return 4;
    case v3i16:
    case v3i32:
    case v3i64:
    case v3f16:
    case v3bf16:
    case v3f32:
    case v3f64: return 3;
    case v2i1:
    case v2i8:
    case v2i16:
    case v2i32:
    case v2i64:
    case v2f16:
    case v2bf16:
    case v2f32:
    case v2f64:
    case nxv2i1:
    case nxv2i8:
    case nxv2i16:
    case nxv2i32:
    case nxv2i64:
    case nxv2f16:
    case nxv2bf16:
    case nxv2f32:
    case nxv2f64: return 2;
    case v1i1:
    case v1i8:
    case v1i16:
    case v1i32:
    case v1i64:
    case v1i128:
    case v1f16:
    case v1f32:
    case v1f64:
    case nxv1i1:
    case nxv1i8:
    case nxv1i16:
    case nxv1i32:
    case nxv1i64:
    case nxv1f16:
    case nxv1bf16:
    case nxv1f32:
    case nxv1f64: return 1;
    }
  }

  ElementCount getVectorElementCount() const {
    return ElementCount::get(getVectorMinNumElements(), isScalableVector());
  }

  unsigned getVectorNumElements() const {
    // TODO: Check that this isn't a scalable vector.
    return getVectorMinNumElements();
  }

  /// Returns the size of the specified MVT in bits.
  ///
  /// If the value type is a scalable vector type, the scalable property will
  /// be set and the runtime size will be a positive integer multiple of the
  /// base size.
  TypeSize getSizeInBits() const {
    switch (SimpleTy) {
    default:
      llvm_unreachable("getSizeInBits called on extended MVT.")__builtin_unreachable();
    case Other:
      llvm_unreachable("Value type is non-standard value, Other.")__builtin_unreachable();
    case iPTR:
      llvm_unreachable("Value type size is target-dependent. Ask TLI.")__builtin_unreachable();
    case iPTRAny:
    case iAny:
    case fAny:
    case vAny:
    case Any:
      llvm_unreachable("Value type is overloaded.")__builtin_unreachable();
    case token:
      llvm_unreachable("Token type is a sentinel that cannot be used "__builtin_unreachable()
                       "in codegen and has no size")__builtin_unreachable();
    case Metadata:
      llvm_unreachable("Value type is metadata.")__builtin_unreachable();
    case i1:
    case v1i1: return TypeSize::Fixed(1);
    case nxv1i1: return TypeSize::Scalable(1);
    case v2i1: return TypeSize::Fixed(2);
    case nxv2i1: return TypeSize::Scalable(2);
    case v4i1: return TypeSize::Fixed(4);
    case nxv4i1: return TypeSize::Scalable(4);
    case i8  :
    case v1i8:
    case v8i1: return TypeSize::Fixed(8);
    case nxv1i8:
    case nxv8i1: return TypeSize::Scalable(8);
    case i16 :
    case f16:
    case bf16:
    case v16i1:
    case v2i8:
    case v1i16:
    case v1f16: return TypeSize::Fixed(16);
    case nxv16i1:
    case nxv2i8:
    case nxv1i16:
    case nxv1bf16:
    case nxv1f16: return TypeSize::Scalable(16);
    case f32 :
    case i32 :
    case v32i1:
    case v4i8:
    case v2i16:
    case v2f16:
    case v2bf16:
    case v1f32:
    case v1i32: return TypeSize::Fixed(32);
    case nxv32i1:
    case nxv4i8:
    case nxv2i16:
    case nxv1i32:
    case nxv2f16:
    case nxv2bf16:
    case nxv1f32: return TypeSize::Scalable(32);
    case v3i16:
    case v3f16:
    case v3bf16: return TypeSize::Fixed(48);
    case x86mmx:
    case f64 :
    case i64 :
    case v64i1:
    case v8i8:
    case v4i16:
    case v2i32:
    case v1i64:
    case v4f16:
    case v4bf16:
    case v2f32:
    case v1f64: return TypeSize::Fixed(64);
    case nxv64i1:
    case nxv8i8:
    case nxv4i16:
    case nxv2i32:
    case nxv1i64:
    case nxv4f16:
    case nxv4bf16:
    case nxv2f32:
    case nxv1f64: return TypeSize::Scalable(64);
    case f80 :  return TypeSize::Fixed(80);
    case v3i32:
    case v3f32: return TypeSize::Fixed(96);
    case f128:
    case ppcf128:
    case i128:
    case v128i1:
    case v16i8:
    case v8i16:
    case v4i32:
    case v2i64:
    case v1i128:
    case v8f16:
    case v8bf16:
    case v4f32:
    case v2f64: return TypeSize::Fixed(128);
    case nxv16i8:
    case nxv8i16:
    case nxv4i32:
    case nxv2i64:
    case nxv8f16:
    case nxv8bf16:
    case nxv4f32:
    case nxv2f64: return TypeSize::Scalable(128);
    case v5i32:
    case v5f32: return TypeSize::Fixed(160);
    case v6i32:
    case v3i64:
    case v6f32:
    case v3f64: return TypeSize::Fixed(192);
    case v7i32:
    case v7f32: return TypeSize::Fixed(224);
    case v256i1:
    case v32i8:
    case v16i16:
    case v8i32:
    case v4i64:
    case v16f16:
    case v16bf16:
    case v8f32:
    case v4f64: return TypeSize::Fixed(256);
    case nxv32i8:
    case nxv16i16:
    case nxv8i32:
    case nxv4i64:
    case nxv16f16:
    case nxv8f32:
    case nxv4f64: return TypeSize::Scalable(256);
    case i64x8:
    case v512i1:
    case v64i8:
    case v32i16:
    case v16i32:
    case v8i64:
    case v32f16:
    case v32bf16:
    case v16f32:
    case v8f64: return TypeSize::Fixed(512);
    case nxv64i8:
    case nxv32i16:
    case nxv16i32:
    case nxv8i64:
    case nxv32f16:
    case nxv16f32:
    case nxv8f64: return TypeSize::Scalable(512);
    case v1024i1:
    case v128i8:
    case v64i16:
    case v32i32:
    case v16i64:
    case v64f16:
    case v64bf16:
    case v32f32:
    case v16f64: return TypeSize::Fixed(1024);
    case nxv32i32:
    case nxv16i64: return TypeSize::Scalable(1024);
    case v256i8:
    case v128i16:
    case v64i32:
    case v32i64:
    case v128f16:
    case v128bf16:
    case v64f32:
    case v32f64: return TypeSize::Fixed(2048);
    case nxv32i64: return TypeSize::Scalable(2048);
    case v512i8:
    case v256i16:
    case v128i32:
    case v64i64:
    case v256f16:
    case v128f32:
    case v64f64:  return TypeSize::Fixed(4096);
    case v1024i8:
    case v512i16:
    case v256i32:
    case v128i64:
    case v512f16:
    case v256f32:
    case x86amx:
    case v128f64:  return TypeSize::Fixed(8192);
    case v512i32:
    case v256i64:
    case v512f32:
    case v256f64:  return TypeSize::Fixed(16384);
    case v1024i32:
    case v1024f32:  return TypeSize::Fixed(32768);
    case v2048i32:
    case v2048f32:  return TypeSize::Fixed(65536);
    case funcref:
    case externref: return TypeSize::Fixed(0); // opaque type
    }
  }

  /// Return the size of the specified fixed width value type in bits. The
  /// function will assert if the type is scalable.
  uint64_t getFixedSizeInBits() const {
    return getSizeInBits().getFixedSize();
  }

  uint64_t getScalarSizeInBits() const {
    return getScalarType().getSizeInBits().getFixedSize();
  }

  /// Return the number of bytes overwritten by a store of the specified value
  /// type.
  ///
  /// If the value type is a scalable vector type, the scalable property will
  /// be set and the runtime size will be a positive integer multiple of the
  /// base size.
  TypeSize getStoreSize() const {
    TypeSize BaseSize = getSizeInBits();
    return {(BaseSize.getKnownMinSize() + 7) / 8, BaseSize.isScalable()};
  }

  /// Return the number of bits overwritten by a store of the specified value
  /// type.
  ///
  /// If the value type is a scalable vector type, the scalable property will
  /// be set and the runtime size will be a positive integer multiple of the
  /// base size.
  TypeSize getStoreSizeInBits() const {
    return getStoreSize() * 8;
  }

  /// Returns true if the number of bits for the type is a multiple of an
  /// 8-bit byte.
  bool isByteSized() const { return getSizeInBits().isKnownMultipleOf(8); }

  /// Return true if we know at compile time this has more bits than VT.
  bool knownBitsGT(MVT VT) const {
    return TypeSize::isKnownGT(getSizeInBits(), VT.getSizeInBits());
  }

  /// Return true if we know at compile time this has more than or the same
  /// bits as VT.
  bool knownBitsGE(MVT VT) const {
    return TypeSize::isKnownGE(getSizeInBits(), VT.getSizeInBits());
  }

  /// Return true if we know at compile time this has fewer bits than VT.
  bool knownBitsLT(MVT VT) const {
    return TypeSize::isKnownLT(getSizeInBits(), VT.getSizeInBits());
  }

  /// Return true if we know at compile time this has fewer than or the same
  /// bits as VT.
  bool knownBitsLE(MVT VT) const {
    return TypeSize::isKnownLE(getSizeInBits(), VT.getSizeInBits());
  }

  /// Return true if this has more bits than VT.
  bool bitsGT(MVT VT) const {
    assert(isScalableVector() == VT.isScalableVector() &&((void)0)
           "Comparison between scalable and fixed types")((void)0);
    return knownBitsGT(VT);
  }

  /// Return true if this has no less bits than VT.
  bool bitsGE(MVT VT) const {
    assert(isScalableVector() == VT.isScalableVector() &&((void)0)
           "Comparison between scalable and fixed types")((void)0);
    return knownBitsGE(VT);
  }

  /// Return true if this has less bits than VT.
  bool bitsLT(MVT VT) const {
    assert(isScalableVector() == VT.isScalableVector() &&((void)0)
           "Comparison between scalable and fixed types")((void)0);
    return knownBitsLT(VT);
  }

  /// Return true if this has no more bits than VT.
  bool bitsLE(MVT VT) const {
    assert(isScalableVector() == VT.isScalableVector() &&((void)0)
           "Comparison between scalable and fixed types")((void)0);
    return knownBitsLE(VT);
  }

  static MVT getFloatingPointVT(unsigned BitWidth) {
    switch (BitWidth) {
    default:
      llvm_unreachable("Bad bit width!")__builtin_unreachable();
    case 16:
      return MVT::f16;
    case 32:
      return MVT::f32;
    case 64:
      return MVT::f64;
    case 80:
      return MVT::f80;
    case 128:
      return MVT::f128;
    }
  }

  static MVT getIntegerVT(unsigned BitWidth) {
    switch (BitWidth) {
    default:
      return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);
    case 1:
      return MVT::i1;
    case 8:
      return MVT::i8;
    case 16:
      return MVT::i16;
    case 32:
      return MVT::i32;
    case 64:
      return MVT::i64;
    case 128:
      return MVT::i128;
    }
  }

  static MVT getVectorVT(MVT VT, unsigned NumElements) {
    switch (VT.SimpleTy) {
    default:
      break;
    case MVT::i1:
      if (NumElements == 1)    return MVT::v1i1;
      if (NumElements == 2)    return MVT::v2i1;
      if (NumElements == 4)    return MVT::v4i1;
      if (NumElements == 8)    return MVT::v8i1;
      if (NumElements == 16)   return MVT::v16i1;
      if (NumElements == 32)   return MVT::v32i1;
      if (NumElements == 64)   return MVT::v64i1;
      if (NumElements == 128)  return MVT::v128i1;
      if (NumElements == 256)  return MVT::v256i1;
      if (NumElements == 512)  return MVT::v512i1;
      if (NumElements == 1024) return MVT::v1024i1;
      break;
    case MVT::i8:
      if (NumElements == 1)   return MVT::v1i8;
      if (NumElements == 2)   return MVT::v2i8;
      if (NumElements == 4)   return MVT::v4i8;
      if (NumElements == 8)   return MVT::v8i8;
      if (NumElements == 16)  return MVT::v16i8;
      if (NumElements == 32)  return MVT::v32i8;
      if (NumElements == 64)  return MVT::v64i8;
      if (NumElements == 128) return MVT::v128i8;
      if (NumElements == 256) return MVT::v256i8;
      if (NumElements == 512) return MVT::v512i8;
      if (NumElements == 1024) return MVT::v1024i8;
      break;
    case MVT::i16:
      if (NumElements == 1)   return MVT::v1i16;
      if (NumElements == 2)   return MVT::v2i16;
      if (NumElements == 3)   return MVT::v3i16;
      if (NumElements == 4)   return MVT::v4i16;
      if (NumElements == 8)   return MVT::v8i16;
      if (NumElements == 16)  return MVT::v16i16;
      if (NumElements == 32)  return MVT::v32i16;
      if (NumElements == 64)  return MVT::v64i16;
      if (NumElements == 128) return MVT::v128i16;
      if (NumElements == 256) return MVT::v256i16;
      if (NumElements == 512) return MVT::v512i16;
      break;
    case MVT::i32:
      if (NumElements == 1)    return MVT::v1i32;
      if (NumElements == 2)    return MVT::v2i32;
      if (NumElements == 3)    return MVT::v3i32;
      if (NumElements == 4)    return MVT::v4i32;
      if (NumElements == 5)    return MVT::v5i32;
      if (NumElements == 6)    return MVT::v6i32;
      if (NumElements == 7)    return MVT::v7i32;
      if (NumElements == 8)    return MVT::v8i32;
      if (NumElements == 16)   return MVT::v16i32;
      if (NumElements == 32)   return MVT::v32i32;
      if (NumElements == 64)   return MVT::v64i32;
      if (NumElements == 128)  return MVT::v128i32;
      if (NumElements == 256)  return MVT::v256i32;
      if (NumElements == 512)  return MVT::v512i32;
      if (NumElements == 1024) return MVT::v1024i32;
      if (NumElements == 2048) return MVT::v2048i32;
      break;
    case MVT::i64:
      if (NumElements == 1)  return MVT::v1i64;
      if (NumElements == 2)  return MVT::v2i64;
      if (NumElements == 3)  return MVT::v3i64;
      if (NumElements == 4)  return MVT::v4i64;
      if (NumElements == 8)  return MVT::v8i64;
      if (NumElements == 16) return MVT::v16i64;
      if (NumElements == 32) return MVT::v32i64;
      if (NumElements == 64) return MVT::v64i64;
      if (NumElements == 128) return MVT::v128i64;
      if (NumElements == 256) return MVT::v256i64;
      break;
    case MVT::i128:
      if (NumElements == 1)  return MVT::v1i128;
      break;
    case MVT::f16:
      if (NumElements == 1)   return MVT::v1f16;
      if (NumElements == 2)   return MVT::v2f16;
      if (NumElements == 3)   return MVT::v3f16;
      if (NumElements == 4)   return MVT::v4f16;
      if (NumElements == 8)   return MVT::v8f16;
      if (NumElements == 16)  return MVT::v16f16;
      if (NumElements == 32)  return MVT::v32f16;
      if (NumElements == 64)  return MVT::v64f16;
      if (NumElements == 128) return MVT::v128f16;
      if (NumElements == 256) return MVT::v256f16;
      if (NumElements == 512) return MVT::v512f16;
      break;
    case MVT::bf16:
      if (NumElements == 2)   return MVT::v2bf16;
      if (NumElements == 3)   return MVT::v3bf16;
      if (NumElements == 4)   return MVT::v4bf16;
      if (NumElements == 8)   return MVT::v8bf16;
      if (NumElements == 16)  return MVT::v16bf16;
      if (NumElements == 32)  return MVT::v32bf16;
      if (NumElements == 64)  return MVT::v64bf16;
      if (NumElements == 128) return MVT::v128bf16;
      break;
    case MVT::f32:
      if (NumElements == 1)    return MVT::v1f32;
      if (NumElements == 2)    return MVT::v2f32;
      if (NumElements == 3)    return MVT::v3f32;
      if (NumElements == 4)    return MVT::v4f32;
      if (NumElements == 5)    return MVT::v5f32;
      if (NumElements == 6)    return MVT::v6f32;
      if (NumElements == 7)    return MVT::v7f32;
      if (NumElements == 8)    return MVT::v8f32;
      if (NumElements == 16)   return MVT::v16f32;
      if (NumElements == 32)   return MVT::v32f32;
      if (NumElements == 64)   return MVT::v64f32;
      if (NumElements == 128)  return MVT::v128f32;
      if (NumElements == 256)  return MVT::v256f32;
      if (NumElements == 512)  return MVT::v512f32;
      if (NumElements == 1024) return MVT::v1024f32;
      if (NumElements == 2048) return MVT::v2048f32;
      break;
    case MVT::f64:
      if (NumElements == 1)  return MVT::v1f64;
      if (NumElements == 2)  return MVT::v2f64;
      if (NumElements == 3)  return MVT::v3f64;
      if (NumElements == 4)  return MVT::v4f64;
      if (NumElements == 8)  return MVT::v8f64;
      if (NumElements == 16) return MVT::v16f64;
      if (NumElements == 32) return MVT::v32f64;
      if (NumElements == 64) return MVT::v64f64;
      if (NumElements == 128) return MVT::v128f64;
      if (NumElements == 256) return MVT::v256f64;
      break;
    }
    return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);
  }

  static MVT getScalableVectorVT(MVT VT, unsigned NumElements) {
    switch(VT.SimpleTy) {
      default:
        break;
      case MVT::i1:
        if (NumElements == 1)  return MVT::nxv1i1;
        if (NumElements == 2)  return MVT::nxv2i1;
        if (NumElements == 4)  return MVT::nxv4i1;
        if (NumElements == 8)  return MVT::nxv8i1;
        if (NumElements == 16) return MVT::nxv16i1;
        if (NumElements == 32) return MVT::nxv32i1;
        if (NumElements == 64) return MVT::nxv64i1;
        break;
      case MVT::i8:
        if (NumElements == 1)  return MVT::nxv1i8;
        if (NumElements == 2)  return MVT::nxv2i8;
        if (NumElements == 4)  return MVT::nxv4i8;
        if (NumElements == 8)  return MVT::nxv8i8;
        if (NumElements == 16) return MVT::nxv16i8;
        if (NumElements == 32) return MVT::nxv32i8;
        if (NumElements == 64) return MVT::nxv64i8;
        break;
      case MVT::i16:
        if (NumElements == 1)  return MVT::nxv1i16;
        if (NumElements == 2)  return MVT::nxv2i16;
        if (NumElements == 4)  return MVT::nxv4i16;
        if (NumElements == 8)  return MVT::nxv8i16;
        if (NumElements == 16) return MVT::nxv16i16;
        if (NumElements == 32) return MVT::nxv32i16;
        break;
      case MVT::i32:
        if (NumElements == 1)  return MVT::nxv1i32;
        if (NumElements == 2)  return MVT::nxv2i32;
        if (NumElements == 4)  return MVT::nxv4i32;
        if (NumElements == 8)  return MVT::nxv8i32;
        if (NumElements == 16) return MVT::nxv16i32;
        if (NumElements == 32) return MVT::nxv32i32;
        break;
      case MVT::i64:
        if (NumElements == 1)  return MVT::nxv1i64;
        if (NumElements == 2)  return MVT::nxv2i64;
        if (NumElements == 4)  return MVT::nxv4i64;
        if (NumElements == 8)  return MVT::nxv8i64;
        if (NumElements == 16) return MVT::nxv16i64;
        if (NumElements == 32) return MVT::nxv32i64;
        break;
      case MVT::f16:
        if (NumElements == 1)  return MVT::nxv1f16;
        if (NumElements == 2)  return MVT::nxv2f16;
        if (NumElements == 4)  return MVT::nxv4f16;
        if (NumElements == 8)  return MVT::nxv8f16;
        if (NumElements == 16)  return MVT::nxv16f16;
        if (NumElements == 32)  return MVT::nxv32f16;
        break;
      case MVT::bf16:
        if (NumElements == 1)  return MVT::nxv1bf16;
        if (NumElements == 2)  return MVT::nxv2bf16;
        if (NumElements == 4)  return MVT::nxv4bf16;
        if (NumElements == 8)  return MVT::nxv8bf16;
        break;
      case MVT::f32:
        if (NumElements == 1)  return MVT::nxv1f32;
        if (NumElements == 2)  return MVT::nxv2f32;
        if (NumElements == 4)  return MVT::nxv4f32;
        if (NumElements == 8)  return MVT::nxv8f32;
        if (NumElements == 16) return MVT::nxv16f32;
        break;
      case MVT::f64:
        if (NumElements == 1)  return MVT::nxv1f64;
        if (NumElements == 2)  return MVT::nxv2f64;
        if (NumElements == 4)  return MVT::nxv4f64;
        if (NumElements == 8)  return MVT::nxv8f64;
        break;
    }
    return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);
  }

  static MVT getVectorVT(MVT VT, unsigned NumElements, bool IsScalable) {
    if (IsScalable)
      return getScalableVectorVT(VT, NumElements);
    return getVectorVT(VT, NumElements);
  }

  static MVT getVectorVT(MVT VT, ElementCount EC) {
    if (EC.isScalable())
      return getScalableVectorVT(VT, EC.getKnownMinValue());
    return getVectorVT(VT, EC.getKnownMinValue());
  }

  /// Return the value type corresponding to the specified type.  This returns
  /// all pointers as iPTR.  If HandleUnknown is true, unknown types are
  /// returned as Other, otherwise they are invalid.
  static MVT getVT(Type *Ty, bool HandleUnknown = false);

public:
  /// SimpleValueType Iteration
  /// @{
  static auto all_valuetypes() {
    return seq_inclusive(MVT::FIRST_VALUETYPE, MVT::LAST_VALUETYPE);
  }

  static auto integer_valuetypes() {
    return seq_inclusive(MVT::FIRST_INTEGER_VALUETYPE,
                         MVT::LAST_INTEGER_VALUETYPE);
  }

  static auto fp_valuetypes() {
    return seq_inclusive(MVT::FIRST_FP_VALUETYPE, MVT::LAST_FP_VALUETYPE);
  }

  static auto vector_valuetypes() {
    return seq_inclusive(MVT::FIRST_VECTOR_VALUETYPE,
                         MVT::LAST_VECTOR_VALUETYPE);
  }

  static auto fixedlen_vector_valuetypes() {
    return seq_inclusive(MVT::FIRST_FIXEDLEN_VECTOR_VALUETYPE,
                         MVT::LAST_FIXEDLEN_VECTOR_VALUETYPE);
  }

  static auto scalable_vector_valuetypes() {
    return seq_inclusive(MVT::FIRST_SCALABLE_VECTOR_VALUETYPE,
                         MVT::LAST_SCALABLE_VECTOR_VALUETYPE);
  }

  static auto integer_fixedlen_vector_valuetypes() {
    return seq_inclusive(MVT::FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE,
                         MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE);
  }

  static auto fp_fixedlen_vector_valuetypes() {
    return seq_inclusive(MVT::FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE,
                         MVT::LAST_FP_FIXEDLEN_VECTOR_VALUETYPE);
  }

  static auto integer_scalable_vector_valuetypes() {
    return seq_inclusive(MVT::FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE,
                         MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE);
  }

  static auto fp_scalable_vector_valuetypes() {
    return seq_inclusive(MVT::FIRST_FP_SCALABLE_VECTOR_VALUETYPE,
                         MVT::LAST_FP_SCALABLE_VECTOR_VALUETYPE);
  }
  /// @}
};

1457} // end namespace llvm

1459#endif // LLVM_SUPPORT_MACHINEVALUETYPE_H