Bug Summary

File:src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/CodeGen/MachineInstr.cpp
Warning:line 200, column 3
Null pointer passed as 2nd argument to memory copy function

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name MachineInstr.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model pic -pic-level 1 -fhalf-no-semantic-interposition -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/gnu/usr.bin/clang/libLLVM/obj -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Analysis -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ASMParser -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/BinaryFormat -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Bitcode -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Bitcode -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Bitstream -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /include/llvm/CodeGen -I /include/llvm/CodeGen/PBQP -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/IR -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/IR -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/Coroutines -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ProfileData/Coverage -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/CodeView -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/DWARF -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/MSF -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/PDB -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Demangle -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ExecutionEngine -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ExecutionEngine/JITLink -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ExecutionEngine/Orc -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Frontend -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Frontend/OpenACC -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Frontend -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Frontend/OpenMP -I /include/llvm/CodeGen/GlobalISel -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/IRReader -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/InstCombine -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/Transforms/InstCombine -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/LTO -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Linker -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/MC -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/MC/MCParser -I /include/llvm/CodeGen/MIRParser -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Object -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Option -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Passes -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ProfileData -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/Scalar -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ADT -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Support -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/Symbolize -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Target -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/Utils -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/Vectorize -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/IPO -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include -I /usr/src/gnu/usr.bin/clang/libLLVM/../include -I /usr/src/gnu/usr.bin/clang/libLLVM/obj -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include -D NDEBUG -D __STDC_LIMIT_MACROS -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D LLVM_PREFIX="/usr" -D PIC -internal-isystem /usr/include/c++/v1 -internal-isystem /usr/local/lib/clang/13.0.0/include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/usr/src/gnu/usr.bin/clang/libLLVM/obj -ferror-limit 19 -fvisibility-inlines-hidden -fwrapv -D_RET_PROTECTOR -ret-protector -fno-rtti -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /home/ben/Projects/vmm/scan-build/2022-01-12-194120-40624-1 -x c++ /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/CodeGen/MachineInstr.cpp

/usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/CodeGen/MachineInstr.cpp

→
1//===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Methods common to all machine instructions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/CodeGen/MachineInstr.h"
14#include "llvm/ADT/APFloat.h"
15#include "llvm/ADT/ArrayRef.h"
16#include "llvm/ADT/FoldingSet.h"
17#include "llvm/ADT/Hashing.h"
18#include "llvm/ADT/None.h"
19#include "llvm/ADT/STLExtras.h"
20#include "llvm/ADT/SmallBitVector.h"
21#include "llvm/ADT/SmallString.h"
22#include "llvm/ADT/SmallVector.h"
23#include "llvm/Analysis/AliasAnalysis.h"
24#include "llvm/Analysis/Loads.h"
25#include "llvm/Analysis/MemoryLocation.h"
26#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
27#include "llvm/CodeGen/MachineBasicBlock.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineInstrBundle.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/MachineModuleInfo.h"
34#include "llvm/CodeGen/MachineOperand.h"
35#include "llvm/CodeGen/MachineRegisterInfo.h"
36#include "llvm/CodeGen/PseudoSourceValue.h"
37#include "llvm/CodeGen/StackMaps.h"
38#include "llvm/CodeGen/TargetInstrInfo.h"
39#include "llvm/CodeGen/TargetRegisterInfo.h"
40#include "llvm/CodeGen/TargetSubtargetInfo.h"
41#include "llvm/Config/llvm-config.h"
42#include "llvm/IR/Constants.h"
43#include "llvm/IR/DebugInfoMetadata.h"
44#include "llvm/IR/DebugLoc.h"
45#include "llvm/IR/DerivedTypes.h"
46#include "llvm/IR/Function.h"
47#include "llvm/IR/InlineAsm.h"
48#include "llvm/IR/InstrTypes.h"
49#include "llvm/IR/Intrinsics.h"
50#include "llvm/IR/LLVMContext.h"
51#include "llvm/IR/Metadata.h"
52#include "llvm/IR/Module.h"
53#include "llvm/IR/ModuleSlotTracker.h"
54#include "llvm/IR/Operator.h"
55#include "llvm/IR/Type.h"
56#include "llvm/IR/Value.h"
57#include "llvm/MC/MCInstrDesc.h"
58#include "llvm/MC/MCRegisterInfo.h"
59#include "llvm/MC/MCSymbol.h"
60#include "llvm/Support/Casting.h"
61#include "llvm/Support/CommandLine.h"
62#include "llvm/Support/Compiler.h"
63#include "llvm/Support/Debug.h"
64#include "llvm/Support/ErrorHandling.h"
65#include "llvm/Support/FormattedStream.h"
66#include "llvm/Support/LowLevelTypeImpl.h"
67#include "llvm/Support/MathExtras.h"
68#include "llvm/Support/raw_ostream.h"
69#include "llvm/Target/TargetIntrinsicInfo.h"
70#include "llvm/Target/TargetMachine.h"
71#include <algorithm>
72#include <cassert>
73#include <cstddef>
74#include <cstdint>
75#include <cstring>
76#include <iterator>
77#include <utility>
78
79using namespace llvm;
80
81static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) {
82 if (const MachineBasicBlock *MBB = MI.getParent())
83 if (const MachineFunction *MF = MBB->getParent())
84 return MF;
85 return nullptr;
86}
87
88// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
89// it.
90static void tryToGetTargetInfo(const MachineInstr &MI,
91 const TargetRegisterInfo *&TRI,
92 const MachineRegisterInfo *&MRI,
93 const TargetIntrinsicInfo *&IntrinsicInfo,
94 const TargetInstrInfo *&TII) {
95
96 if (const MachineFunction *MF = getMFIfAvailable(MI)) {
97 TRI = MF->getSubtarget().getRegisterInfo();
98 MRI = &MF->getRegInfo();
99 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
100 TII = MF->getSubtarget().getInstrInfo();
101 }
102}
103
104void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
105 if (MCID->ImplicitDefs)
106 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
107 ++ImpDefs)
108 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
109 if (MCID->ImplicitUses)
110 for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
111 ++ImpUses)
112 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
113}
114
115/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
116/// implicit operands. It reserves space for the number of operands specified by
117/// the MCInstrDesc.
118MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
119 DebugLoc dl, bool NoImp)
120 : MCID(&tid), debugLoc(std::move(dl)), DebugInstrNum(0) {
121 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((void)0);
122
123 // Reserve space for the expected number of operands.
124 if (unsigned NumOps = MCID->getNumOperands() +
125 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
126 CapOperands = OperandCapacity::get(NumOps);
127 Operands = MF.allocateOperandArray(CapOperands);
128 }
129
130 if (!NoImp)
131 addImplicitDefUseOperands(MF);
132}
133
134/// MachineInstr ctor - Copies MachineInstr arg exactly.
135/// Does not copy the number from debug instruction numbering, to preserve
136/// uniqueness.
137MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
138 : MCID(&MI.getDesc()), Info(MI.Info), debugLoc(MI.getDebugLoc()),
139 DebugInstrNum(0) {
140 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((void)0);
141
142 CapOperands = OperandCapacity::get(MI.getNumOperands());
143 Operands = MF.allocateOperandArray(CapOperands);
144
145 // Copy operands.
146 for (const MachineOperand &MO : MI.operands())
147 addOperand(MF, MO);
148
149 // Copy all the sensible flags.
150 setFlags(MI.Flags);
151}
152
153void MachineInstr::moveBefore(MachineInstr *MovePos) {
154 MovePos->getParent()->splice(MovePos, getParent(), getIterator());
155}
156
157/// getRegInfo - If this instruction is embedded into a MachineFunction,
158/// return the MachineRegisterInfo object for the current function, otherwise
159/// return null.
160MachineRegisterInfo *MachineInstr::getRegInfo() {
161 if (MachineBasicBlock *MBB = getParent())
10
←
Assuming 'MBB' is null
→
11
←
Taking false branch
→
162 return &MBB->getParent()->getRegInfo();
163 return nullptr;
12
←
Returning null pointer, which participates in a condition later
→
164}
165
166/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
167/// this instruction from their respective use lists. This requires that the
168/// operands already be on their use lists.
169void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
170 for (MachineOperand &MO : operands())
171 if (MO.isReg())
172 MRI.removeRegOperandFromUseList(&MO);
173}
174
175/// AddRegOperandsToUseLists - Add all of the register operands in
176/// this instruction from their respective use lists. This requires that the
177/// operands not be on their use lists yet.
178void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
179 for (MachineOperand &MO : operands())
180 if (MO.isReg())
181 MRI.addRegOperandToUseList(&MO);
182}
183
184void MachineInstr::addOperand(const MachineOperand &Op) {
185 MachineBasicBlock *MBB = getParent();
186 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs")((void)0);
187 MachineFunction *MF = MBB->getParent();
188 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs")((void)0);
189 addOperand(*MF, Op);
190}
191
192/// Move NumOps MachineOperands from Src to Dst, with support for overlapping
193/// ranges. If MRI is non-null also update use-def chains.
194static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
195 unsigned NumOps, MachineRegisterInfo *MRI) {
196 if (MRI
21.1
'MRI' is null
21.1
'MRI' is null
)
22
←
Taking false branch
→
197 return MRI->moveOperands(Dst, Src, NumOps);
198 // MachineOperand is a trivially copyable type so we can just use memmove.
199 assert(Dst && Src && "Unknown operands")((void)0);
200 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
23
←
Null pointer passed as 2nd argument to memory copy function
201}
202
203/// addOperand - Add the specified operand to the instruction. If it is an
204/// implicit operand, it is added to the end of the operand list. If it is
205/// an explicit operand it is added at the end of the explicit operand list
206/// (before the first implicit operand).
207void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
208 assert(MCID && "Cannot add operands before providing an instr descriptor")((void)0);
209
210 // Check if we're adding one of our existing operands.
211 if (&Op >= Operands && &Op < Operands + NumOperands) {
7
←
Assuming the condition is false
→
212 // This is unusual: MI->addOperand(MI->getOperand(i)).
213 // If adding Op requires reallocating or moving existing operands around,
214 // the Op reference could go stale. Support it by copying Op.
215 MachineOperand CopyOp(Op);
216 return addOperand(MF, CopyOp);
217 }
218
219 // Find the insert location for the new operand. Implicit registers go at
220 // the end, everything else goes before the implicit regs.
221 //
222 // FIXME: Allow mixed explicit and implicit operands on inline asm.
223 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
224 // implicit-defs, but they must not be moved around. See the FIXME in
225 // InstrEmitter.cpp.
226 unsigned OpNo = getNumOperands();
227 bool isImpReg = Op.isReg() && Op.isImplicit();
228 if (!isImpReg
7.1
'isImpReg' is false
7.1
'isImpReg' is false
 && !isInlineAsm()) {
8
←
Taking false branch
→
229 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
230 --OpNo;
231 assert(!Operands[OpNo].isTied() && "Cannot move tied operands")((void)0);
232 }
233 }
234
235#ifndef NDEBUG1
236 bool isDebugOp = Op.getType() == MachineOperand::MO_Metadata ||
237 Op.getType() == MachineOperand::MO_MCSymbol;
238 // OpNo now points as the desired insertion point. Unless this is a variadic
239 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
240 // RegMask operands go between the explicit and implicit operands.
241 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||((void)0)
242 OpNo < MCID->getNumOperands() || isDebugOp) &&((void)0)
243 "Trying to add an operand to a machine instr that is already done!")((void)0);
244#endif
245
246 MachineRegisterInfo *MRI = getRegInfo();
9
←
Calling 'MachineInstr::getRegInfo'
→
13
←
Returning from 'MachineInstr::getRegInfo'
→
247
248 // Determine if the Operands array needs to be reallocated.
249 // Save the old capacity and operand array.
250 OperandCapacity OldCap = CapOperands;
251 MachineOperand *OldOperands = Operands;
14
←
'OldOperands' initialized here
→
252 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
15
←
Assuming pointer value is null
→
16
←
Assuming 'OldOperands' is null
→
253 CapOperands = OldOperands
16.1
'OldOperands' is null
16.1
'OldOperands' is null
 ? OldCap.getNext() : OldCap.get(1);
17
←
'?' condition is false
→
254 Operands = MF.allocateOperandArray(CapOperands);
255 // Move the operands before the insertion point.
256 if (OpNo)
18
←
Assuming 'OpNo' is not equal to 0
→
19
←
Taking true branch
→
257 moveOperands(Operands, OldOperands, OpNo, MRI);
20
←
Passing null pointer value via 2nd parameter 'Src'
→
21
←
Calling 'moveOperands'
→
258 }
259
260 // Move the operands following the insertion point.
261 if (OpNo != NumOperands)
262 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
263 MRI);
264 ++NumOperands;
265
266 // Deallocate the old operand array.
267 if (OldOperands != Operands && OldOperands)
268 MF.deallocateOperandArray(OldCap, OldOperands);
269
270 // Copy Op into place. It still needs to be inserted into the MRI use lists.
271 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
272 NewMO->ParentMI = this;
273
274 // When adding a register operand, tell MRI about it.
275 if (NewMO->isReg()) {
276 // Ensure isOnRegUseList() returns false, regardless of Op's status.
277 NewMO->Contents.Reg.Prev = nullptr;
278 // Ignore existing ties. This is not a property that can be copied.
279 NewMO->TiedTo = 0;
280 // Add the new operand to MRI, but only for instructions in an MBB.
281 if (MRI)
282 MRI->addRegOperandToUseList(NewMO);
283 // The MCID operand information isn't accurate until we start adding
284 // explicit operands. The implicit operands are added first, then the
285 // explicits are inserted before them.
286 if (!isImpReg) {
287 // Tie uses to defs as indicated in MCInstrDesc.
288 if (NewMO->isUse()) {
289 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
290 if (DefIdx != -1)
291 tieOperands(DefIdx, OpNo);
292 }
293 // If the register operand is flagged as early, mark the operand as such.
294 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
295 NewMO->setIsEarlyClobber(true);
296 }
297 }
298}
299
300/// RemoveOperand - Erase an operand from an instruction, leaving it with one
301/// fewer operand than it started with.
302///
303void MachineInstr::RemoveOperand(unsigned OpNo) {
304 assert(OpNo < getNumOperands() && "Invalid operand number")((void)0);
305 untieRegOperand(OpNo);
306
307#ifndef NDEBUG1
308 // Moving tied operands would break the ties.
309 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
310 if (Operands[i].isReg())
311 assert(!Operands[i].isTied() && "Cannot move tied operands")((void)0);
312#endif
313
314 MachineRegisterInfo *MRI = getRegInfo();
315 if (MRI && Operands[OpNo].isReg())
316 MRI->removeRegOperandFromUseList(Operands + OpNo);
317
318 // Don't call the MachineOperand destructor. A lot of this code depends on
319 // MachineOperand having a trivial destructor anyway, and adding a call here
320 // wouldn't make it 'destructor-correct'.
321
322 if (unsigned N = NumOperands - 1 - OpNo)
323 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
324 --NumOperands;
325}
326
327void MachineInstr::setExtraInfo(MachineFunction &MF,
328 ArrayRef<MachineMemOperand *> MMOs,
329 MCSymbol *PreInstrSymbol,
330 MCSymbol *PostInstrSymbol,
331 MDNode *HeapAllocMarker) {
332 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
333 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
334 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
335 int NumPointers =
336 MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol + HasHeapAllocMarker;
337
338 // Drop all extra info if there is none.
339 if (NumPointers <= 0) {
340 Info.clear();
341 return;
342 }
343
344 // If more than one pointer, then store out of line. Store heap alloc markers
345 // out of line because PointerSumType cannot hold more than 4 tag types with
346 // 32-bit pointers.
347 // FIXME: Maybe we should make the symbols in the extra info mutable?
348 else if (NumPointers > 1 || HasHeapAllocMarker) {
349 Info.set<EIIK_OutOfLine>(MF.createMIExtraInfo(
350 MMOs, PreInstrSymbol, PostInstrSymbol, HeapAllocMarker));
351 return;
352 }
353
354 // Otherwise store the single pointer inline.
355 if (HasPreInstrSymbol)
356 Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
357 else if (HasPostInstrSymbol)
358 Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
359 else
360 Info.set<EIIK_MMO>(MMOs[0]);
361}
362
363void MachineInstr::dropMemRefs(MachineFunction &MF) {
364 if (memoperands_empty())
365 return;
366
367 setExtraInfo(MF, {}, getPreInstrSymbol(), getPostInstrSymbol(),
368 getHeapAllocMarker());
369}
370
371void MachineInstr::setMemRefs(MachineFunction &MF,
372 ArrayRef<MachineMemOperand *> MMOs) {
373 if (MMOs.empty()) {
374 dropMemRefs(MF);
375 return;
376 }
377
378 setExtraInfo(MF, MMOs, getPreInstrSymbol(), getPostInstrSymbol(),
379 getHeapAllocMarker());
380}
381
382void MachineInstr::addMemOperand(MachineFunction &MF,
383 MachineMemOperand *MO) {
384 SmallVector<MachineMemOperand *, 2> MMOs;
385 MMOs.append(memoperands_begin(), memoperands_end());
386 MMOs.push_back(MO);
387 setMemRefs(MF, MMOs);
388}
389
390void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) {
391 if (this == &MI)
392 // Nothing to do for a self-clone!
393 return;
394
395 assert(&MF == MI.getMF() &&((void)0)
396 "Invalid machine functions when cloning memory refrences!")((void)0);
397 // See if we can just steal the extra info already allocated for the
398 // instruction. We can do this whenever the pre- and post-instruction symbols
399 // are the same (including null).
400 if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
401 getPostInstrSymbol() == MI.getPostInstrSymbol() &&
402 getHeapAllocMarker() == MI.getHeapAllocMarker()) {
403 Info = MI.Info;
404 return;
405 }
406
407 // Otherwise, fall back on a copy-based clone.
408 setMemRefs(MF, MI.memoperands());
409}
410
411/// Check to see if the MMOs pointed to by the two MemRefs arrays are
412/// identical.
413static bool hasIdenticalMMOs(ArrayRef<MachineMemOperand *> LHS,
414 ArrayRef<MachineMemOperand *> RHS) {
415 if (LHS.size() != RHS.size())
416 return false;
417
418 auto LHSPointees = make_pointee_range(LHS);
419 auto RHSPointees = make_pointee_range(RHS);
420 return std::equal(LHSPointees.begin(), LHSPointees.end(),
421 RHSPointees.begin());
422}
423
424void MachineInstr::cloneMergedMemRefs(MachineFunction &MF,
425 ArrayRef<const MachineInstr *> MIs) {
426 // Try handling easy numbers of MIs with simpler mechanisms.
427 if (MIs.empty()) {
428 dropMemRefs(MF);
429 return;
430 }
431 if (MIs.size() == 1) {
432 cloneMemRefs(MF, *MIs[0]);
433 return;
434 }
435 // Because an empty memoperands list provides *no* information and must be
436 // handled conservatively (assuming the instruction can do anything), the only
437 // way to merge with it is to drop all other memoperands.
438 if (MIs[0]->memoperands_empty()) {
439 dropMemRefs(MF);
440 return;
441 }
442
443 // Handle the general case.
444 SmallVector<MachineMemOperand *, 2> MergedMMOs;
445 // Start with the first instruction.
446 assert(&MF == MIs[0]->getMF() &&((void)0)
447 "Invalid machine functions when cloning memory references!")((void)0);
448 MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
449 // Now walk all the other instructions and accumulate any different MMOs.
450 for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
451 assert(&MF == MI.getMF() &&((void)0)
452 "Invalid machine functions when cloning memory references!")((void)0);
453
454 // Skip MIs with identical operands to the first. This is a somewhat
455 // arbitrary hack but will catch common cases without being quadratic.
456 // TODO: We could fully implement merge semantics here if needed.
457 if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
458 continue;
459
460 // Because an empty memoperands list provides *no* information and must be
461 // handled conservatively (assuming the instruction can do anything), the
462 // only way to merge with it is to drop all other memoperands.
463 if (MI.memoperands_empty()) {
464 dropMemRefs(MF);
465 return;
466 }
467
468 // Otherwise accumulate these into our temporary buffer of the merged state.
469 MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
470 }
471
472 setMemRefs(MF, MergedMMOs);
473}
474
475void MachineInstr::setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
476 // Do nothing if old and new symbols are the same.
477 if (Symbol == getPreInstrSymbol())
478 return;
479
480 // If there was only one symbol and we're removing it, just clear info.
481 if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
482 Info.clear();
483 return;
484 }
485
486 setExtraInfo(MF, memoperands(), Symbol, getPostInstrSymbol(),
487 getHeapAllocMarker());
488}
489
490void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
491 // Do nothing if old and new symbols are the same.
492 if (Symbol == getPostInstrSymbol())
493 return;
494
495 // If there was only one symbol and we're removing it, just clear info.
496 if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
497 Info.clear();
498 return;
499 }
500
501 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), Symbol,
502 getHeapAllocMarker());
503}
504
505void MachineInstr::setHeapAllocMarker(MachineFunction &MF, MDNode *Marker) {
506 // Do nothing if old and new symbols are the same.
507 if (Marker == getHeapAllocMarker())
508 return;
509
510 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
511 Marker);
512}
513
514void MachineInstr::cloneInstrSymbols(MachineFunction &MF,
515 const MachineInstr &MI) {
516 if (this == &MI)
517 // Nothing to do for a self-clone!
518 return;
519
520 assert(&MF == MI.getMF() &&((void)0)
521 "Invalid machine functions when cloning instruction symbols!")((void)0);
522
523 setPreInstrSymbol(MF, MI.getPreInstrSymbol());
524 setPostInstrSymbol(MF, MI.getPostInstrSymbol());
525 setHeapAllocMarker(MF, MI.getHeapAllocMarker());
526}
527
528uint16_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
529 // For now, the just return the union of the flags. If the flags get more
530 // complicated over time, we might need more logic here.
531 return getFlags() | Other.getFlags();
532}
533
534uint16_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) {
535 uint16_t MIFlags = 0;
536 // Copy the wrapping flags.
537 if (const OverflowingBinaryOperator *OB =
538 dyn_cast<OverflowingBinaryOperator>(&I)) {
539 if (OB->hasNoSignedWrap())
540 MIFlags |= MachineInstr::MIFlag::NoSWrap;
541 if (OB->hasNoUnsignedWrap())
542 MIFlags |= MachineInstr::MIFlag::NoUWrap;
543 }
544
545 // Copy the exact flag.
546 if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
547 if (PE->isExact())
548 MIFlags |= MachineInstr::MIFlag::IsExact;
549
550 // Copy the fast-math flags.
551 if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
552 const FastMathFlags Flags = FP->getFastMathFlags();
553 if (Flags.noNaNs())
554 MIFlags |= MachineInstr::MIFlag::FmNoNans;
555 if (Flags.noInfs())
556 MIFlags |= MachineInstr::MIFlag::FmNoInfs;
557 if (Flags.noSignedZeros())
558 MIFlags |= MachineInstr::MIFlag::FmNsz;
559 if (Flags.allowReciprocal())
560 MIFlags |= MachineInstr::MIFlag::FmArcp;
561 if (Flags.allowContract())
562 MIFlags |= MachineInstr::MIFlag::FmContract;
563 if (Flags.approxFunc())
564 MIFlags |= MachineInstr::MIFlag::FmAfn;
565 if (Flags.allowReassoc())
566 MIFlags |= MachineInstr::MIFlag::FmReassoc;
567 }
568
569 return MIFlags;
570}
571
572void MachineInstr::copyIRFlags(const Instruction &I) {
573 Flags = copyFlagsFromInstruction(I);
574}
575
576bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
577 assert(!isBundledWithPred() && "Must be called on bundle header")((void)0);
578 for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
579 if (MII->getDesc().getFlags() & Mask) {
580 if (Type == AnyInBundle)
581 return true;
582 } else {
583 if (Type == AllInBundle && !MII->isBundle())
584 return false;
585 }
586 // This was the last instruction in the bundle.
587 if (!MII->isBundledWithSucc())
588 return Type == AllInBundle;
589 }
590}
591
592bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
593 MICheckType Check) const {
594 // If opcodes or number of operands are not the same then the two
595 // instructions are obviously not identical.
596 if (Other.getOpcode() != getOpcode() ||
597 Other.getNumOperands() != getNumOperands())
598 return false;
599
600 if (isBundle()) {
601 // We have passed the test above that both instructions have the same
602 // opcode, so we know that both instructions are bundles here. Let's compare
603 // MIs inside the bundle.
604 assert(Other.isBundle() && "Expected that both instructions are bundles.")((void)0);
605 MachineBasicBlock::const_instr_iterator I1 = getIterator();
606 MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
607 // Loop until we analysed the last intruction inside at least one of the
608 // bundles.
609 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
610 ++I1;
611 ++I2;
612 if (!I1->isIdenticalTo(*I2, Check))
613 return false;
614 }
615 // If we've reached the end of just one of the two bundles, but not both,
616 // the instructions are not identical.
617 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
618 return false;
619 }
620
621 // Check operands to make sure they match.
622 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
623 const MachineOperand &MO = getOperand(i);
624 const MachineOperand &OMO = Other.getOperand(i);
625 if (!MO.isReg()) {
626 if (!MO.isIdenticalTo(OMO))
627 return false;
628 continue;
629 }
630
631 // Clients may or may not want to ignore defs when testing for equality.
632 // For example, machine CSE pass only cares about finding common
633 // subexpressions, so it's safe to ignore virtual register defs.
634 if (MO.isDef()) {
635 if (Check == IgnoreDefs)
636 continue;
637 else if (Check == IgnoreVRegDefs) {
638 if (!Register::isVirtualRegister(MO.getReg()) ||
639 !Register::isVirtualRegister(OMO.getReg()))
640 if (!MO.isIdenticalTo(OMO))
641 return false;
642 } else {
643 if (!MO.isIdenticalTo(OMO))
644 return false;
645 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
646 return false;
647 }
648 } else {
649 if (!MO.isIdenticalTo(OMO))
650 return false;
651 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
652 return false;
653 }
654 }
655 // If DebugLoc does not match then two debug instructions are not identical.
656 if (isDebugInstr())
657 if (getDebugLoc() && Other.getDebugLoc() &&
658 getDebugLoc() != Other.getDebugLoc())
659 return false;
660 return true;
661}
662
663const MachineFunction *MachineInstr::getMF() const {
664 return getParent()->getParent();
665}
666
667MachineInstr *MachineInstr::removeFromParent() {
668 assert(getParent() && "Not embedded in a basic block!")((void)0);
669 return getParent()->remove(this);
670}
671
672MachineInstr *MachineInstr::removeFromBundle() {
673 assert(getParent() && "Not embedded in a basic block!")((void)0);
674 return getParent()->remove_instr(this);
675}
676
677void MachineInstr::eraseFromParent() {
678 assert(getParent() && "Not embedded in a basic block!")((void)0);
679 getParent()->erase(this);
680}
681
682void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
683 assert(getParent() && "Not embedded in a basic block!")((void)0);
684 MachineBasicBlock *MBB = getParent();
685 MachineFunction *MF = MBB->getParent();
686 assert(MF && "Not embedded in a function!")((void)0);
687
688 MachineInstr *MI = (MachineInstr *)this;
689 MachineRegisterInfo &MRI = MF->getRegInfo();
690
691 for (const MachineOperand &MO : MI->operands()) {
692 if (!MO.isReg() || !MO.isDef())
693 continue;
694 Register Reg = MO.getReg();
695 if (!Reg.isVirtual())
696 continue;
697 MRI.markUsesInDebugValueAsUndef(Reg);
698 }
699 MI->eraseFromParent();
700}
701
702void MachineInstr::eraseFromBundle() {
703 assert(getParent() && "Not embedded in a basic block!")((void)0);
704 getParent()->erase_instr(this);
705}
706
707bool MachineInstr::isCandidateForCallSiteEntry(QueryType Type) const {
708 if (!isCall(Type))
709 return false;
710 switch (getOpcode()) {
711 case TargetOpcode::PATCHPOINT:
712 case TargetOpcode::STACKMAP:
713 case TargetOpcode::STATEPOINT:
714 case TargetOpcode::FENTRY_CALL:
715 return false;
716 }
717 return true;
718}
719
720bool MachineInstr::shouldUpdateCallSiteInfo() const {
721 if (isBundle())
722 return isCandidateForCallSiteEntry(MachineInstr::AnyInBundle);
723 return isCandidateForCallSiteEntry();
724}
725
726unsigned MachineInstr::getNumExplicitOperands() const {
727 unsigned NumOperands = MCID->getNumOperands();
728 if (!MCID->isVariadic())
729 return NumOperands;
730
731 for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
732 const MachineOperand &MO = getOperand(I);
733 // The operands must always be in the following order:
734 // - explicit reg defs,
735 // - other explicit operands (reg uses, immediates, etc.),
736 // - implicit reg defs
737 // - implicit reg uses
738 if (MO.isReg() && MO.isImplicit())
739 break;
740 ++NumOperands;
741 }
742 return NumOperands;
743}
744
745unsigned MachineInstr::getNumExplicitDefs() const {
746 unsigned NumDefs = MCID->getNumDefs();
747 if (!MCID->isVariadic())
748 return NumDefs;
749
750 for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
751 const MachineOperand &MO = getOperand(I);
752 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
753 break;
754 ++NumDefs;
755 }
756 return NumDefs;
757}
758
759void MachineInstr::bundleWithPred() {
760 assert(!isBundledWithPred() && "MI is already bundled with its predecessor")((void)0);
761 setFlag(BundledPred);
762 MachineBasicBlock::instr_iterator Pred = getIterator();
763 --Pred;
764 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags")((void)0);
765 Pred->setFlag(BundledSucc);
766}
767
768void MachineInstr::bundleWithSucc() {
769 assert(!isBundledWithSucc() && "MI is already bundled with its successor")((void)0);
770 setFlag(BundledSucc);
771 MachineBasicBlock::instr_iterator Succ = getIterator();
772 ++Succ;
773 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags")((void)0);
774 Succ->setFlag(BundledPred);
775}
776
777void MachineInstr::unbundleFromPred() {
778 assert(isBundledWithPred() && "MI isn't bundled with its predecessor")((void)0);
779 clearFlag(BundledPred);
780 MachineBasicBlock::instr_iterator Pred = getIterator();
781 --Pred;
782 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags")((void)0);
783 Pred->clearFlag(BundledSucc);
784}
785
786void MachineInstr::unbundleFromSucc() {
787 assert(isBundledWithSucc() && "MI isn't bundled with its successor")((void)0);
788 clearFlag(BundledSucc);
789 MachineBasicBlock::instr_iterator Succ = getIterator();
790 ++Succ;
791 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags")((void)0);
792 Succ->clearFlag(BundledPred);
793}
794
795bool MachineInstr::isStackAligningInlineAsm() const {
796 if (isInlineAsm()) {
797 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
798 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
799 return true;
800 }
801 return false;
802}
803
804InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
805 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!")((void)0);
806 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
807 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
808}
809
810int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
811 unsigned *GroupNo) const {
812 assert(isInlineAsm() && "Expected an inline asm instruction")((void)0);
813 assert(OpIdx < getNumOperands() && "OpIdx out of range")((void)0);
814
815 // Ignore queries about the initial operands.
816 if (OpIdx < InlineAsm::MIOp_FirstOperand)
817 return -1;
818
819 unsigned Group = 0;
820 unsigned NumOps;
821 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
822 i += NumOps) {
823 const MachineOperand &FlagMO = getOperand(i);
824 // If we reach the implicit register operands, stop looking.
825 if (!FlagMO.isImm())
826 return -1;
827 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
828 if (i + NumOps > OpIdx) {
829 if (GroupNo)
830 *GroupNo = Group;
831 return i;
832 }
833 ++Group;
834 }
835 return -1;
836}
837
838const DILabel *MachineInstr::getDebugLabel() const {
839 assert(isDebugLabel() && "not a DBG_LABEL")((void)0);
840 return cast<DILabel>(getOperand(0).getMetadata());
841}
842
843const MachineOperand &MachineInstr::getDebugVariableOp() const {
844 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*")((void)0);
845 unsigned VariableOp = isDebugValueList() ? 0 : 2;
846 return getOperand(VariableOp);
847}
848
849MachineOperand &MachineInstr::getDebugVariableOp() {
850 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*")((void)0);
851 unsigned VariableOp = isDebugValueList() ? 0 : 2;
852 return getOperand(VariableOp);
853}
854
855const DILocalVariable *MachineInstr::getDebugVariable() const {
856 return cast<DILocalVariable>(getDebugVariableOp().getMetadata());
857}
858
859const MachineOperand &MachineInstr::getDebugExpressionOp() const {
860 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*")((void)0);
861 unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
862 return getOperand(ExpressionOp);
863}
864
865MachineOperand &MachineInstr::getDebugExpressionOp() {
866 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*")((void)0);
867 unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
868 return getOperand(ExpressionOp);
869}
870
871const DIExpression *MachineInstr::getDebugExpression() const {
872 return cast<DIExpression>(getDebugExpressionOp().getMetadata());
873}
874
875bool MachineInstr::isDebugEntryValue() const {
876 return isDebugValue() && getDebugExpression()->isEntryValue();
877}
878
879const TargetRegisterClass*
880MachineInstr::getRegClassConstraint(unsigned OpIdx,
881 const TargetInstrInfo *TII,
882 const TargetRegisterInfo *TRI) const {
883 assert(getParent() && "Can't have an MBB reference here!")((void)0);
884 assert(getMF() && "Can't have an MF reference here!")((void)0);
885 const MachineFunction &MF = *getMF();
886
887 // Most opcodes have fixed constraints in their MCInstrDesc.
888 if (!isInlineAsm())
889 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
890
891 if (!getOperand(OpIdx).isReg())
892 return nullptr;
893
894 // For tied uses on inline asm, get the constraint from the def.
895 unsigned DefIdx;
896 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
897 OpIdx = DefIdx;
898
899 // Inline asm stores register class constraints in the flag word.
900 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
901 if (FlagIdx < 0)
902 return nullptr;
903
904 unsigned Flag = getOperand(FlagIdx).getImm();
905 unsigned RCID;
906 if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
907 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
908 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
909 InlineAsm::hasRegClassConstraint(Flag, RCID))
910 return TRI->getRegClass(RCID);
911
912 // Assume that all registers in a memory operand are pointers.
913 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
914 return TRI->getPointerRegClass(MF);
915
916 return nullptr;
917}
918
919const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
920 Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
921 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
922 // Check every operands inside the bundle if we have
923 // been asked to.
924 if (ExploreBundle)
925 for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
926 ++OpndIt)
927 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
928 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
929 else
930 // Otherwise, just check the current operands.
931 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
932 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
933 return CurRC;
934}
935
936const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
937 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
938 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
939 assert(CurRC && "Invalid initial register class")((void)0);
940 // Check if Reg is constrained by some of its use/def from MI.
941 const MachineOperand &MO = getOperand(OpIdx);
942 if (!MO.isReg() || MO.getReg() != Reg)
943 return CurRC;
944 // If yes, accumulate the constraints through the operand.
945 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
946}
947
948const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
949 unsigned OpIdx, const TargetRegisterClass *CurRC,
950 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
951 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
952 const MachineOperand &MO = getOperand(OpIdx);
953 assert(MO.isReg() &&((void)0)
954 "Cannot get register constraints for non-register operand")((void)0);
955 assert(CurRC && "Invalid initial register class")((void)0);
956 if (unsigned SubIdx = MO.getSubReg()) {
957 if (OpRC)
958 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
959 else
960 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
961 } else if (OpRC)
962 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
963 return CurRC;
964}
965
966/// Return the number of instructions inside the MI bundle, not counting the
967/// header instruction.
968unsigned MachineInstr::getBundleSize() const {
969 MachineBasicBlock::const_instr_iterator I = getIterator();
970 unsigned Size = 0;
971 while (I->isBundledWithSucc()) {
972 ++Size;
973 ++I;
974 }
975 return Size;
976}
977
978/// Returns true if the MachineInstr has an implicit-use operand of exactly
979/// the given register (not considering sub/super-registers).
980bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const {
981 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
982 const MachineOperand &MO = getOperand(i);
983 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
984 return true;
985 }
986 return false;
987}
988
989/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
990/// the specific register or -1 if it is not found. It further tightens
991/// the search criteria to a use that kills the register if isKill is true.
992int MachineInstr::findRegisterUseOperandIdx(
993 Register Reg, bool isKill, const TargetRegisterInfo *TRI) const {
994 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
995 const MachineOperand &MO = getOperand(i);
996 if (!MO.isReg() || !MO.isUse())
997 continue;
998 Register MOReg = MO.getReg();
999 if (!MOReg)
1000 continue;
1001 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
1002 if (!isKill || MO.isKill())
1003 return i;
1004 }
1005 return -1;
1006}
1007
1008/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1009/// indicating if this instruction reads or writes Reg. This also considers
1010/// partial defines.
1011std::pair<bool,bool>
1012MachineInstr::readsWritesVirtualRegister(Register Reg,
1013 SmallVectorImpl<unsigned> *Ops) const {
1014 bool PartDef = false; // Partial redefine.
1015 bool FullDef = false; // Full define.
1016 bool Use = false;
1017
1018 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1019 const MachineOperand &MO = getOperand(i);
1020 if (!MO.isReg() || MO.getReg() != Reg)
1021 continue;
1022 if (Ops)
1023 Ops->push_back(i);
1024 if (MO.isUse())
1025 Use |= !MO.isUndef();
1026 else if (MO.getSubReg() && !MO.isUndef())
1027 // A partial def undef doesn't count as reading the register.
1028 PartDef = true;
1029 else
1030 FullDef = true;
1031 }
1032 // A partial redefine uses Reg unless there is also a full define.
1033 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1034}
1035
1036/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1037/// the specified register or -1 if it is not found. If isDead is true, defs
1038/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1039/// also checks if there is a def of a super-register.
1040int
1041MachineInstr::findRegisterDefOperandIdx(Register Reg, bool isDead, bool Overlap,
1042 const TargetRegisterInfo *TRI) const {
1043 bool isPhys = Register::isPhysicalRegister(Reg);
1044 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1045 const MachineOperand &MO = getOperand(i);
1046 // Accept regmask operands when Overlap is set.
1047 // Ignore them when looking for a specific def operand (Overlap == false).
1048 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1049 return i;
1050 if (!MO.isReg() || !MO.isDef())
1051 continue;
1052 Register MOReg = MO.getReg();
1053 bool Found = (MOReg == Reg);
1054 if (!Found && TRI && isPhys && Register::isPhysicalRegister(MOReg)) {
1055 if (Overlap)
1056 Found = TRI->regsOverlap(MOReg, Reg);
1057 else
1058 Found = TRI->isSubRegister(MOReg, Reg);
1059 }
1060 if (Found && (!isDead || MO.isDead()))
1061 return i;
1062 }
1063 return -1;
1064}
1065
1066/// findFirstPredOperandIdx() - Find the index of the first operand in the
1067/// operand list that is used to represent the predicate. It returns -1 if
1068/// none is found.
1069int MachineInstr::findFirstPredOperandIdx() const {
1070 // Don't call MCID.findFirstPredOperandIdx() because this variant
1071 // is sometimes called on an instruction that's not yet complete, and
1072 // so the number of operands is less than the MCID indicates. In
1073 // particular, the PTX target does this.
1074 const MCInstrDesc &MCID = getDesc();
1075 if (MCID.isPredicable()) {
1076 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1077 if (MCID.OpInfo[i].isPredicate())
1078 return i;
1079 }
1080
1081 return -1;
1082}
1083
1084// MachineOperand::TiedTo is 4 bits wide.
1085const unsigned TiedMax = 15;
1086
1087/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1088///
1089/// Use and def operands can be tied together, indicated by a non-zero TiedTo
1090/// field. TiedTo can have these values:
1091///
1092/// 0: Operand is not tied to anything.
1093/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1094/// TiedMax: Tied to an operand >= TiedMax-1.
1095///
1096/// The tied def must be one of the first TiedMax operands on a normal
1097/// instruction. INLINEASM instructions allow more tied defs.
1098///
1099void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1100 MachineOperand &DefMO = getOperand(DefIdx);
1101 MachineOperand &UseMO = getOperand(UseIdx);
1102 assert(DefMO.isDef() && "DefIdx must be a def operand")((void)0);
1103 assert(UseMO.isUse() && "UseIdx must be a use operand")((void)0);
1104 assert(!DefMO.isTied() && "Def is already tied to another use")((void)0);
1105 assert(!UseMO.isTied() && "Use is already tied to another def")((void)0);
1106
1107 if (DefIdx < TiedMax)
1108 UseMO.TiedTo = DefIdx + 1;
1109 else {
1110 // Inline asm can use the group descriptors to find tied operands,
1111 // statepoint tied operands are trivial to match (1-1 reg def with reg use),
1112 // but on normal instruction, the tied def must be within the first TiedMax
1113 // operands.
1114 assert((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) &&((void)0)
1115 "DefIdx out of range")((void)0);
1116 UseMO.TiedTo = TiedMax;
1117 }
1118
1119 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1120 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1121}
1122
1123/// Given the index of a tied register operand, find the operand it is tied to.
1124/// Defs are tied to uses and vice versa. Returns the index of the tied operand
1125/// which must exist.
1126unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1127 const MachineOperand &MO = getOperand(OpIdx);
1128 assert(MO.isTied() && "Operand isn't tied")((void)0);
1129
1130 // Normally TiedTo is in range.
1131 if (MO.TiedTo < TiedMax)
1132 return MO.TiedTo - 1;
1133
1134 // Uses on normal instructions can be out of range.
1135 if (!isInlineAsm() && getOpcode() != TargetOpcode::STATEPOINT) {
1136 // Normal tied defs must be in the 0..TiedMax-1 range.
1137 if (MO.isUse())
1138 return TiedMax - 1;
1139 // MO is a def. Search for the tied use.
1140 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1141 const MachineOperand &UseMO = getOperand(i);
1142 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1143 return i;
1144 }
1145 llvm_unreachable("Can't find tied use")__builtin_unreachable();
1146 }
1147
1148 if (getOpcode() == TargetOpcode::STATEPOINT) {
1149 // In STATEPOINT defs correspond 1-1 to GC pointer operands passed
1150 // on registers.
1151 StatepointOpers SO(this);
1152 unsigned CurUseIdx = SO.getFirstGCPtrIdx();
1153 assert(CurUseIdx != -1U && "only gc pointer statepoint operands can be tied")((void)0);
1154 unsigned NumDefs = getNumDefs();
1155 for (unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {
1156 while (!getOperand(CurUseIdx).isReg())
1157 CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1158 if (OpIdx == CurDefIdx)
1159 return CurUseIdx;
1160 if (OpIdx == CurUseIdx)
1161 return CurDefIdx;
1162 CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1163 }
1164 llvm_unreachable("Can't find tied use")__builtin_unreachable();
1165 }
1166
1167 // Now deal with inline asm by parsing the operand group descriptor flags.
1168 // Find the beginning of each operand group.
1169 SmallVector<unsigned, 8> GroupIdx;
1170 unsigned OpIdxGroup = ~0u;
1171 unsigned NumOps;
1172 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1173 i += NumOps) {
1174 const MachineOperand &FlagMO = getOperand(i);
1175 assert(FlagMO.isImm() && "Invalid tied operand on inline asm")((void)0);
1176 unsigned CurGroup = GroupIdx.size();
1177 GroupIdx.push_back(i);
1178 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1179 // OpIdx belongs to this operand group.
1180 if (OpIdx > i && OpIdx < i + NumOps)
1181 OpIdxGroup = CurGroup;
1182 unsigned TiedGroup;
1183 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1184 continue;
1185 // Operands in this group are tied to operands in TiedGroup which must be
1186 // earlier. Find the number of operands between the two groups.
1187 unsigned Delta = i - GroupIdx[TiedGroup];
1188
1189 // OpIdx is a use tied to TiedGroup.
1190 if (OpIdxGroup == CurGroup)
1191 return OpIdx - Delta;
1192
1193 // OpIdx is a def tied to this use group.
1194 if (OpIdxGroup == TiedGroup)
1195 return OpIdx + Delta;
1196 }
1197 llvm_unreachable("Invalid tied operand on inline asm")__builtin_unreachable();
1198}
1199
1200/// clearKillInfo - Clears kill flags on all operands.
1201///
1202void MachineInstr::clearKillInfo() {
1203 for (MachineOperand &MO : operands()) {
1204 if (MO.isReg() && MO.isUse())
1205 MO.setIsKill(false);
1206 }
1207}
1208
1209void MachineInstr::substituteRegister(Register FromReg, Register ToReg,
1210 unsigned SubIdx,
1211 const TargetRegisterInfo &RegInfo) {
1212 if (Register::isPhysicalRegister(ToReg)) {
1213 if (SubIdx)
1214 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1215 for (MachineOperand &MO : operands()) {
1216 if (!MO.isReg() || MO.getReg() != FromReg)
1217 continue;
1218 MO.substPhysReg(ToReg, RegInfo);
1219 }
1220 } else {
1221 for (MachineOperand &MO : operands()) {
1222 if (!MO.isReg() || MO.getReg() != FromReg)
1223 continue;
1224 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1225 }
1226 }
1227}
1228
1229/// isSafeToMove - Return true if it is safe to move this instruction. If
1230/// SawStore is set to true, it means that there is a store (or call) between
1231/// the instruction's location and its intended destination.
1232bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const {
1233 // Ignore stuff that we obviously can't move.
1234 //
1235 // Treat volatile loads as stores. This is not strictly necessary for
1236 // volatiles, but it is required for atomic loads. It is not allowed to move
1237 // a load across an atomic load with Ordering > Monotonic.
1238 if (mayStore() || isCall() || isPHI() ||
1239 (mayLoad() && hasOrderedMemoryRef())) {
1240 SawStore = true;
1241 return false;
1242 }
1243
1244 if (isPosition() || isDebugInstr() || isTerminator() ||
1245 mayRaiseFPException() || hasUnmodeledSideEffects())
1246 return false;
1247
1248 // See if this instruction does a load. If so, we have to guarantee that the
1249 // loaded value doesn't change between the load and the its intended
1250 // destination. The check for isInvariantLoad gives the target the chance to
1251 // classify the load as always returning a constant, e.g. a constant pool
1252 // load.
1253 if (mayLoad() && !isDereferenceableInvariantLoad(AA))
1254 // Otherwise, this is a real load. If there is a store between the load and
1255 // end of block, we can't move it.
1256 return !SawStore;
1257
1258 return true;
1259}
1260
1261static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA,
1262 bool UseTBAA, const MachineMemOperand *MMOa,
1263 const MachineMemOperand *MMOb) {
1264 // The following interface to AA is fashioned after DAGCombiner::isAlias and
1265 // operates with MachineMemOperand offset with some important assumptions:
1266 // - LLVM fundamentally assumes flat address spaces.
1267 // - MachineOperand offset can *only* result from legalization and cannot
1268 // affect queries other than the trivial case of overlap checking.
1269 // - These offsets never wrap and never step outside of allocated objects.
1270 // - There should never be any negative offsets here.
1271 //
1272 // FIXME: Modify API to hide this math from "user"
1273 // Even before we go to AA we can reason locally about some memory objects. It
1274 // can save compile time, and possibly catch some corner cases not currently
1275 // covered.
1276
1277 int64_t OffsetA = MMOa->getOffset();
1278 int64_t OffsetB = MMOb->getOffset();
1279 int64_t MinOffset = std::min(OffsetA, OffsetB);
1280
1281 uint64_t WidthA = MMOa->getSize();
1282 uint64_t WidthB = MMOb->getSize();
1283 bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
1284 bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
1285
1286 const Value *ValA = MMOa->getValue();
1287 const Value *ValB = MMOb->getValue();
1288 bool SameVal = (ValA && ValB && (ValA == ValB));
1289 if (!SameVal) {
1290 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1291 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1292 if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1293 return false;
1294 if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1295 return false;
1296 if (PSVa && PSVb && (PSVa == PSVb))
1297 SameVal = true;
1298 }
1299
1300 if (SameVal) {
1301 if (!KnownWidthA || !KnownWidthB)
1302 return true;
1303 int64_t MaxOffset = std::max(OffsetA, OffsetB);
1304 int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1305 return (MinOffset + LowWidth > MaxOffset);
1306 }
1307
1308 if (!AA)
1309 return true;
1310
1311 if (!ValA || !ValB)
1312 return true;
1313
1314 assert((OffsetA >= 0) && "Negative MachineMemOperand offset")((void)0);
1315 assert((OffsetB >= 0) && "Negative MachineMemOperand offset")((void)0);
1316
1317 int64_t OverlapA =
1318 KnownWidthA ? WidthA + OffsetA - MinOffset : MemoryLocation::UnknownSize;
1319 int64_t OverlapB =
1320 KnownWidthB ? WidthB + OffsetB - MinOffset : MemoryLocation::UnknownSize;
1321
1322 return !AA->isNoAlias(
1323 MemoryLocation(ValA, OverlapA, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1324 MemoryLocation(ValB, OverlapB,
1325 UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1326}
1327
1328bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other,
1329 bool UseTBAA) const {
1330 const MachineFunction *MF = getMF();
1331 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1332 const MachineFrameInfo &MFI = MF->getFrameInfo();
1333
1334 // Exclude call instruction which may alter the memory but can not be handled
1335 // by this function.
1336 if (isCall() || Other.isCall())
1337 return true;
1338
1339 // If neither instruction stores to memory, they can't alias in any
1340 // meaningful way, even if they read from the same address.
1341 if (!mayStore() && !Other.mayStore())
1342 return false;
1343
1344 // Both instructions must be memory operations to be able to alias.
1345 if (!mayLoadOrStore() || !Other.mayLoadOrStore())
1346 return false;
1347
1348 // Let the target decide if memory accesses cannot possibly overlap.
1349 if (TII->areMemAccessesTriviallyDisjoint(*this, Other))
1350 return false;
1351
1352 // Memory operations without memory operands may access anything. Be
1353 // conservative and assume `MayAlias`.
1354 if (memoperands_empty() || Other.memoperands_empty())
1355 return true;
1356
1357 // Skip if there are too many memory operands.
1358 auto NumChecks = getNumMemOperands() * Other.getNumMemOperands();
1359 if (NumChecks > TII->getMemOperandAACheckLimit())
1360 return true;
1361
1362 // Check each pair of memory operands from both instructions, which can't
1363 // alias only if all pairs won't alias.
1364 for (auto *MMOa : memoperands())
1365 for (auto *MMOb : Other.memoperands())
1366 if (MemOperandsHaveAlias(MFI, AA, UseTBAA, MMOa, MMOb))
1367 return true;
1368
1369 return false;
1370}
1371
1372/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1373/// or volatile memory reference, or if the information describing the memory
1374/// reference is not available. Return false if it is known to have no ordered
1375/// memory references.
1376bool MachineInstr::hasOrderedMemoryRef() const {
1377 // An instruction known never to access memory won't have a volatile access.
1378 if (!mayStore() &&
1379 !mayLoad() &&
1380 !isCall() &&
1381 !hasUnmodeledSideEffects())
1382 return false;
1383
1384 // Otherwise, if the instruction has no memory reference information,
1385 // conservatively assume it wasn't preserved.
1386 if (memoperands_empty())
1387 return true;
1388
1389 // Check if any of our memory operands are ordered.
1390 return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1391 return !MMO->isUnordered();
1392 });
1393}
1394
1395/// isDereferenceableInvariantLoad - Return true if this instruction will never
1396/// trap and is loading from a location whose value is invariant across a run of
1397/// this function.
1398bool MachineInstr::isDereferenceableInvariantLoad(AAResults *AA) const {
1399 // If the instruction doesn't load at all, it isn't an invariant load.
1400 if (!mayLoad())
1401 return false;
1402
1403 // If the instruction has lost its memoperands, conservatively assume that
1404 // it may not be an invariant load.
1405 if (memoperands_empty())
1406 return false;
1407
1408 const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1409
1410 for (MachineMemOperand *MMO : memoperands()) {
1411 if (!MMO->isUnordered())
1412 // If the memory operand has ordering side effects, we can't move the
1413 // instruction. Such an instruction is technically an invariant load,
1414 // but the caller code would need updated to expect that.
1415 return false;
1416 if (MMO->isStore()) return false;
1417 if (MMO->isInvariant() && MMO->isDereferenceable())
1418 continue;
1419
1420 // A load from a constant PseudoSourceValue is invariant.
1421 if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1422 if (PSV->isConstant(&MFI))
1423 continue;
1424
1425 if (const Value *V = MMO->getValue()) {
1426 // If we have an AliasAnalysis, ask it whether the memory is constant.
1427 if (AA &&
1428 AA->pointsToConstantMemory(
1429 MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1430 continue;
1431 }
1432
1433 // Otherwise assume conservatively.
1434 return false;
1435 }
1436
1437 // Everything checks out.
1438 return true;
1439}
1440
1441/// isConstantValuePHI - If the specified instruction is a PHI that always
1442/// merges together the same virtual register, return the register, otherwise
1443/// return 0.
1444unsigned MachineInstr::isConstantValuePHI() const {
1445 if (!isPHI())
1446 return 0;
1447 assert(getNumOperands() >= 3 &&((void)0)
1448 "It's illegal to have a PHI without source operands")((void)0);
1449
1450 Register Reg = getOperand(1).getReg();
1451 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1452 if (getOperand(i).getReg() != Reg)
1453 return 0;
1454 return Reg;
1455}
1456
1457bool MachineInstr::hasUnmodeledSideEffects() const {
1458 if (hasProperty(MCID::UnmodeledSideEffects))
1459 return true;
1460 if (isInlineAsm()) {
1461 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1462 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1463 return true;
1464 }
1465
1466 return false;
1467}
1468
1469bool MachineInstr::isLoadFoldBarrier() const {
1470 return mayStore() || isCall() ||
1471 (hasUnmodeledSideEffects() && !isPseudoProbe());
1472}
1473
1474/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1475///
1476bool MachineInstr::allDefsAreDead() const {
1477 for (const MachineOperand &MO : operands()) {
1478 if (!MO.isReg() || MO.isUse())
1479 continue;
1480 if (!MO.isDead())
1481 return false;
1482 }
1483 return true;
1484}
1485
1486/// copyImplicitOps - Copy implicit register operands from specified
1487/// instruction to this instruction.
1488void MachineInstr::copyImplicitOps(MachineFunction &MF,
1489 const MachineInstr &MI) {
1490 for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
1491 i != e; ++i) {
1492 const MachineOperand &MO = MI.getOperand(i);
1493 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1494 addOperand(MF, MO);
1495 }
1496}
1497
1498bool MachineInstr::hasComplexRegisterTies() const {
1499 const MCInstrDesc &MCID = getDesc();
1500 if (MCID.Opcode == TargetOpcode::STATEPOINT)
1501 return true;
1502 for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1503 const auto &Operand = getOperand(I);
1504 if (!Operand.isReg() || Operand.isDef())
1505 // Ignore the defined registers as MCID marks only the uses as tied.
1506 continue;
1507 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1508 int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1509 if (ExpectedTiedIdx != TiedIdx)
1510 return true;
1511 }
1512 return false;
1513}
1514
1515LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1516 const MachineRegisterInfo &MRI) const {
1517 const MachineOperand &Op = getOperand(OpIdx);
1518 if (!Op.isReg())
1519 return LLT{};
1520
1521 if (isVariadic() || OpIdx >= getNumExplicitOperands())
1522 return MRI.getType(Op.getReg());
1523
1524 auto &OpInfo = getDesc().OpInfo[OpIdx];
1525 if (!OpInfo.isGenericType())
1526 return MRI.getType(Op.getReg());
1527
1528 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1529 return LLT{};
1530
1531 LLT TypeToPrint = MRI.getType(Op.getReg());
1532 // Don't mark the type index printed if it wasn't actually printed: maybe
1533 // another operand with the same type index has an actual type attached:
1534 if (TypeToPrint.isValid())
1535 PrintedTypes.set(OpInfo.getGenericTypeIndex());
1536 return TypeToPrint;
1537}
1538
1539#if !defined(NDEBUG1) || defined(LLVM_ENABLE_DUMP)
1540LLVM_DUMP_METHOD__attribute__((noinline)) void MachineInstr::dump() const {
1541 dbgs() << " ";
1542 print(dbgs());
1543}
1544
1545LLVM_DUMP_METHOD__attribute__((noinline)) void MachineInstr::dumprImpl(
1546 const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
1547 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const {
1548 if (Depth >= MaxDepth)
1549 return;
1550 if (!AlreadySeenInstrs.insert(this).second)
1551 return;
1552 // PadToColumn always inserts at least one space.
1553 // Don't mess up the alignment if we don't want any space.
1554 if (Depth)
1555 fdbgs().PadToColumn(Depth * 2);
1556 print(fdbgs());
1557 for (const MachineOperand &MO : operands()) {
1558 if (!MO.isReg() || MO.isDef())
1559 continue;
1560 Register Reg = MO.getReg();
1561 if (Reg.isPhysical())
1562 continue;
1563 const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg);
1564 if (NewMI == nullptr)
1565 continue;
1566 NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs);
1567 }
1568}
1569
1570LLVM_DUMP_METHOD__attribute__((noinline)) void MachineInstr::dumpr(const MachineRegisterInfo &MRI,
1571 unsigned MaxDepth) const {
1572 SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs;
1573 dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs);
1574}
1575#endif
1576
1577void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1578 bool SkipDebugLoc, bool AddNewLine,
1579 const TargetInstrInfo *TII) const {
1580 const Module *M = nullptr;
1581 const Function *F = nullptr;
1582 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1583 F = &MF->getFunction();
1584 M = F->getParent();
1585 if (!TII)
1586 TII = MF->getSubtarget().getInstrInfo();
1587 }
1588
1589 ModuleSlotTracker MST(M);
1590 if (F)
1591 MST.incorporateFunction(*F);
1592 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);
1593}
1594
1595void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
1596 bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1597 bool AddNewLine, const TargetInstrInfo *TII) const {
1598 // We can be a bit tidier if we know the MachineFunction.
1599 const TargetRegisterInfo *TRI = nullptr;
1600 const MachineRegisterInfo *MRI = nullptr;
1601 const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1602 tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1603
1604 if (isCFIInstruction())
1605 assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction")((void)0);
1606
1607 SmallBitVector PrintedTypes(8);
1608 bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1609 auto getTiedOperandIdx = [&](unsigned OpIdx) {
1610 if (!ShouldPrintRegisterTies)
1611 return 0U;
1612 const MachineOperand &MO = getOperand(OpIdx);
1613 if (MO.isReg() && MO.isTied() && !MO.isDef())
1614 return findTiedOperandIdx(OpIdx);
1615 return 0U;
1616 };
1617 unsigned StartOp = 0;
1618 unsigned e = getNumOperands();
1619
1620 // Print explicitly defined operands on the left of an assignment syntax.
1621 while (StartOp < e) {
1622 const MachineOperand &MO = getOperand(StartOp);
1623 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1624 break;
1625
1626 if (StartOp != 0)
1627 OS << ", ";
1628
1629 LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1630 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1631 MO.print(OS, MST, TypeToPrint, StartOp, /*PrintDef=*/false, IsStandalone,
1632 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1633 ++StartOp;
1634 }
1635
1636 if (StartOp != 0)
1637 OS << " = ";
1638
1639 if (getFlag(MachineInstr::FrameSetup))
1640 OS << "frame-setup ";
1641 if (getFlag(MachineInstr::FrameDestroy))
1642 OS << "frame-destroy ";
1643 if (getFlag(MachineInstr::FmNoNans))
1644 OS << "nnan ";
1645 if (getFlag(MachineInstr::FmNoInfs))
1646 OS << "ninf ";
1647 if (getFlag(MachineInstr::FmNsz))
1648 OS << "nsz ";
1649 if (getFlag(MachineInstr::FmArcp))
1650 OS << "arcp ";
1651 if (getFlag(MachineInstr::FmContract))
1652 OS << "contract ";
1653 if (getFlag(MachineInstr::FmAfn))
1654 OS << "afn ";
1655 if (getFlag(MachineInstr::FmReassoc))
1656 OS << "reassoc ";
1657 if (getFlag(MachineInstr::NoUWrap))
1658 OS << "nuw ";
1659 if (getFlag(MachineInstr::NoSWrap))
1660 OS << "nsw ";
1661 if (getFlag(MachineInstr::IsExact))
1662 OS << "exact ";
1663 if (getFlag(MachineInstr::NoFPExcept))
1664 OS << "nofpexcept ";
1665 if (getFlag(MachineInstr::NoMerge))
1666 OS << "nomerge ";
1667
1668 // Print the opcode name.
1669 if (TII)
1670 OS << TII->getName(getOpcode());
1671 else
1672 OS << "UNKNOWN";
1673
1674 if (SkipOpers)
1675 return;
1676
1677 // Print the rest of the operands.
1678 bool FirstOp = true;
1679 unsigned AsmDescOp = ~0u;
1680 unsigned AsmOpCount = 0;
1681
1682 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1683 // Print asm string.
1684 OS << " ";
1685 const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1686 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1687 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1688 getOperand(OpIdx).print(OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true, IsStandalone,
1689 ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1690 IntrinsicInfo);
1691
1692 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1693 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1694 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1695 OS << " [sideeffect]";
1696 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1697 OS << " [mayload]";
1698 if (ExtraInfo & InlineAsm::Extra_MayStore)
1699 OS << " [maystore]";
1700 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1701 OS << " [isconvergent]";
1702 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1703 OS << " [alignstack]";
1704 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1705 OS << " [attdialect]";
1706 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1707 OS << " [inteldialect]";
1708
1709 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1710 FirstOp = false;
1711 }
1712
1713 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1714 const MachineOperand &MO = getOperand(i);
1715
1716 if (FirstOp) FirstOp = false; else OS << ",";
1717 OS << " ";
1718
1719 if (isDebugValue() && MO.isMetadata()) {
1720 // Pretty print DBG_VALUE* instructions.
1721 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1722 if (DIV && !DIV->getName().empty())
1723 OS << "!\"" << DIV->getName() << '\"';
1724 else {
1725 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1726 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1727 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1728 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1729 }
1730 } else if (isDebugLabel() && MO.isMetadata()) {
1731 // Pretty print DBG_LABEL instructions.
1732 auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1733 if (DIL && !DIL->getName().empty())
1734 OS << "\"" << DIL->getName() << '\"';
1735 else {
1736 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1737 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1738 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1739 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1740 }
1741 } else if (i == AsmDescOp && MO.isImm()) {
1742 // Pretty print the inline asm operand descriptor.
1743 OS << '$' << AsmOpCount++;
1744 unsigned Flag = MO.getImm();
1745 OS << ":[";
1746 OS << InlineAsm::getKindName(InlineAsm::getKind(Flag));
1747
1748 unsigned RCID = 0;
1749 if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1750 InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1751 if (TRI) {
1752 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1753 } else
1754 OS << ":RC" << RCID;
1755 }
1756
1757 if (InlineAsm::isMemKind(Flag)) {
1758 unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1759 OS << ":" << InlineAsm::getMemConstraintName(MCID);
1760 }
1761
1762 unsigned TiedTo = 0;
1763 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1764 OS << " tiedto:$" << TiedTo;
1765
1766 OS << ']';
1767
1768 // Compute the index of the next operand descriptor.
1769 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1770 } else {
1771 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1772 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1773 if (MO.isImm() && isOperandSubregIdx(i))
1774 MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI);
1775 else
1776 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1777 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1778 }
1779 }
1780
1781 // Print any optional symbols attached to this instruction as-if they were
1782 // operands.
1783 if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1784 if (!FirstOp) {
1785 FirstOp = false;
1786 OS << ',';
1787 }
1788 OS << " pre-instr-symbol ";
1789 MachineOperand::printSymbol(OS, *PreInstrSymbol);
1790 }
1791 if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1792 if (!FirstOp) {
1793 FirstOp = false;
1794 OS << ',';
1795 }
1796 OS << " post-instr-symbol ";
1797 MachineOperand::printSymbol(OS, *PostInstrSymbol);
1798 }
1799 if (MDNode *HeapAllocMarker = getHeapAllocMarker()) {
1800 if (!FirstOp) {
1801 FirstOp = false;
1802 OS << ',';
1803 }
1804 OS << " heap-alloc-marker ";
1805 HeapAllocMarker->printAsOperand(OS, MST);
1806 }
1807
1808 if (DebugInstrNum) {
1809 if (!FirstOp)
1810 OS << ",";
1811 OS << " debug-instr-number " << DebugInstrNum;
1812 }
1813
1814 if (!SkipDebugLoc) {
1815 if (const DebugLoc &DL = getDebugLoc()) {
1816 if (!FirstOp)
1817 OS << ',';
1818 OS << " debug-location ";
1819 DL->printAsOperand(OS, MST);
1820 }
1821 }
1822
1823 if (!memoperands_empty()) {
1824 SmallVector<StringRef, 0> SSNs;
1825 const LLVMContext *Context = nullptr;
1826 std::unique_ptr<LLVMContext> CtxPtr;
1827 const MachineFrameInfo *MFI = nullptr;
1828 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1829 MFI = &MF->getFrameInfo();
1830 Context = &MF->getFunction().getContext();
1831 } else {
1832 CtxPtr = std::make_unique<LLVMContext>();
1833 Context = CtxPtr.get();
1834 }
1835
1836 OS << " :: ";
1837 bool NeedComma = false;
1838 for (const MachineMemOperand *Op : memoperands()) {
1839 if (NeedComma)
1840 OS << ", ";
1841 Op->print(OS, MST, SSNs, *Context, MFI, TII);
1842 NeedComma = true;
1843 }
1844 }
1845
1846 if (SkipDebugLoc)
1847 return;
1848
1849 bool HaveSemi = false;
1850
1851 // Print debug location information.
1852 if (const DebugLoc &DL = getDebugLoc()) {
1853 if (!HaveSemi) {
1854 OS << ';';
1855 HaveSemi = true;
1856 }
1857 OS << ' ';
1858 DL.print(OS);
1859 }
1860
1861 // Print extra comments for DEBUG_VALUE.
1862 if (isDebugValue() && getDebugVariableOp().isMetadata()) {
1863 if (!HaveSemi) {
1864 OS << ";";
1865 HaveSemi = true;
1866 }
1867 auto *DV = getDebugVariable();
1868 OS << " line no:" << DV->getLine();
1869 if (isIndirectDebugValue())
1870 OS << " indirect";
1871 }
1872 // TODO: DBG_LABEL
1873
1874 if (AddNewLine)
1875 OS << '\n';
1876}
1877
1878bool MachineInstr::addRegisterKilled(Register IncomingReg,
1879 const TargetRegisterInfo *RegInfo,
1880 bool AddIfNotFound) {
1881 bool isPhysReg = Register::isPhysicalRegister(IncomingReg);
1882 bool hasAliases = isPhysReg &&
1883 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1884 bool Found = false;
1885 SmallVector<unsigned,4> DeadOps;
1886 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1887 MachineOperand &MO = getOperand(i);
1888 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1889 continue;
1890
1891 // DEBUG_VALUE nodes do not contribute to code generation and should
1892 // always be ignored. Failure to do so may result in trying to modify
1893 // KILL flags on DEBUG_VALUE nodes.
1894 if (MO.isDebug())
1895 continue;
1896
1897 Register Reg = MO.getReg();
1898 if (!Reg)
1899 continue;
1900
1901 if (Reg == IncomingReg) {
1902 if (!Found) {
1903 if (MO.isKill())
1904 // The register is already marked kill.
1905 return true;
1906 if (isPhysReg && isRegTiedToDefOperand(i))
1907 // Two-address uses of physregs must not be marked kill.
1908 return true;
1909 MO.setIsKill();
1910 Found = true;
1911 }
1912 } else if (hasAliases && MO.isKill() && Register::isPhysicalRegister(Reg)) {
1913 // A super-register kill already exists.
1914 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1915 return true;
1916 if (RegInfo->isSubRegister(IncomingReg, Reg))
1917 DeadOps.push_back(i);
1918 }
1919 }
1920
1921 // Trim unneeded kill operands.
1922 while (!DeadOps.empty()) {
1923 unsigned OpIdx = DeadOps.back();
1924 if (getOperand(OpIdx).isImplicit() &&
1925 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1926 RemoveOperand(OpIdx);
1927 else
1928 getOperand(OpIdx).setIsKill(false);
1929 DeadOps.pop_back();
1930 }
1931
1932 // If not found, this means an alias of one of the operands is killed. Add a
1933 // new implicit operand if required.
1934 if (!Found && AddIfNotFound) {
1935 addOperand(MachineOperand::CreateReg(IncomingReg,
1936 false /*IsDef*/,
1937 true /*IsImp*/,
1938 true /*IsKill*/));
1939 return true;
1940 }
1941 return Found;
1942}
1943
1944void MachineInstr::clearRegisterKills(Register Reg,
1945 const TargetRegisterInfo *RegInfo) {
1946 if (!Register::isPhysicalRegister(Reg))
1947 RegInfo = nullptr;
1948 for (MachineOperand &MO : operands()) {
1949 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1950 continue;
1951 Register OpReg = MO.getReg();
1952 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1953 MO.setIsKill(false);
1954 }
1955}
1956
1957bool MachineInstr::addRegisterDead(Register Reg,
1958 const TargetRegisterInfo *RegInfo,
1959 bool AddIfNotFound) {
1960 bool isPhysReg = Register::isPhysicalRegister(Reg);
1961 bool hasAliases = isPhysReg &&
1962 MCRegAliasIterator(Reg, RegInfo, false).isValid();
1963 bool Found = false;
1964 SmallVector<unsigned,4> DeadOps;
1965 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1966 MachineOperand &MO = getOperand(i);
1967 if (!MO.isReg() || !MO.isDef())
1968 continue;
1969 Register MOReg = MO.getReg();
1970 if (!MOReg)
1971 continue;
1972
1973 if (MOReg == Reg) {
1974 MO.setIsDead();
1975 Found = true;
1976 } else if (hasAliases && MO.isDead() &&
1977 Register::isPhysicalRegister(MOReg)) {
1978 // There exists a super-register that's marked dead.
1979 if (RegInfo->isSuperRegister(Reg, MOReg))
1980 return true;
1981 if (RegInfo->isSubRegister(Reg, MOReg))
1982 DeadOps.push_back(i);
1983 }
1984 }
1985
1986 // Trim unneeded dead operands.
1987 while (!DeadOps.empty()) {
1988 unsigned OpIdx = DeadOps.back();
1989 if (getOperand(OpIdx).isImplicit() &&
1990 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1991 RemoveOperand(OpIdx);
1992 else
1993 getOperand(OpIdx).setIsDead(false);
1994 DeadOps.pop_back();
1995 }
1996
1997 // If not found, this means an alias of one of the operands is dead. Add a
1998 // new implicit operand if required.
1999 if (Found || !AddIfNotFound)
2000 return Found;
2001
2002 addOperand(MachineOperand::CreateReg(Reg,
2003 true /*IsDef*/,
2004 true /*IsImp*/,
2005 false /*IsKill*/,
2006 true /*IsDead*/));
2007 return true;
2008}
2009
2010void MachineInstr::clearRegisterDeads(Register Reg) {
2011 for (MachineOperand &MO : operands()) {
2012 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
2013 continue;
2014 MO.setIsDead(false);
2015 }
2016}
2017
2018void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) {
2019 for (MachineOperand &MO : operands()) {
2020 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
2021 continue;
2022 MO.setIsUndef(IsUndef);
2023 }
2024}
2025
2026void MachineInstr::addRegisterDefined(Register Reg,
2027 const TargetRegisterInfo *RegInfo) {
2028 if (Register::isPhysicalRegister(Reg)) {
2029 MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
2030 if (MO)
2031 return;
2032 } else {
2033 for (const MachineOperand &MO : operands()) {
2034 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
2035 MO.getSubReg() == 0)
2036 return;
2037 }
2038 }
2039 addOperand(MachineOperand::CreateReg(Reg,
2040 true /*IsDef*/,
2041 true /*IsImp*/));
2042}
2043
2044void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
2045 const TargetRegisterInfo &TRI) {
2046 bool HasRegMask = false;
2047 for (MachineOperand &MO : operands()) {
2048 if (MO.isRegMask()) {
2049 HasRegMask = true;
2050 continue;
2051 }
2052 if (!MO.isReg() || !MO.isDef()) continue;
2053 Register Reg = MO.getReg();
2054 if (!Reg.isPhysical())
2055 continue;
2056 // If there are no uses, including partial uses, the def is dead.
2057 if (llvm::none_of(UsedRegs,
2058 [&](MCRegister Use) { return TRI.regsOverlap(Use, Reg); }))
2059 MO.setIsDead();
2060 }
2061
2062 // This is a call with a register mask operand.
2063 // Mask clobbers are always dead, so add defs for the non-dead defines.
2064 if (HasRegMask)
2065 for (const Register &UsedReg : UsedRegs)
2066 addRegisterDefined(UsedReg, &TRI);
2067}
2068
2069unsigned
2070MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
2071 // Build up a buffer of hash code components.
2072 SmallVector<size_t, 16> HashComponents;
2073 HashComponents.reserve(MI->getNumOperands() + 1);
2074 HashComponents.push_back(MI->getOpcode());
2075 for (const MachineOperand &MO : MI->operands()) {
2076 if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
2077 continue; // Skip virtual register defs.
2078
2079 HashComponents.push_back(hash_value(MO));
2080 }
2081 return hash_combine_range(HashComponents.begin(), HashComponents.end());
2082}
2083
2084void MachineInstr::emitError(StringRef Msg) const {
2085 // Find the source location cookie.
2086 uint64_t LocCookie = 0;
2087 const MDNode *LocMD = nullptr;
2088 for (unsigned i = getNumOperands(); i != 0; --i) {
2089 if (getOperand(i-1).isMetadata() &&
2090 (LocMD = getOperand(i-1).getMetadata()) &&
2091 LocMD->getNumOperands() != 0) {
2092 if (const ConstantInt *CI =
2093 mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
2094 LocCookie = CI->getZExtValue();
2095 break;
2096 }
2097 }
2098 }
2099
2100 if (const MachineBasicBlock *MBB = getParent())
2101 if (const MachineFunction *MF = MBB->getParent())
2102 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2103 report_fatal_error(Msg);
2104}
2105
2106MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2107 const MCInstrDesc &MCID, bool IsIndirect,
2108 Register Reg, const MDNode *Variable,
2109 const MDNode *Expr) {
2110 assert(isa<DILocalVariable>(Variable) && "not a variable")((void)0);
2111 assert(cast<DIExpression>(Expr)->isValid() && "not an expression")((void)0);
2112 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&((void)0)
2113 "Expected inlined-at fields to agree")((void)0);
2114 auto MIB = BuildMI(MF, DL, MCID).addReg(Reg, RegState::Debug);
2115 if (IsIndirect)
2116 MIB.addImm(0U);
2117 else
2118 MIB.addReg(0U, RegState::Debug);
2119 return MIB.addMetadata(Variable).addMetadata(Expr);
2120}
2121
2122MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2123 const MCInstrDesc &MCID, bool IsIndirect,
2124 const MachineOperand &MO,
2125 const MDNode *Variable, const MDNode *Expr) {
2126 assert(isa<DILocalVariable>(Variable) && "not a variable")((void)0);
2127 assert(cast<DIExpression>(Expr)->isValid() && "not an expression")((void)0);
2128 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&((void)0)
2129 "Expected inlined-at fields to agree")((void)0);
2130 if (MO.isReg())
2131 return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
2132
2133 auto MIB = BuildMI(MF, DL, MCID).add(MO);
2134 if (IsIndirect)
2135 MIB.addImm(0U);
2136 else
2137 MIB.addReg(0U, RegState::Debug);
2138 return MIB.addMetadata(Variable).addMetadata(Expr);
2139}
2140
2141MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2142 const MCInstrDesc &MCID, bool IsIndirect,
2143 ArrayRef<MachineOperand> MOs,
2144 const MDNode *Variable, const MDNode *Expr) {
2145 assert(isa<DILocalVariable>(Variable) && "not a variable")((void)0);
2146 assert(cast<DIExpression>(Expr)->isValid() && "not an expression")((void)0);
2147 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&((void)0)
2148 "Expected inlined-at fields to agree")((void)0);
2149 if (MCID.Opcode == TargetOpcode::DBG_VALUE)
2150 return BuildMI(MF, DL, MCID, IsIndirect, MOs[0], Variable, Expr);
2151
2152 auto MIB = BuildMI(MF, DL, MCID);
2153 MIB.addMetadata(Variable).addMetadata(Expr);
2154 for (const MachineOperand &MO : MOs)
2155 if (MO.isReg())
2156 MIB.addReg(MO.getReg(), RegState::Debug);
2157 else
2158 MIB.add(MO);
2159 return MIB;
2160}
2161
2162MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2163 MachineBasicBlock::iterator I,
2164 const DebugLoc &DL, const MCInstrDesc &MCID,
2165 bool IsIndirect, Register Reg,
2166 const MDNode *Variable, const MDNode *Expr) {
2167 MachineFunction &MF = *BB.getParent();
2168 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2169 BB.insert(I, MI);
2170 return MachineInstrBuilder(MF, MI);
2171}
2172
2173MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2174 MachineBasicBlock::iterator I,
2175 const DebugLoc &DL, const MCInstrDesc &MCID,
2176 bool IsIndirect, MachineOperand &MO,
2177 const MDNode *Variable, const MDNode *Expr) {
2178 MachineFunction &MF = *BB.getParent();
2179 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
2180 BB.insert(I, MI);
2181 return MachineInstrBuilder(MF, *MI);
2182}
2183
2184MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2185 MachineBasicBlock::iterator I,
2186 const DebugLoc &DL, const MCInstrDesc &MCID,
2187 bool IsIndirect, ArrayRef<MachineOperand> MOs,
2188 const MDNode *Variable, const MDNode *Expr) {
2189 MachineFunction &MF = *BB.getParent();
2190 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MOs, Variable, Expr);
2191 BB.insert(I, MI);
2192 return MachineInstrBuilder(MF, *MI);
2193}
2194
2195/// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2196/// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2197static const DIExpression *
2198computeExprForSpill(const MachineInstr &MI,
2199 SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2200 assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&((void)0)
2201 "Expected inlined-at fields to agree")((void)0);
2202
2203 const DIExpression *Expr = MI.getDebugExpression();
2204 if (MI.isIndirectDebugValue()) {
2205 assert(MI.getDebugOffset().getImm() == 0 &&((void)0)
2206 "DBG_VALUE with nonzero offset")((void)0);
2207 Expr = DIExpression::prepend(Expr, DIExpression::DerefBefore);
2208 } else if (MI.isDebugValueList()) {
2209 // We will replace the spilled register with a frame index, so
2210 // immediately deref all references to the spilled register.
2211 std::array<uint64_t, 1> Ops{{dwarf::DW_OP_deref}};
2212 for (const MachineOperand *Op : SpilledOperands) {
2213 unsigned OpIdx = MI.getDebugOperandIndex(Op);
2214 Expr = DIExpression::appendOpsToArg(Expr, Ops, OpIdx);
2215 }
2216 }
2217 return Expr;
2218}
2219static const DIExpression *computeExprForSpill(const MachineInstr &MI,
2220 Register SpillReg) {
2221 assert(MI.hasDebugOperandForReg(SpillReg) && "Spill Reg is not used in MI.")((void)0);
2222 SmallVector<const MachineOperand *> SpillOperands;
2223 for (const MachineOperand &Op : MI.getDebugOperandsForReg(SpillReg))
2224 SpillOperands.push_back(&Op);
2225 return computeExprForSpill(MI, SpillOperands);
2226}
2227
2228MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
2229 MachineBasicBlock::iterator I,
2230 const MachineInstr &Orig,
2231 int FrameIndex, Register SpillReg) {
2232 const DIExpression *Expr = computeExprForSpill(Orig, SpillReg);
2233 MachineInstrBuilder NewMI =
2234 BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
2235 // Non-Variadic Operands: Location, Offset, Variable, Expression
2236 // Variadic Operands: Variable, Expression, Locations...
2237 if (Orig.isNonListDebugValue())
2238 NewMI.addFrameIndex(FrameIndex).addImm(0U);
2239 NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2240 if (Orig.isDebugValueList()) {
2241 for (const MachineOperand &Op : Orig.debug_operands())
2242 if (Op.isReg() && Op.getReg() == SpillReg)
2243 NewMI.addFrameIndex(FrameIndex);
2244 else
2245 NewMI.add(MachineOperand(Op));
2246 }
2247 return NewMI;
2248}
2249MachineInstr *llvm::buildDbgValueForSpill(
2250 MachineBasicBlock &BB, MachineBasicBlock::iterator I,
2251 const MachineInstr &Orig, int FrameIndex,
2252 SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2253 const DIExpression *Expr = computeExprForSpill(Orig, SpilledOperands);
2254 MachineInstrBuilder NewMI =
2255 BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
1
Calling 'BuildMI'
→
3
←
Returning from 'BuildMI'
→
2256 // Non-Variadic Operands: Location, Offset, Variable, Expression
2257 // Variadic Operands: Variable, Expression, Locations...
2258 if (Orig.isNonListDebugValue())
4
←
Taking true branch
→
2259 NewMI.addFrameIndex(FrameIndex).addImm(0U);
5
←
Calling 'MachineInstrBuilder::addFrameIndex'
→
2260 NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2261 if (Orig.isDebugValueList()) {
2262 for (const MachineOperand &Op : Orig.debug_operands())
2263 if (is_contained(SpilledOperands, &Op))
2264 NewMI.addFrameIndex(FrameIndex);
2265 else
2266 NewMI.add(MachineOperand(Op));
2267 }
2268 return NewMI;
2269}
2270
2271void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex,
2272 Register Reg) {
2273 const DIExpression *Expr = computeExprForSpill(Orig, Reg);
2274 if (Orig.isNonListDebugValue())
2275 Orig.getDebugOffset().ChangeToImmediate(0U);
2276 for (MachineOperand &Op : Orig.getDebugOperandsForReg(Reg))
2277 Op.ChangeToFrameIndex(FrameIndex);
2278 Orig.getDebugExpressionOp().setMetadata(Expr);
2279}
2280
2281void MachineInstr::collectDebugValues(
2282 SmallVectorImpl<MachineInstr *> &DbgValues) {
2283 MachineInstr &MI = *this;
2284 if (!MI.getOperand(0).isReg())
2285 return;
2286
2287 MachineBasicBlock::iterator DI = MI; ++DI;
2288 for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2289 DI != DE; ++DI) {
2290 if (!DI->isDebugValue())
2291 return;
2292 if (DI->hasDebugOperandForReg(MI.getOperand(0).getReg()))
2293 DbgValues.push_back(&*DI);
2294 }
2295}
2296
2297void MachineInstr::changeDebugValuesDefReg(Register Reg) {
2298 // Collect matching debug values.
2299 SmallVector<MachineInstr *, 2> DbgValues;
2300
2301 if (!getOperand(0).isReg())
2302 return;
2303
2304 Register DefReg = getOperand(0).getReg();
2305 auto *MRI = getRegInfo();
2306 for (auto &MO : MRI->use_operands(DefReg)) {
2307 auto *DI = MO.getParent();
2308 if (!DI->isDebugValue())
2309 continue;
2310 if (DI->hasDebugOperandForReg(DefReg)) {
2311 DbgValues.push_back(DI);
2312 }
2313 }
2314
2315 // Propagate Reg to debug value instructions.
2316 for (auto *DBI : DbgValues)
2317 for (MachineOperand &Op : DBI->getDebugOperandsForReg(DefReg))
2318 Op.setReg(Reg);
2319}
2320
2321using MMOList = SmallVector<const MachineMemOperand *, 2>;
2322
2323static unsigned getSpillSlotSize(const MMOList &Accesses,
2324 const MachineFrameInfo &MFI) {
2325 unsigned Size = 0;
2326 for (auto A : Accesses)
2327 if (MFI.isSpillSlotObjectIndex(
2328 cast<FixedStackPseudoSourceValue>(A->getPseudoValue())
2329 ->getFrameIndex()))
2330 Size += A->getSize();
2331 return Size;
2332}
2333
2334Optional<unsigned>
2335MachineInstr::getSpillSize(const TargetInstrInfo *TII) const {
2336 int FI;
2337 if (TII->isStoreToStackSlotPostFE(*this, FI)) {
2338 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2339 if (MFI.isSpillSlotObjectIndex(FI))
2340 return (*memoperands_begin())->getSize();
2341 }
2342 return None;
2343}
2344
2345Optional<unsigned>
2346MachineInstr::getFoldedSpillSize(const TargetInstrInfo *TII) const {
2347 MMOList Accesses;
2348 if (TII->hasStoreToStackSlot(*this, Accesses))
2349 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2350 return None;
2351}
2352
2353Optional<unsigned>
2354MachineInstr::getRestoreSize(const TargetInstrInfo *TII) const {
2355 int FI;
2356 if (TII->isLoadFromStackSlotPostFE(*this, FI)) {
2357 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2358 if (MFI.isSpillSlotObjectIndex(FI))
2359 return (*memoperands_begin())->getSize();
2360 }
2361 return None;
2362}
2363
2364Optional<unsigned>
2365MachineInstr::getFoldedRestoreSize(const TargetInstrInfo *TII) const {
2366 MMOList Accesses;
2367 if (TII->hasLoadFromStackSlot(*this, Accesses))
2368 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2369 return None;
2370}
2371
2372unsigned MachineInstr::getDebugInstrNum() {
2373 if (DebugInstrNum == 0)
2374 DebugInstrNum = getParent()->getParent()->getNewDebugInstrNum();
2375 return DebugInstrNum;
2376}
2377
2378unsigned MachineInstr::getDebugInstrNum(MachineFunction &MF) {
2379 if (DebugInstrNum == 0)
2380 DebugInstrNum = MF.getNewDebugInstrNum();
2381 return DebugInstrNum;
2382}
←

/usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/CodeGen/MachineInstrBuilder.h

1//===- CodeGen/MachineInstrBuilder.h - Simplify creation of MIs --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file exposes a function named BuildMI, which is useful for dramatically
10// simplifying how MachineInstr's are created. It allows use of code like this:
11//
12// M = BuildMI(MBB, MI, DL, TII.get(X86::ADD8rr), Dst)
13// .addReg(argVal1)
14// .addReg(argVal2);
15//
16//===----------------------------------------------------------------------===//
17
18#ifndef LLVM_CODEGEN_MACHINEINSTRBUILDER_H
19#define LLVM_CODEGEN_MACHINEINSTRBUILDER_H
20
21#include "llvm/ADT/ArrayRef.h"
22#include "llvm/CodeGen/GlobalISel/Utils.h"
23#include "llvm/CodeGen/MachineBasicBlock.h"
24#include "llvm/CodeGen/MachineFunction.h"
25#include "llvm/CodeGen/MachineInstr.h"
26#include "llvm/CodeGen/MachineInstrBundle.h"
27#include "llvm/CodeGen/MachineOperand.h"
28#include "llvm/CodeGen/TargetRegisterInfo.h"
29#include "llvm/IR/InstrTypes.h"
30#include "llvm/IR/Intrinsics.h"
31#include "llvm/Support/ErrorHandling.h"
32#include <cassert>
33#include <cstdint>
34
35namespace llvm {
36
37class MCInstrDesc;
38class MDNode;
39
40namespace RegState {
41
42enum {
43 /// Register definition.
44 Define = 0x2,
45 /// Not emitted register (e.g. carry, or temporary result).
46 Implicit = 0x4,
47 /// The last use of a register.
48 Kill = 0x8,
49 /// Unused definition.
50 Dead = 0x10,
51 /// Value of the register doesn't matter.
52 Undef = 0x20,
53 /// Register definition happens before uses.
54 EarlyClobber = 0x40,
55 /// Register 'use' is for debugging purpose.
56 Debug = 0x80,
57 /// Register reads a value that is defined inside the same instruction or
58 /// bundle.
59 InternalRead = 0x100,
60 /// Register that may be renamed.
61 Renamable = 0x200,
62 DefineNoRead = Define | Undef,
63 ImplicitDefine = Implicit | Define,
64 ImplicitKill = Implicit | Kill
65};
66
67} // end namespace RegState
68
69class MachineInstrBuilder {
70 MachineFunction *MF = nullptr;
71 MachineInstr *MI = nullptr;
72
73public:
74 MachineInstrBuilder() = default;
75
76 /// Create a MachineInstrBuilder for manipulating an existing instruction.
77 /// F must be the machine function that was used to allocate I.
78 MachineInstrBuilder(MachineFunction &F, MachineInstr *I) : MF(&F), MI(I) {}
79 MachineInstrBuilder(MachineFunction &F, MachineBasicBlock::iterator I)
80 : MF(&F), MI(&*I) {}
81
82 /// Allow automatic conversion to the machine instruction we are working on.
83 operator MachineInstr*() const { return MI; }
84 MachineInstr *operator->() const { return MI; }
85 operator MachineBasicBlock::iterator() const { return MI; }
86
87 /// If conversion operators fail, use this method to get the MachineInstr
88 /// explicitly.
89 MachineInstr *getInstr() const { return MI; }
90
91 /// Get the register for the operand index.
92 /// The operand at the index should be a register (asserted by
93 /// MachineOperand).
94 Register getReg(unsigned Idx) const { return MI->getOperand(Idx).getReg(); }
95
96 /// Add a new virtual register operand.
97 const MachineInstrBuilder &addReg(Register RegNo, unsigned flags = 0,
98 unsigned SubReg = 0) const {
99 assert((flags & 0x1) == 0 &&((void)0)
100 "Passing in 'true' to addReg is forbidden! Use enums instead.")((void)0);
101 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
102 flags & RegState::Define,
103 flags & RegState::Implicit,
104 flags & RegState::Kill,
105 flags & RegState::Dead,
106 flags & RegState::Undef,
107 flags & RegState::EarlyClobber,
108 SubReg,
109 flags & RegState::Debug,
110 flags & RegState::InternalRead,
111 flags & RegState::Renamable));
112 return *this;
113 }
114
115 /// Add a virtual register definition operand.
116 const MachineInstrBuilder &addDef(Register RegNo, unsigned Flags = 0,
117 unsigned SubReg = 0) const {
118 return addReg(RegNo, Flags | RegState::Define, SubReg);
119 }
120
121 /// Add a virtual register use operand. It is an error for Flags to contain
122 /// `RegState::Define` when calling this function.
123 const MachineInstrBuilder &addUse(Register RegNo, unsigned Flags = 0,
124 unsigned SubReg = 0) const {
125 assert(!(Flags & RegState::Define) &&((void)0)
126 "Misleading addUse defines register, use addReg instead.")((void)0);
127 return addReg(RegNo, Flags, SubReg);
128 }
129
130 /// Add a new immediate operand.
131 const MachineInstrBuilder &addImm(int64_t Val) const {
132 MI->addOperand(*MF, MachineOperand::CreateImm(Val));
133 return *this;
134 }
135
136 const MachineInstrBuilder &addCImm(const ConstantInt *Val) const {
137 MI->addOperand(*MF, MachineOperand::CreateCImm(Val));
138 return *this;
139 }
140
141 const MachineInstrBuilder &addFPImm(const ConstantFP *Val) const {
142 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val));
143 return *this;
144 }
145
146 const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB,
147 unsigned TargetFlags = 0) const {
148 MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
149 return *this;
150 }
151
152 const MachineInstrBuilder &addFrameIndex(int Idx) const {
153 MI->addOperand(*MF, MachineOperand::CreateFI(Idx));
6
←
Calling 'MachineInstr::addOperand'
→
154 return *this;
155 }
156
157 const MachineInstrBuilder &
158 addConstantPoolIndex(unsigned Idx, int Offset = 0,
159 unsigned TargetFlags = 0) const {
160 MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
161 return *this;
162 }
163
164 const MachineInstrBuilder &addTargetIndex(unsigned Idx, int64_t Offset = 0,
165 unsigned TargetFlags = 0) const {
166 MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset,
167 TargetFlags));
168 return *this;
169 }
170
171 const MachineInstrBuilder &addJumpTableIndex(unsigned Idx,
172 unsigned TargetFlags = 0) const {
173 MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
174 return *this;
175 }
176
177 const MachineInstrBuilder &addGlobalAddress(const GlobalValue *GV,
178 int64_t Offset = 0,
179 unsigned TargetFlags = 0) const {
180 MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags));
181 return *this;
182 }
183
184 const MachineInstrBuilder &addExternalSymbol(const char *FnName,
185 unsigned TargetFlags = 0) const {
186 MI->addOperand(*MF, MachineOperand::CreateES(FnName, TargetFlags));
187 return *this;
188 }
189
190 const MachineInstrBuilder &addBlockAddress(const BlockAddress *BA,
191 int64_t Offset = 0,
192 unsigned TargetFlags = 0) const {
193 MI->addOperand(*MF, MachineOperand::CreateBA(BA, Offset, TargetFlags));
194 return *this;
195 }
196
197 const MachineInstrBuilder &addRegMask(const uint32_t *Mask) const {
198 MI->addOperand(*MF, MachineOperand::CreateRegMask(Mask));
199 return *this;
200 }
201
202 const MachineInstrBuilder &addMemOperand(MachineMemOperand *MMO) const {
203 MI->addMemOperand(*MF, MMO);
204 return *this;
205 }
206
207 const MachineInstrBuilder &
208 setMemRefs(ArrayRef<MachineMemOperand *> MMOs) const {
209 MI->setMemRefs(*MF, MMOs);
210 return *this;
211 }
212
213 const MachineInstrBuilder &cloneMemRefs(const MachineInstr &OtherMI) const {
214 MI->cloneMemRefs(*MF, OtherMI);
215 return *this;
216 }
217
218 const MachineInstrBuilder &
219 cloneMergedMemRefs(ArrayRef<const MachineInstr *> OtherMIs) const {
220 MI->cloneMergedMemRefs(*MF, OtherMIs);
221 return *this;
222 }
223
224 const MachineInstrBuilder &add(const MachineOperand &MO) const {
225 MI->addOperand(*MF, MO);
226 return *this;
227 }
228
229 const MachineInstrBuilder &add(ArrayRef<MachineOperand> MOs) const {
230 for (const MachineOperand &MO : MOs) {
231 MI->addOperand(*MF, MO);
232 }
233 return *this;
234 }
235
236 const MachineInstrBuilder &addMetadata(const MDNode *MD) const {
237 MI->addOperand(*MF, MachineOperand::CreateMetadata(MD));
238 assert((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable())((void)0)
239 : true) &&((void)0)
240 "first MDNode argument of a DBG_VALUE not a variable")((void)0);
241 assert((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel())((void)0)
242 : true) &&((void)0)
243 "first MDNode argument of a DBG_LABEL not a label")((void)0);
244 return *this;
245 }
246
247 const MachineInstrBuilder &addCFIIndex(unsigned CFIIndex) const {
248 MI->addOperand(*MF, MachineOperand::CreateCFIIndex(CFIIndex));
249 return *this;
250 }
251
252 const MachineInstrBuilder &addIntrinsicID(Intrinsic::ID ID) const {
253 MI->addOperand(*MF, MachineOperand::CreateIntrinsicID(ID));
254 return *this;
255 }
256
257 const MachineInstrBuilder &addPredicate(CmpInst::Predicate Pred) const {
258 MI->addOperand(*MF, MachineOperand::CreatePredicate(Pred));
259 return *this;
260 }
261
262 const MachineInstrBuilder &addShuffleMask(ArrayRef<int> Val) const {
263 MI->addOperand(*MF, MachineOperand::CreateShuffleMask(Val));
264 return *this;
265 }
266
267 const MachineInstrBuilder &addSym(MCSymbol *Sym,
268 unsigned char TargetFlags = 0) const {
269 MI->addOperand(*MF, MachineOperand::CreateMCSymbol(Sym, TargetFlags));
270 return *this;
271 }
272
273 const MachineInstrBuilder &setMIFlags(unsigned Flags) const {
274 MI->setFlags(Flags);
275 return *this;
276 }
277
278 const MachineInstrBuilder &setMIFlag(MachineInstr::MIFlag Flag) const {
279 MI->setFlag(Flag);
280 return *this;
281 }
282
283 // Add a displacement from an existing MachineOperand with an added offset.
284 const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off,
285 unsigned char TargetFlags = 0) const {
286 // If caller specifies new TargetFlags then use it, otherwise the
287 // default behavior is to copy the target flags from the existing
288 // MachineOperand. This means if the caller wants to clear the
289 // target flags it needs to do so explicitly.
290 if (0 == TargetFlags)
291 TargetFlags = Disp.getTargetFlags();
292
293 switch (Disp.getType()) {
294 default:
295 llvm_unreachable("Unhandled operand type in addDisp()")__builtin_unreachable();
296 case MachineOperand::MO_Immediate:
297 return addImm(Disp.getImm() + off);
298 case MachineOperand::MO_ConstantPoolIndex:
299 return addConstantPoolIndex(Disp.getIndex(), Disp.getOffset() + off,
300 TargetFlags);
301 case MachineOperand::MO_GlobalAddress:
302 return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off,
303 TargetFlags);
304 case MachineOperand::MO_BlockAddress:
305 return addBlockAddress(Disp.getBlockAddress(), Disp.getOffset() + off,
306 TargetFlags);
307 case MachineOperand::MO_JumpTableIndex:
308 assert(off == 0 && "cannot create offset into jump tables")((void)0);
309 return addJumpTableIndex(Disp.getIndex(), TargetFlags);
310 }
311 }
312
313 /// Copy all the implicit operands from OtherMI onto this one.
314 const MachineInstrBuilder &
315 copyImplicitOps(const MachineInstr &OtherMI) const {
316 MI->copyImplicitOps(*MF, OtherMI);
317 return *this;
318 }
319
320 bool constrainAllUses(const TargetInstrInfo &TII,
321 const TargetRegisterInfo &TRI,
322 const RegisterBankInfo &RBI) const {
323 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
324 }
325};
326
327/// Builder interface. Specify how to create the initial instruction itself.
328inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
329 const MCInstrDesc &MCID) {
330 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL));
331}
332
333/// This version of the builder sets up the first operand as a
334/// destination virtual register.
335inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
336 const MCInstrDesc &MCID, Register DestReg) {
337 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL))
338 .addReg(DestReg, RegState::Define);
339}
340
341/// This version of the builder inserts the newly-built instruction before
342/// the given position in the given MachineBasicBlock, and sets up the first
343/// operand as a destination virtual register.
344inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
345 MachineBasicBlock::iterator I,
346 const DebugLoc &DL, const MCInstrDesc &MCID,
347 Register DestReg) {
348 MachineFunction &MF = *BB.getParent();
349 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
350 BB.insert(I, MI);
351 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
352}
353
354/// This version of the builder inserts the newly-built instruction before
355/// the given position in the given MachineBasicBlock, and sets up the first
356/// operand as a destination virtual register.
357///
358/// If \c I is inside a bundle, then the newly inserted \a MachineInstr is
359/// added to the same bundle.
360inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
361 MachineBasicBlock::instr_iterator I,
362 const DebugLoc &DL, const MCInstrDesc &MCID,
363 Register DestReg) {
364 MachineFunction &MF = *BB.getParent();
365 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
366 BB.insert(I, MI);
367 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
368}
369
370inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
371 const DebugLoc &DL, const MCInstrDesc &MCID,
372 Register DestReg) {
373 // Calling the overload for instr_iterator is always correct. However, the
374 // definition is not available in headers, so inline the check.
375 if (I.isInsideBundle())
376 return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID, DestReg);
377 return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID, DestReg);
378}
379
380inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
381 const DebugLoc &DL, const MCInstrDesc &MCID,
382 Register DestReg) {
383 return BuildMI(BB, *I, DL, MCID, DestReg);
384}
385
386/// This version of the builder inserts the newly-built instruction before the
387/// given position in the given MachineBasicBlock, and does NOT take a
388/// destination register.
389inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
390 MachineBasicBlock::iterator I,
391 const DebugLoc &DL,
392 const MCInstrDesc &MCID) {
393 MachineFunction &MF = *BB.getParent();
394 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
395 BB.insert(I, MI);
2
←
Value assigned to field 'Operands'
→
396 return MachineInstrBuilder(MF, MI);
397}
398
399inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
400 MachineBasicBlock::instr_iterator I,
401 const DebugLoc &DL,
402 const MCInstrDesc &MCID) {
403 MachineFunction &MF = *BB.getParent();
404 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
405 BB.insert(I, MI);
406 return MachineInstrBuilder(MF, MI);
407}
408
409inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
410 const DebugLoc &DL,
411 const MCInstrDesc &MCID) {
412 // Calling the overload for instr_iterator is always correct. However, the
413 // definition is not available in headers, so inline the check.
414 if (I.isInsideBundle())
415 return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID);
416 return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID);
417}
418
419inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
420 const DebugLoc &DL,
421 const MCInstrDesc &MCID) {
422 return BuildMI(BB, *I, DL, MCID);
423}
424
425/// This version of the builder inserts the newly-built instruction at the end
426/// of the given MachineBasicBlock, and does NOT take a destination register.
427inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc &DL,
428 const MCInstrDesc &MCID) {
429 return BuildMI(*BB, BB->end(), DL, MCID);
430}
431
432/// This version of the builder inserts the newly-built instruction at the
433/// end of the given MachineBasicBlock, and sets up the first operand as a
434/// destination virtual register.
435inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc &DL,
436 const MCInstrDesc &MCID, Register DestReg) {
437 return BuildMI(*BB, BB->end(), DL, MCID, DestReg);
438}
439
440/// This version of the builder builds a DBG_VALUE intrinsic
441/// for either a value in a register or a register-indirect
442/// address. The convention is that a DBG_VALUE is indirect iff the
443/// second operand is an immediate.
444MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
445 const MCInstrDesc &MCID, bool IsIndirect,
446 Register Reg, const MDNode *Variable,
447 const MDNode *Expr);
448
449/// This version of the builder builds a DBG_VALUE intrinsic
450/// for a MachineOperand.
451MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
452 const MCInstrDesc &MCID, bool IsIndirect,
453 const MachineOperand &MO, const MDNode *Variable,
454 const MDNode *Expr);
455
456/// This version of the builder builds a DBG_VALUE or DBG_VALUE_LIST intrinsic
457/// for a MachineOperand.
458MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
459 const MCInstrDesc &MCID, bool IsIndirect,
460 ArrayRef<MachineOperand> MOs,
461 const MDNode *Variable, const MDNode *Expr);
462
463/// This version of the builder builds a DBG_VALUE intrinsic
464/// for either a value in a register or a register-indirect
465/// address and inserts it at position I.
466MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
467 MachineBasicBlock::iterator I, const DebugLoc &DL,
468 const MCInstrDesc &MCID, bool IsIndirect,
469 Register Reg, const MDNode *Variable,
470 const MDNode *Expr);
471
472/// This version of the builder builds a DBG_VALUE intrinsic
473/// for a machine operand and inserts it at position I.
474MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
475 MachineBasicBlock::iterator I, const DebugLoc &DL,
476 const MCInstrDesc &MCID, bool IsIndirect,
477 MachineOperand &MO, const MDNode *Variable,
478 const MDNode *Expr);
479
480/// This version of the builder builds a DBG_VALUE or DBG_VALUE_LIST intrinsic
481/// for a machine operand and inserts it at position I.
482MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
483 MachineBasicBlock::iterator I, const DebugLoc &DL,
484 const MCInstrDesc &MCID, bool IsIndirect,
485 ArrayRef<MachineOperand> MOs,
486 const MDNode *Variable, const MDNode *Expr);
487
488/// Clone a DBG_VALUE whose value has been spilled to FrameIndex.
489MachineInstr *buildDbgValueForSpill(MachineBasicBlock &BB,
490 MachineBasicBlock::iterator I,
491 const MachineInstr &Orig, int FrameIndex,
492 Register SpillReg);
493MachineInstr *
494buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I,
495 const MachineInstr &Orig, int FrameIndex,
496 SmallVectorImpl<const MachineOperand *> &SpilledOperands);
497
498/// Update a DBG_VALUE whose value has been spilled to FrameIndex. Useful when
499/// modifying an instruction in place while iterating over a basic block.
500void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg);
501
502inline unsigned getDefRegState(bool B) {
503 return B ? RegState::Define : 0;
504}
505inline unsigned getImplRegState(bool B) {
506 return B ? RegState::Implicit : 0;
507}
508inline unsigned getKillRegState(bool B) {
509 return B ? RegState::Kill : 0;
510}
511inline unsigned getDeadRegState(bool B) {
512 return B ? RegState::Dead : 0;
513}
514inline unsigned getUndefRegState(bool B) {
515 return B ? RegState::Undef : 0;
516}
517inline unsigned getInternalReadRegState(bool B) {
518 return B ? RegState::InternalRead : 0;
519}
520inline unsigned getDebugRegState(bool B) {
521 return B ? RegState::Debug : 0;
522}
523inline unsigned getRenamableRegState(bool B) {
524 return B ? RegState::Renamable : 0;
525}
526
527/// Get all register state flags from machine operand \p RegOp.
528inline unsigned getRegState(const MachineOperand &RegOp) {
529 assert(RegOp.isReg() && "Not a register operand")((void)0);
530 return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) |
531 getKillRegState(RegOp.isKill()) | getDeadRegState(RegOp.isDead()) |
532 getUndefRegState(RegOp.isUndef()) |
533 getInternalReadRegState(RegOp.isInternalRead()) |
534 getDebugRegState(RegOp.isDebug()) |
535 getRenamableRegState(Register::isPhysicalRegister(RegOp.getReg()) &&
536 RegOp.isRenamable());
537}
538
539/// Helper class for constructing bundles of MachineInstrs.
540///
541/// MIBundleBuilder can create a bundle from scratch by inserting new
542/// MachineInstrs one at a time, or it can create a bundle from a sequence of
543/// existing MachineInstrs in a basic block.
544class MIBundleBuilder {
545 MachineBasicBlock &MBB;
546 MachineBasicBlock::instr_iterator Begin;
547 MachineBasicBlock::instr_iterator End;
548
549public:
550 /// Create an MIBundleBuilder that inserts instructions into a new bundle in
551 /// BB above the bundle or instruction at Pos.
552 MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator Pos)
553 : MBB(BB), Begin(Pos.getInstrIterator()), End(Begin) {}
554
555 /// Create a bundle from the sequence of instructions between B and E.
556 MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator B,
557 MachineBasicBlock::iterator E)
558 : MBB(BB), Begin(B.getInstrIterator()), End(E.getInstrIterator()) {
559 assert(B != E && "No instructions to bundle")((void)0);
560 ++B;
561 while (B != E) {
562 MachineInstr &MI = *B;
563 ++B;
564 MI.bundleWithPred();
565 }
566 }
567
568 /// Create an MIBundleBuilder representing an existing instruction or bundle
569 /// that has MI as its head.
570 explicit MIBundleBuilder(MachineInstr *MI)
571 : MBB(*MI->getParent()), Begin(MI),
572 End(getBundleEnd(MI->getIterator())) {}
573
574 /// Return a reference to the basic block containing this bundle.
575 MachineBasicBlock &getMBB() const { return MBB; }
576
577 /// Return true if no instructions have been inserted in this bundle yet.
578 /// Empty bundles aren't representable in a MachineBasicBlock.
579 bool empty() const { return Begin == End; }
580
581 /// Return an iterator to the first bundled instruction.
582 MachineBasicBlock::instr_iterator begin() const { return Begin; }
583
584 /// Return an iterator beyond the last bundled instruction.
585 MachineBasicBlock::instr_iterator end() const { return End; }
586
587 /// Insert MI into this bundle before I which must point to an instruction in
588 /// the bundle, or end().
589 MIBundleBuilder &insert(MachineBasicBlock::instr_iterator I,
590 MachineInstr *MI) {
591 MBB.insert(I, MI);
592 if (I == Begin) {
593 if (!empty())
594 MI->bundleWithSucc();
595 Begin = MI->getIterator();
596 return *this;
597 }
598 if (I == End) {
599 MI->bundleWithPred();
600 return *this;
601 }
602 // MI was inserted in the middle of the bundle, so its neighbors' flags are
603 // already fine. Update MI's bundle flags manually.
604 MI->setFlag(MachineInstr::BundledPred);
605 MI->setFlag(MachineInstr::BundledSucc);
606 return *this;
607 }
608
609 /// Insert MI into MBB by prepending it to the instructions in the bundle.
610 /// MI will become the first instruction in the bundle.
611 MIBundleBuilder &prepend(MachineInstr *MI) {
612 return insert(begin(), MI);
613 }
614
615 /// Insert MI into MBB by appending it to the instructions in the bundle.
616 /// MI will become the last instruction in the bundle.
617 MIBundleBuilder &append(MachineInstr *MI) {
618 return insert(end(), MI);
619 }
620};
621
622} // end namespace llvm
623
624#endif // LLVM_CODEGEN_MACHINEINSTRBUILDER_H