Bug Summary

File:src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/MC/MCRegisterInfo.h
Warning:line 217, column 21
Dereference of null pointer

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name CriticalAntiDepBreaker.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model pic -pic-level 1 -fhalf-no-semantic-interposition -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/gnu/usr.bin/clang/libLLVM/obj -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Analysis -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ASMParser -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/BinaryFormat -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Bitcode -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Bitcode -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Bitstream -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /include/llvm/CodeGen -I /include/llvm/CodeGen/PBQP -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/IR -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/IR -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/Coroutines -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ProfileData/Coverage -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/CodeView -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/DWARF -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/MSF -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/PDB -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Demangle -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ExecutionEngine -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ExecutionEngine/JITLink -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ExecutionEngine/Orc -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Frontend -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Frontend/OpenACC -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Frontend -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Frontend/OpenMP -I /include/llvm/CodeGen/GlobalISel -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/IRReader -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/InstCombine -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/Transforms/InstCombine -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/LTO -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Linker -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/MC -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/MC/MCParser -I /include/llvm/CodeGen/MIRParser -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Object -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Option -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Passes -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ProfileData -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/Scalar -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ADT -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Support -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/Symbolize -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Target -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/Utils -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/Vectorize -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/IPO -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include -I /usr/src/gnu/usr.bin/clang/libLLVM/../include -I /usr/src/gnu/usr.bin/clang/libLLVM/obj -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include -D NDEBUG -D __STDC_LIMIT_MACROS -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D LLVM_PREFIX="/usr" -D PIC -internal-isystem /usr/include/c++/v1 -internal-isystem /usr/local/lib/clang/13.0.0/include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/usr/src/gnu/usr.bin/clang/libLLVM/obj -ferror-limit 19 -fvisibility-inlines-hidden -fwrapv -D_RET_PROTECTOR -ret-protector -fno-rtti -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /home/ben/Projects/vmm/scan-build/2022-01-12-194120-40624-1 -x c++ /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp

/usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp

→
1//===- CriticalAntiDepBreaker.cpp - Anti-dep breaker ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the CriticalAntiDepBreaker class, which
10// implements register anti-dependence breaking along a blocks
11// critical path during post-RA scheduler.
12//
13//===----------------------------------------------------------------------===//
14
15#include "CriticalAntiDepBreaker.h"
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/ADT/DenseMap.h"
18#include "llvm/ADT/SmallVector.h"
19#include "llvm/CodeGen/MachineBasicBlock.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstr.h"
23#include "llvm/CodeGen/MachineOperand.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/RegisterClassInfo.h"
26#include "llvm/CodeGen/ScheduleDAG.h"
27#include "llvm/CodeGen/TargetInstrInfo.h"
28#include "llvm/CodeGen/TargetRegisterInfo.h"
29#include "llvm/CodeGen/TargetSubtargetInfo.h"
30#include "llvm/MC/MCInstrDesc.h"
31#include "llvm/MC/MCRegisterInfo.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/raw_ostream.h"
34#include <cassert>
35#include <utility>
36
37using namespace llvm;
38
39#define DEBUG_TYPE"post-RA-sched" "post-RA-sched"
40
41CriticalAntiDepBreaker::CriticalAntiDepBreaker(MachineFunction &MFi,
42 const RegisterClassInfo &RCI)
43 : AntiDepBreaker(), MF(MFi), MRI(MF.getRegInfo()),
44 TII(MF.getSubtarget().getInstrInfo()),
45 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI),
46 Classes(TRI->getNumRegs(), nullptr), KillIndices(TRI->getNumRegs(), 0),
47 DefIndices(TRI->getNumRegs(), 0), KeepRegs(TRI->getNumRegs(), false) {}
48
49CriticalAntiDepBreaker::~CriticalAntiDepBreaker() = default;
50
51void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
52 const unsigned BBSize = BB->size();
53 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
54 // Clear out the register class data.
55 Classes[i] = nullptr;
56
57 // Initialize the indices to indicate that no registers are live.
58 KillIndices[i] = ~0u;
59 DefIndices[i] = BBSize;
60 }
61
62 // Clear "do not change" set.
63 KeepRegs.reset();
64
65 bool IsReturnBlock = BB->isReturnBlock();
66
67 // Examine the live-in regs of all successors.
68 for (const MachineBasicBlock *Succ : BB->successors())
69 for (const auto &LI : Succ->liveins()) {
70 for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) {
71 unsigned Reg = *AI;
72 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
73 KillIndices[Reg] = BBSize;
74 DefIndices[Reg] = ~0u;
75 }
76 }
77
78 // Mark live-out callee-saved registers. In a return block this is
79 // all callee-saved registers. In non-return this is any
80 // callee-saved register that is not saved in the prolog.
81 const MachineFrameInfo &MFI = MF.getFrameInfo();
82 BitVector Pristine = MFI.getPristineRegs(MF);
83 for (const MCPhysReg *I = MF.getRegInfo().getCalleeSavedRegs(); *I;
84 ++I) {
85 unsigned Reg = *I;
86 if (!IsReturnBlock && !Pristine.test(Reg))
87 continue;
88 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
89 unsigned Reg = *AI;
90 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
91 KillIndices[Reg] = BBSize;
92 DefIndices[Reg] = ~0u;
93 }
94 }
95}
96
97void CriticalAntiDepBreaker::FinishBlock() {
98 RegRefs.clear();
99 KeepRegs.reset();
100}
101
102void CriticalAntiDepBreaker::Observe(MachineInstr &MI, unsigned Count,
103 unsigned InsertPosIndex) {
104 // Kill instructions can define registers but are really nops, and there might
105 // be a real definition earlier that needs to be paired with uses dominated by
106 // this kill.
107
108 // FIXME: It may be possible to remove the isKill() restriction once PR18663
109 // has been properly fixed. There can be value in processing kills as seen in
110 // the AggressiveAntiDepBreaker class.
111 if (MI.isDebugInstr() || MI.isKill())
112 return;
113 assert(Count < InsertPosIndex && "Instruction index out of expected range!")((void)0);
114
115 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
116 if (KillIndices[Reg] != ~0u) {
117 // If Reg is currently live, then mark that it can't be renamed as
118 // we don't know the extent of its live-range anymore (now that it
119 // has been scheduled).
120 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
121 KillIndices[Reg] = Count;
122 } else if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) {
123 // Any register which was defined within the previous scheduling region
124 // may have been rescheduled and its lifetime may overlap with registers
125 // in ways not reflected in our current liveness state. For each such
126 // register, adjust the liveness state to be conservatively correct.
127 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
128
129 // Move the def index to the end of the previous region, to reflect
130 // that the def could theoretically have been scheduled at the end.
131 DefIndices[Reg] = InsertPosIndex;
132 }
133 }
134
135 PrescanInstruction(MI);
136 ScanInstruction(MI, Count);
137}
138
139/// CriticalPathStep - Return the next SUnit after SU on the bottom-up
140/// critical path.
141static const SDep *CriticalPathStep(const SUnit *SU) {
142 const SDep *Next = nullptr;
143 unsigned NextDepth = 0;
144 // Find the predecessor edge with the greatest depth.
145 for (const SDep &P : SU->Preds) {
146 const SUnit *PredSU = P.getSUnit();
147 unsigned PredLatency = P.getLatency();
148 unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
149 // In the case of a latency tie, prefer an anti-dependency edge over
150 // other types of edges.
151 if (NextDepth < PredTotalLatency ||
152 (NextDepth == PredTotalLatency && P.getKind() == SDep::Anti)) {
153 NextDepth = PredTotalLatency;
154 Next = &P;
155 }
156 }
157 return Next;
158}
159
160void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr &MI) {
161 // It's not safe to change register allocation for source operands of
162 // instructions that have special allocation requirements. Also assume all
163 // registers used in a call must not be changed (ABI).
164 // FIXME: The issue with predicated instruction is more complex. We are being
165 // conservative here because the kill markers cannot be trusted after
166 // if-conversion:
167 // %r6 = LDR %sp, %reg0, 92, 14, %reg0; mem:LD4[FixedStack14]
168 // ...
169 // STR %r0, killed %r6, %reg0, 0, 0, %cpsr; mem:ST4[%395]
170 // %r6 = LDR %sp, %reg0, 100, 0, %cpsr; mem:LD4[FixedStack12]
171 // STR %r0, killed %r6, %reg0, 0, 14, %reg0; mem:ST4[%396](align=8)
172 //
173 // The first R6 kill is not really a kill since it's killed by a predicated
174 // instruction which may not be executed. The second R6 def may or may not
175 // re-define R6 so it's not safe to change it since the last R6 use cannot be
176 // changed.
177 bool Special =
178 MI.isCall() || MI.hasExtraSrcRegAllocReq() || TII->isPredicated(MI);
179
180 // Scan the register operands for this instruction and update
181 // Classes and RegRefs.
182 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
183 MachineOperand &MO = MI.getOperand(i);
184 if (!MO.isReg()) continue;
185 Register Reg = MO.getReg();
186 if (Reg == 0) continue;
187 const TargetRegisterClass *NewRC = nullptr;
188
189 if (i < MI.getDesc().getNumOperands())
190 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
191
192 // For now, only allow the register to be changed if its register
193 // class is consistent across all uses.
194 if (!Classes[Reg] && NewRC)
195 Classes[Reg] = NewRC;
196 else if (!NewRC || Classes[Reg] != NewRC)
197 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
198
199 // Now check for aliases.
200 for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
201 // If an alias of the reg is used during the live range, give up.
202 // Note that this allows us to skip checking if AntiDepReg
203 // overlaps with any of the aliases, among other things.
204 unsigned AliasReg = *AI;
205 if (Classes[AliasReg]) {
206 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
207 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
208 }
209 }
210
211 // If we're still willing to consider this register, note the reference.
212 if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))
213 RegRefs.insert(std::make_pair(Reg, &MO));
214
215 // If this reg is tied and live (Classes[Reg] is set to -1), we can't change
216 // it or any of its sub or super regs. We need to use KeepRegs to mark the
217 // reg because not all uses of the same reg within an instruction are
218 // necessarily tagged as tied.
219 // Example: an x86 "xor %eax, %eax" will have one source operand tied to the
220 // def register but not the second (see PR20020 for details).
221 // FIXME: can this check be relaxed to account for undef uses
222 // of a register? In the above 'xor' example, the uses of %eax are undef, so
223 // earlier instructions could still replace %eax even though the 'xor'
224 // itself can't be changed.
225 if (MI.isRegTiedToUseOperand(i) &&
226 Classes[Reg] == reinterpret_cast<TargetRegisterClass *>(-1)) {
227 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
228 SubRegs.isValid(); ++SubRegs) {
229 KeepRegs.set(*SubRegs);
230 }
231 for (MCSuperRegIterator SuperRegs(Reg, TRI);
232 SuperRegs.isValid(); ++SuperRegs) {
233 KeepRegs.set(*SuperRegs);
234 }
235 }
236
237 if (MO.isUse() && Special) {
238 if (!KeepRegs.test(Reg)) {
239 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
240 SubRegs.isValid(); ++SubRegs)
241 KeepRegs.set(*SubRegs);
242 }
243 }
244 }
245}
246
247void CriticalAntiDepBreaker::ScanInstruction(MachineInstr &MI, unsigned Count) {
248 // Update liveness.
249 // Proceeding upwards, registers that are defed but not used in this
250 // instruction are now dead.
251 assert(!MI.isKill() && "Attempting to scan a kill instruction")((void)0);
252
253 if (!TII->isPredicated(MI)) {
20
←
Assuming the condition is true
→
21
←
Taking true branch
→
254 // Predicated defs are modeled as read + write, i.e. similar to two
255 // address updates.
256 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
22
←
Loop condition is true. Entering loop body
→
257 MachineOperand &MO = MI.getOperand(i);
258
259 if (MO.isRegMask()) {
23
←
Taking true branch
→
260 auto ClobbersPhysRegAndSubRegs = [&](unsigned PhysReg) {
261 for (MCSubRegIterator SRI(PhysReg, TRI, true); SRI.isValid(); ++SRI)
262 if (!MO.clobbersPhysReg(*SRI))
263 return false;
264
265 return true;
266 };
267
268 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
24
←
Assuming 'i' is not equal to 'e'
→
25
←
Loop condition is true. Entering loop body
→
28
←
Assuming 'i' is equal to 'e'
→
29
←
Loop condition is false. Execution continues on line 279
→
269 if (ClobbersPhysRegAndSubRegs(i)) {
26
←
Assuming the condition is false
→
27
←
Taking false branch
→
270 DefIndices[i] = Count;
271 KillIndices[i] = ~0u;
272 KeepRegs.reset(i);
273 Classes[i] = nullptr;
274 RegRefs.erase(i);
275 }
276 }
277 }
278
279 if (!MO.isReg()) continue;
30
←
Taking false branch
→
280 Register Reg = MO.getReg();
281 if (Reg == 0) continue;
31
←
Taking false branch
→
282 if (!MO.isDef()) continue;
32
←
Assuming the condition is false
→
33
←
Taking false branch
→
283
284 // Ignore two-addr defs.
285 if (MI.isRegTiedToUseOperand(i))
34
←
Taking false branch
→
286 continue;
287
288 // If we've already marked this reg as unchangeable, don't remove
289 // it or any of its subregs from KeepRegs.
290 bool Keep = KeepRegs.test(Reg);
291
292 // For the reg itself and all subregs: update the def to current;
293 // reset the kill state, any restrictions, and references.
294 for (MCSubRegIterator SRI(Reg, TRI, true); SRI.isValid(); ++SRI) {
35
←
Loop condition is false. Execution continues on line 304
→
295 unsigned SubregReg = *SRI;
296 DefIndices[SubregReg] = Count;
297 KillIndices[SubregReg] = ~0u;
298 Classes[SubregReg] = nullptr;
299 RegRefs.erase(SubregReg);
300 if (!Keep)
301 KeepRegs.reset(SubregReg);
302 }
303 // Conservatively mark super-registers as unusable.
304 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR)
36
←
Calling constructor for 'MCSuperRegIterator'
→
305 Classes[*SR] = reinterpret_cast<TargetRegisterClass *>(-1);
306 }
307 }
308 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
309 MachineOperand &MO = MI.getOperand(i);
310 if (!MO.isReg()) continue;
311 Register Reg = MO.getReg();
312 if (Reg == 0) continue;
313 if (!MO.isUse()) continue;
314
315 const TargetRegisterClass *NewRC = nullptr;
316 if (i < MI.getDesc().getNumOperands())
317 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
318
319 // For now, only allow the register to be changed if its register
320 // class is consistent across all uses.
321 if (!Classes[Reg] && NewRC)
322 Classes[Reg] = NewRC;
323 else if (!NewRC || Classes[Reg] != NewRC)
324 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
325
326 RegRefs.insert(std::make_pair(Reg, &MO));
327
328 // It wasn't previously live but now it is, this is a kill.
329 // Repeat for all aliases.
330 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
331 unsigned AliasReg = *AI;
332 if (KillIndices[AliasReg] == ~0u) {
333 KillIndices[AliasReg] = Count;
334 DefIndices[AliasReg] = ~0u;
335 }
336 }
337 }
338}
339
340// Check all machine operands that reference the antidependent register and must
341// be replaced by NewReg. Return true if any of their parent instructions may
342// clobber the new register.
343//
344// Note: AntiDepReg may be referenced by a two-address instruction such that
345// it's use operand is tied to a def operand. We guard against the case in which
346// the two-address instruction also defines NewReg, as may happen with
347// pre/postincrement loads. In this case, both the use and def operands are in
348// RegRefs because the def is inserted by PrescanInstruction and not erased
349// during ScanInstruction. So checking for an instruction with definitions of
350// both NewReg and AntiDepReg covers it.
351bool
352CriticalAntiDepBreaker::isNewRegClobberedByRefs(RegRefIter RegRefBegin,
353 RegRefIter RegRefEnd,
354 unsigned NewReg) {
355 for (RegRefIter I = RegRefBegin; I != RegRefEnd; ++I ) {
356 MachineOperand *RefOper = I->second;
357
358 // Don't allow the instruction defining AntiDepReg to earlyclobber its
359 // operands, in case they may be assigned to NewReg. In this case antidep
360 // breaking must fail, but it's too rare to bother optimizing.
361 if (RefOper->isDef() && RefOper->isEarlyClobber())
362 return true;
363
364 // Handle cases in which this instruction defines NewReg.
365 MachineInstr *MI = RefOper->getParent();
366 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
367 const MachineOperand &CheckOper = MI->getOperand(i);
368
369 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg))
370 return true;
371
372 if (!CheckOper.isReg() || !CheckOper.isDef() ||
373 CheckOper.getReg() != NewReg)
374 continue;
375
376 // Don't allow the instruction to define NewReg and AntiDepReg.
377 // When AntiDepReg is renamed it will be an illegal op.
378 if (RefOper->isDef())
379 return true;
380
381 // Don't allow an instruction using AntiDepReg to be earlyclobbered by
382 // NewReg.
383 if (CheckOper.isEarlyClobber())
384 return true;
385
386 // Don't allow inline asm to define NewReg at all. Who knows what it's
387 // doing with it.
388 if (MI->isInlineAsm())
389 return true;
390 }
391 }
392 return false;
393}
394
395unsigned CriticalAntiDepBreaker::
396findSuitableFreeRegister(RegRefIter RegRefBegin,
397 RegRefIter RegRefEnd,
398 unsigned AntiDepReg,
399 unsigned LastNewReg,
400 const TargetRegisterClass *RC,
401 SmallVectorImpl<unsigned> &Forbid) {
402 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
403 for (unsigned i = 0; i != Order.size(); ++i) {
404 unsigned NewReg = Order[i];
405 // Don't replace a register with itself.
406 if (NewReg == AntiDepReg) continue;
407 // Don't replace a register with one that was recently used to repair
408 // an anti-dependence with this AntiDepReg, because that would
409 // re-introduce that anti-dependence.
410 if (NewReg == LastNewReg) continue;
411 // If any instructions that define AntiDepReg also define the NewReg, it's
412 // not suitable. For example, Instruction with multiple definitions can
413 // result in this condition.
414 if (isNewRegClobberedByRefs(RegRefBegin, RegRefEnd, NewReg)) continue;
415 // If NewReg is dead and NewReg's most recent def is not before
416 // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
417 assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u))((void)0)
418 && "Kill and Def maps aren't consistent for AntiDepReg!")((void)0);
419 assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u))((void)0)
420 && "Kill and Def maps aren't consistent for NewReg!")((void)0);
421 if (KillIndices[NewReg] != ~0u ||
422 Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) ||
423 KillIndices[AntiDepReg] > DefIndices[NewReg])
424 continue;
425 // If NewReg overlaps any of the forbidden registers, we can't use it.
426 bool Forbidden = false;
427 for (unsigned R : Forbid)
428 if (TRI->regsOverlap(NewReg, R)) {
429 Forbidden = true;
430 break;
431 }
432 if (Forbidden) continue;
433 return NewReg;
434 }
435
436 // No registers are free and available!
437 return 0;
438}
439
440unsigned CriticalAntiDepBreaker::
441BreakAntiDependencies(const std::vector<SUnit> &SUnits,
442 MachineBasicBlock::iterator Begin,
443 MachineBasicBlock::iterator End,
444 unsigned InsertPosIndex,
445 DbgValueVector &DbgValues) {
446 // The code below assumes that there is at least one instruction,
447 // so just duck out immediately if the block is empty.
448 if (SUnits.empty()) return 0;
1
Assuming the condition is false
→
2
←
Taking false branch
→
449
450 // Keep a map of the MachineInstr*'s back to the SUnit representing them.
451 // This is used for updating debug information.
452 //
453 // FIXME: Replace this with the existing map in ScheduleDAGInstrs::MISUnitMap
454 DenseMap<MachineInstr *, const SUnit *> MISUnitMap;
455
456 // Find the node at the bottom of the critical path.
457 const SUnit *Max = nullptr;
458 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
3
←
Assuming 'i' is not equal to 'e'
→
4
←
Loop condition is true. Entering loop body
→
5
←
Assuming 'i' is equal to 'e'
→
6
←
Loop condition is false. Execution continues on line 464
→
459 const SUnit *SU = &SUnits[i];
460 MISUnitMap[SU->getInstr()] = SU;
461 if (!Max
4.1
'Max' is null
4.1
'Max' is null
 || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency)
462 Max = SU;
463 }
464 assert(Max && "Failed to find bottom of the critical path")((void)0);
465
466#ifndef NDEBUG1
467 {
468 LLVM_DEBUG(dbgs() << "Critical path has total latency "do { } while (false)
469 << (Max->getDepth() + Max->Latency) << "\n")do { } while (false);
470 LLVM_DEBUG(dbgs() << "Available regs:")do { } while (false);
471 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
472 if (KillIndices[Reg] == ~0u)
473 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI))do { } while (false);
474 }
475 LLVM_DEBUG(dbgs() << '\n')do { } while (false);
476 }
477#endif
478
479 // Track progress along the critical path through the SUnit graph as we walk
480 // the instructions.
481 const SUnit *CriticalPathSU = Max;
482 MachineInstr *CriticalPathMI = CriticalPathSU->getInstr();
483
484 // Consider this pattern:
485 // A = ...
486 // ... = A
487 // A = ...
488 // ... = A
489 // A = ...
490 // ... = A
491 // A = ...
492 // ... = A
493 // There are three anti-dependencies here, and without special care,
494 // we'd break all of them using the same register:
495 // A = ...
496 // ... = A
497 // B = ...
498 // ... = B
499 // B = ...
500 // ... = B
501 // B = ...
502 // ... = B
503 // because at each anti-dependence, B is the first register that
504 // isn't A which is free. This re-introduces anti-dependencies
505 // at all but one of the original anti-dependencies that we were
506 // trying to break. To avoid this, keep track of the most recent
507 // register that each register was replaced with, avoid
508 // using it to repair an anti-dependence on the same register.
509 // This lets us produce this:
510 // A = ...
511 // ... = A
512 // B = ...
513 // ... = B
514 // C = ...
515 // ... = C
516 // B = ...
517 // ... = B
518 // This still has an anti-dependence on B, but at least it isn't on the
519 // original critical path.
520 //
521 // TODO: If we tracked more than one register here, we could potentially
522 // fix that remaining critical edge too. This is a little more involved,
523 // because unlike the most recent register, less recent registers should
524 // still be considered, though only if no other registers are available.
525 std::vector<unsigned> LastNewReg(TRI->getNumRegs(), 0);
526
527 // Attempt to break anti-dependence edges on the critical path. Walk the
528 // instructions from the bottom up, tracking information about liveness
529 // as we go to help determine which registers are available.
530 unsigned Broken = 0;
531 unsigned Count = InsertPosIndex - 1;
532 for (MachineBasicBlock::iterator I = End, E = Begin; I != E; --Count) {
7
←
Loop condition is true. Entering loop body
→
533 MachineInstr &MI = *--I;
534 // Kill instructions can define registers but are really nops, and there
535 // might be a real definition earlier that needs to be paired with uses
536 // dominated by this kill.
537
538 // FIXME: It may be possible to remove the isKill() restriction once PR18663
539 // has been properly fixed. There can be value in processing kills as seen
540 // in the AggressiveAntiDepBreaker class.
541 if (MI.isDebugInstr() || MI.isKill())
8
←
Taking false branch
→
542 continue;
543
544 // Check if this instruction has a dependence on the critical path that
545 // is an anti-dependence that we may be able to break. If it is, set
546 // AntiDepReg to the non-zero register associated with the anti-dependence.
547 //
548 // We limit our attention to the critical path as a heuristic to avoid
549 // breaking anti-dependence edges that aren't going to significantly
550 // impact the overall schedule. There are a limited number of registers
551 // and we want to save them for the important edges.
552 //
553 // TODO: Instructions with multiple defs could have multiple
554 // anti-dependencies. The current code here only knows how to break one
555 // edge per instruction. Note that we'd have to be able to break all of
556 // the anti-dependencies in an instruction in order to be effective.
557 unsigned AntiDepReg = 0;
558 if (&MI == CriticalPathMI) {
9
←
Assuming the condition is false
→
10
←
Taking false branch
→
559 if (const SDep *Edge = CriticalPathStep(CriticalPathSU)) {
560 const SUnit *NextSU = Edge->getSUnit();
561
562 // Only consider anti-dependence edges.
563 if (Edge->getKind() == SDep::Anti) {
564 AntiDepReg = Edge->getReg();
565 assert(AntiDepReg != 0 && "Anti-dependence on reg0?")((void)0);
566 if (!MRI.isAllocatable(AntiDepReg))
567 // Don't break anti-dependencies on non-allocatable registers.
568 AntiDepReg = 0;
569 else if (KeepRegs.test(AntiDepReg))
570 // Don't break anti-dependencies if a use down below requires
571 // this exact register.
572 AntiDepReg = 0;
573 else {
574 // If the SUnit has other dependencies on the SUnit that it
575 // anti-depends on, don't bother breaking the anti-dependency
576 // since those edges would prevent such units from being
577 // scheduled past each other regardless.
578 //
579 // Also, if there are dependencies on other SUnits with the
580 // same register as the anti-dependency, don't attempt to
581 // break it.
582 for (const SDep &P : CriticalPathSU->Preds)
583 if (P.getSUnit() == NextSU
584 ? (P.getKind() != SDep::Anti || P.getReg() != AntiDepReg)
585 : (P.getKind() == SDep::Data &&
586 P.getReg() == AntiDepReg)) {
587 AntiDepReg = 0;
588 break;
589 }
590 }
591 }
592 CriticalPathSU = NextSU;
593 CriticalPathMI = CriticalPathSU->getInstr();
594 } else {
595 // We've reached the end of the critical path.
596 CriticalPathSU = nullptr;
597 CriticalPathMI = nullptr;
598 }
599 }
600
601 PrescanInstruction(MI);
602
603 SmallVector<unsigned, 2> ForbidRegs;
604
605 // If MI's defs have a special allocation requirement, don't allow
606 // any def registers to be changed. Also assume all registers
607 // defined in a call must not be changed (ABI).
608 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI))
11
←
Assuming the condition is false
→
12
←
Assuming the condition is false
→
13
←
Assuming the condition is false
→
14
←
Taking false branch
→
609 // If this instruction's defs have special allocation requirement, don't
610 // break this anti-dependency.
611 AntiDepReg = 0;
612 else if (AntiDepReg
14.1
'AntiDepReg' is 0
14.1
'AntiDepReg' is 0
) {
15
←
Taking false branch
→
613 // If this instruction has a use of AntiDepReg, breaking it
614 // is invalid. If the instruction defines other registers,
615 // save a list of them so that we don't pick a new register
616 // that overlaps any of them.
617 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
618 MachineOperand &MO = MI.getOperand(i);
619 if (!MO.isReg()) continue;
620 Register Reg = MO.getReg();
621 if (Reg == 0) continue;
622 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) {
623 AntiDepReg = 0;
624 break;
625 }
626 if (MO.isDef() && Reg != AntiDepReg)
627 ForbidRegs.push_back(Reg);
628 }
629 }
630
631 // Determine AntiDepReg's register class, if it is live and is
632 // consistently used within a single class.
633 const TargetRegisterClass *RC = AntiDepReg
15.1
'AntiDepReg' is equal to 0
15.1
'AntiDepReg' is equal to 0
 != 0 ? Classes[AntiDepReg]
16
←
'?' condition is false
→
634 : nullptr;
635 assert((AntiDepReg == 0 || RC != nullptr) &&((void)0)
636 "Register should be live if it's causing an anti-dependence!")((void)0);
637 if (RC == reinterpret_cast<TargetRegisterClass *>(-1))
17
←
Taking false branch
→
638 AntiDepReg = 0;
639
640 // Look for a suitable register to use to break the anti-dependence.
641 //
642 // TODO: Instead of picking the first free register, consider which might
643 // be the best.
644 if (AntiDepReg
17.1
'AntiDepReg' is equal to 0
17.1
'AntiDepReg' is equal to 0
 != 0) {
18
←
Taking false branch
→
645 std::pair<std::multimap<unsigned, MachineOperand *>::iterator,
646 std::multimap<unsigned, MachineOperand *>::iterator>
647 Range = RegRefs.equal_range(AntiDepReg);
648 if (unsigned NewReg = findSuitableFreeRegister(Range.first, Range.second,
649 AntiDepReg,
650 LastNewReg[AntiDepReg],
651 RC, ForbidRegs)) {
652 LLVM_DEBUG(dbgs() << "Breaking anti-dependence edge on "do { } while (false)
653 << printReg(AntiDepReg, TRI) << " with "do { } while (false)
654 << RegRefs.count(AntiDepReg) << " references"do { } while (false)
655 << " using " << printReg(NewReg, TRI) << "!\n")do { } while (false);
656
657 // Update the references to the old register to refer to the new
658 // register.
659 for (std::multimap<unsigned, MachineOperand *>::iterator
660 Q = Range.first, QE = Range.second; Q != QE; ++Q) {
661 Q->second->setReg(NewReg);
662 // If the SU for the instruction being updated has debug information
663 // related to the anti-dependency register, make sure to update that
664 // as well.
665 const SUnit *SU = MISUnitMap[Q->second->getParent()];
666 if (!SU) continue;
667 UpdateDbgValues(DbgValues, Q->second->getParent(),
668 AntiDepReg, NewReg);
669 }
670
671 // We just went back in time and modified history; the
672 // liveness information for the anti-dependence reg is now
673 // inconsistent. Set the state as if it were dead.
674 Classes[NewReg] = Classes[AntiDepReg];
675 DefIndices[NewReg] = DefIndices[AntiDepReg];
676 KillIndices[NewReg] = KillIndices[AntiDepReg];
677 assert(((KillIndices[NewReg] == ~0u) !=((void)0)
678 (DefIndices[NewReg] == ~0u)) &&((void)0)
679 "Kill and Def maps aren't consistent for NewReg!")((void)0);
680
681 Classes[AntiDepReg] = nullptr;
682 DefIndices[AntiDepReg] = KillIndices[AntiDepReg];
683 KillIndices[AntiDepReg] = ~0u;
684 assert(((KillIndices[AntiDepReg] == ~0u) !=((void)0)
685 (DefIndices[AntiDepReg] == ~0u)) &&((void)0)
686 "Kill and Def maps aren't consistent for AntiDepReg!")((void)0);
687
688 RegRefs.erase(AntiDepReg);
689 LastNewReg[AntiDepReg] = NewReg;
690 ++Broken;
691 }
692 }
693
694 ScanInstruction(MI, Count);
19
←
Calling 'CriticalAntiDepBreaker::ScanInstruction'
→
695 }
696
697 return Broken;
698}
699
700AntiDepBreaker *
701llvm::createCriticalAntiDepBreaker(MachineFunction &MFi,
702 const RegisterClassInfo &RCI) {
703 return new CriticalAntiDepBreaker(MFi, RCI);
704}
←

/usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/MC/MCRegisterInfo.h

1//===- MC/MCRegisterInfo.h - Target Register Description --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes an abstract interface used to get information about a
10// target machines register file. This information is used for a variety of
11// purposed, especially register allocation.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_MC_MCREGISTERINFO_H
16#define LLVM_MC_MCREGISTERINFO_H
17
18#include "llvm/ADT/DenseMap.h"
19#include "llvm/ADT/iterator.h"
20#include "llvm/ADT/iterator_range.h"
21#include "llvm/MC/LaneBitmask.h"
22#include "llvm/MC/MCRegister.h"
23#include <cassert>
24#include <cstdint>
25#include <iterator>
26#include <utility>
27
28namespace llvm {
29
30/// MCRegisterClass - Base class of TargetRegisterClass.
31class MCRegisterClass {
32public:
33 using iterator = const MCPhysReg*;
34 using const_iterator = const MCPhysReg*;
35
36 const iterator RegsBegin;
37 const uint8_t *const RegSet;
38 const uint32_t NameIdx;
39 const uint16_t RegsSize;
40 const uint16_t RegSetSize;
41 const uint16_t ID;
42 const uint16_t RegSizeInBits;
43 const int8_t CopyCost;
44 const bool Allocatable;
45
46 /// getID() - Return the register class ID number.
47 ///
48 unsigned getID() const { return ID; }
49
50 /// begin/end - Return all of the registers in this class.
51 ///
52 iterator begin() const { return RegsBegin; }
53 iterator end() const { return RegsBegin + RegsSize; }
54
55 /// getNumRegs - Return the number of registers in this class.
56 ///
57 unsigned getNumRegs() const { return RegsSize; }
58
59 /// getRegister - Return the specified register in the class.
60 ///
61 unsigned getRegister(unsigned i) const {
62 assert(i < getNumRegs() && "Register number out of range!")((void)0);
63 return RegsBegin[i];
64 }
65
66 /// contains - Return true if the specified register is included in this
67 /// register class. This does not include virtual registers.
68 bool contains(MCRegister Reg) const {
69 unsigned RegNo = unsigned(Reg);
70 unsigned InByte = RegNo % 8;
71 unsigned Byte = RegNo / 8;
72 if (Byte >= RegSetSize)
73 return false;
74 return (RegSet[Byte] & (1 << InByte)) != 0;
75 }
76
77 /// contains - Return true if both registers are in this class.
78 bool contains(MCRegister Reg1, MCRegister Reg2) const {
79 return contains(Reg1) && contains(Reg2);
80 }
81
82 /// Return the size of the physical register in bits if we are able to
83 /// determine it. This always returns zero for registers of targets that use
84 /// HW modes, as we need more information to determine the size of registers
85 /// in such cases. Use TargetRegisterInfo to cover them.
86 unsigned getSizeInBits() const { return RegSizeInBits; }
87
88 /// getCopyCost - Return the cost of copying a value between two registers in
89 /// this class. A negative number means the register class is very expensive
90 /// to copy e.g. status flag register classes.
91 int getCopyCost() const { return CopyCost; }
92
93 /// isAllocatable - Return true if this register class may be used to create
94 /// virtual registers.
95 bool isAllocatable() const { return Allocatable; }
96};
97
98/// MCRegisterDesc - This record contains information about a particular
99/// register. The SubRegs field is a zero terminated array of registers that
100/// are sub-registers of the specific register, e.g. AL, AH are sub-registers
101/// of AX. The SuperRegs field is a zero terminated array of registers that are
102/// super-registers of the specific register, e.g. RAX, EAX, are
103/// super-registers of AX.
104///
105struct MCRegisterDesc {
106 uint32_t Name; // Printable name for the reg (for debugging)
107 uint32_t SubRegs; // Sub-register set, described above
108 uint32_t SuperRegs; // Super-register set, described above
109
110 // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
111 // sub-register in SubRegs.
112 uint32_t SubRegIndices;
113
114 // RegUnits - Points to the list of register units. The low 4 bits holds the
115 // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
116 uint32_t RegUnits;
117
118 /// Index into list with lane mask sequences. The sequence contains a lanemask
119 /// for every register unit.
120 uint16_t RegUnitLaneMasks;
121};
122
123/// MCRegisterInfo base class - We assume that the target defines a static
124/// array of MCRegisterDesc objects that represent all of the machine
125/// registers that the target has. As such, we simply have to track a pointer
126/// to this array so that we can turn register number into a register
127/// descriptor.
128///
129/// Note this class is designed to be a base class of TargetRegisterInfo, which
130/// is the interface used by codegen. However, specific targets *should never*
131/// specialize this class. MCRegisterInfo should only contain getters to access
132/// TableGen generated physical register data. It must not be extended with
133/// virtual methods.
134///
135class MCRegisterInfo {
136public:
137 using regclass_iterator = const MCRegisterClass *;
138
139 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be
140 /// performed with a binary search.
141 struct DwarfLLVMRegPair {
142 unsigned FromReg;
143 unsigned ToReg;
144
145 bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; }
146 };
147
148 /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
149 /// index, -1 in any being invalid.
150 struct SubRegCoveredBits {
151 uint16_t Offset;
152 uint16_t Size;
153 };
154
155private:
156 const MCRegisterDesc *Desc; // Pointer to the descriptor array
157 unsigned NumRegs; // Number of entries in the array
158 MCRegister RAReg; // Return address register
159 MCRegister PCReg; // Program counter register
160 const MCRegisterClass *Classes; // Pointer to the regclass array
161 unsigned NumClasses; // Number of entries in the array
162 unsigned NumRegUnits; // Number of regunits.
163 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
164 const MCPhysReg *DiffLists; // Pointer to the difflists array
165 const LaneBitmask *RegUnitMaskSequences; // Pointer to lane mask sequences
166 // for register units.
167 const char *RegStrings; // Pointer to the string table.
168 const char *RegClassStrings; // Pointer to the class strings.
169 const uint16_t *SubRegIndices; // Pointer to the subreg lookup
170 // array.
171 const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered
172 // bit ranges array.
173 unsigned NumSubRegIndices; // Number of subreg indices.
174 const uint16_t *RegEncodingTable; // Pointer to array of register
175 // encodings.
176
177 unsigned L2DwarfRegsSize;
178 unsigned EHL2DwarfRegsSize;
179 unsigned Dwarf2LRegsSize;
180 unsigned EHDwarf2LRegsSize;
181 const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping
182 const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
183 const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping
184 const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
185 DenseMap<MCRegister, int> L2SEHRegs; // LLVM to SEH regs mapping
186 DenseMap<MCRegister, int> L2CVRegs; // LLVM to CV regs mapping
187
188public:
189 // Forward declaration to become a friend class of DiffListIterator.
190 template <class SubT> class mc_difflist_iterator;
191
192 /// DiffListIterator - Base iterator class that can traverse the
193 /// differentially encoded register and regunit lists in DiffLists.
194 /// Don't use this class directly, use one of the specialized sub-classes
195 /// defined below.
196 class DiffListIterator {
197 uint16_t Val = 0;
198 const MCPhysReg *List = nullptr;
199
200 protected:
201 /// Create an invalid iterator. Call init() to point to something useful.
202 DiffListIterator() = default;
203
204 /// init - Point the iterator to InitVal, decoding subsequent values from
205 /// DiffList. The iterator will initially point to InitVal, sub-classes are
206 /// responsible for skipping the seed value if it is not part of the list.
207 void init(MCPhysReg InitVal, const MCPhysReg *DiffList) {
208 Val = InitVal;
209 List = DiffList;
210 }
211
212 /// advance - Move to the next list position, return the applied
213 /// differential. This function does not detect the end of the list, that
214 /// is the caller's responsibility (by checking for a 0 return value).
215 MCRegister advance() {
216 assert(isValid() && "Cannot move off the end of the list.")((void)0);
217 MCPhysReg D = *List++;
40
←
Dereference of null pointer
218 Val += D;
219 return D;
220 }
221
222 public:
223 /// isValid - returns true if this iterator is not yet at the end.
224 bool isValid() const { return List; }
225
226 /// Dereference the iterator to get the value at the current position.
227 MCRegister operator*() const { return Val; }
228
229 /// Pre-increment to move to the next position.
230 void operator++() {
231 // The end of the list is encoded as a 0 differential.
232 if (!advance())
39
←
Calling 'DiffListIterator::advance'
→
233 List = nullptr;
234 }
235
236 template <class SubT> friend class MCRegisterInfo::mc_difflist_iterator;
237 };
238
239 /// Forward iterator using DiffListIterator.
240 template <class SubT>
241 class mc_difflist_iterator
242 : public iterator_facade_base<mc_difflist_iterator<SubT>,
243 std::forward_iterator_tag, MCPhysReg> {
244 MCRegisterInfo::DiffListIterator Iter;
245 /// Current value as MCPhysReg, so we can return a reference to it.
246 MCPhysReg Val;
247
248 protected:
249 mc_difflist_iterator(MCRegisterInfo::DiffListIterator Iter) : Iter(Iter) {}
250
251 // Allow conversion between instantiations where valid.
252 mc_difflist_iterator(MCRegister Reg, const MCPhysReg *DiffList) {
253 Iter.init(Reg, DiffList);
254 Val = *Iter;
255 }
256
257 public:
258 // Allow default construction to build variables, but this doesn't build
259 // a useful iterator.
260 mc_difflist_iterator() = default;
261
262 /// Return an iterator past the last element.
263 static SubT end() {
264 SubT End;
265 End.Iter.List = nullptr;
266 return End;
267 }
268
269 bool operator==(const mc_difflist_iterator &Arg) const {
270 return Iter.List == Arg.Iter.List;
271 }
272
273 const MCPhysReg &operator*() const { return Val; }
274
275 using mc_difflist_iterator::iterator_facade_base::operator++;
276 void operator++() {
277 assert(Iter.List && "Cannot increment the end iterator!")((void)0);
278 ++Iter;
279 Val = *Iter;
280 }
281 };
282
283 /// Forward iterator over all sub-registers.
284 /// TODO: Replace remaining uses of MCSubRegIterator.
285 class mc_subreg_iterator : public mc_difflist_iterator<mc_subreg_iterator> {
286 public:
287 mc_subreg_iterator(MCRegisterInfo::DiffListIterator Iter)
288 : mc_difflist_iterator(Iter) {}
289 mc_subreg_iterator() = default;
290 mc_subreg_iterator(MCRegister Reg, const MCRegisterInfo *MCRI)
291 : mc_difflist_iterator(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs) {}
292 };
293
294 /// Forward iterator over all super-registers.
295 /// TODO: Replace remaining uses of MCSuperRegIterator.
296 class mc_superreg_iterator
297 : public mc_difflist_iterator<mc_superreg_iterator> {
298 public:
299 mc_superreg_iterator(MCRegisterInfo::DiffListIterator Iter)
300 : mc_difflist_iterator(Iter) {}
301 mc_superreg_iterator() = default;
302 mc_superreg_iterator(MCRegister Reg, const MCRegisterInfo *MCRI)
303 : mc_difflist_iterator(Reg,
304 MCRI->DiffLists + MCRI->get(Reg).SuperRegs) {}
305 };
306
307 /// Return an iterator range over all sub-registers of \p Reg, excluding \p
308 /// Reg.
309 iterator_range<mc_subreg_iterator> subregs(MCRegister Reg) const {
310 return make_range(std::next(mc_subreg_iterator(Reg, this)),
311 mc_subreg_iterator::end());
312 }
313
314 /// Return an iterator range over all sub-registers of \p Reg, including \p
315 /// Reg.
316 iterator_range<mc_subreg_iterator> subregs_inclusive(MCRegister Reg) const {
317 return make_range({Reg, this}, mc_subreg_iterator::end());
318 }
319
320 /// Return an iterator range over all super-registers of \p Reg, excluding \p
321 /// Reg.
322 iterator_range<mc_superreg_iterator> superregs(MCRegister Reg) const {
323 return make_range(std::next(mc_superreg_iterator(Reg, this)),
324 mc_superreg_iterator::end());
325 }
326
327 /// Return an iterator range over all super-registers of \p Reg, including \p
328 /// Reg.
329 iterator_range<mc_superreg_iterator>
330 superregs_inclusive(MCRegister Reg) const {
331 return make_range({Reg, this}, mc_superreg_iterator::end());
332 }
333
334 /// Return an iterator range over all sub- and super-registers of \p Reg,
335 /// including \p Reg.
336 detail::concat_range<const MCPhysReg, iterator_range<mc_subreg_iterator>,
337 iterator_range<mc_superreg_iterator>>
338 sub_and_superregs_inclusive(MCRegister Reg) const {
339 return concat<const MCPhysReg>(subregs_inclusive(Reg), superregs(Reg));
340 }
341
342 // These iterators are allowed to sub-class DiffListIterator and access
343 // internal list pointers.
344 friend class MCSubRegIterator;
345 friend class MCSubRegIndexIterator;
346 friend class MCSuperRegIterator;
347 friend class MCRegUnitIterator;
348 friend class MCRegUnitMaskIterator;
349 friend class MCRegUnitRootIterator;
350
351 /// Initialize MCRegisterInfo, called by TableGen
352 /// auto-generated routines. *DO NOT USE*.
353 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
354 unsigned PC,
355 const MCRegisterClass *C, unsigned NC,
356 const MCPhysReg (*RURoots)[2],
357 unsigned NRU,
358 const MCPhysReg *DL,
359 const LaneBitmask *RUMS,
360 const char *Strings,
361 const char *ClassStrings,
362 const uint16_t *SubIndices,
363 unsigned NumIndices,
364 const SubRegCoveredBits *SubIdxRanges,
365 const uint16_t *RET) {
366 Desc = D;
367 NumRegs = NR;
368 RAReg = RA;
369 PCReg = PC;
370 Classes = C;
371 DiffLists = DL;
372 RegUnitMaskSequences = RUMS;
373 RegStrings = Strings;
374 RegClassStrings = ClassStrings;
375 NumClasses = NC;
376 RegUnitRoots = RURoots;
377 NumRegUnits = NRU;
378 SubRegIndices = SubIndices;
379 NumSubRegIndices = NumIndices;
380 SubRegIdxRanges = SubIdxRanges;
381 RegEncodingTable = RET;
382
383 // Initialize DWARF register mapping variables
384 EHL2DwarfRegs = nullptr;
385 EHL2DwarfRegsSize = 0;
386 L2DwarfRegs = nullptr;
387 L2DwarfRegsSize = 0;
388 EHDwarf2LRegs = nullptr;
389 EHDwarf2LRegsSize = 0;
390 Dwarf2LRegs = nullptr;
391 Dwarf2LRegsSize = 0;
392 }
393
394 /// Used to initialize LLVM register to Dwarf
395 /// register number mapping. Called by TableGen auto-generated routines.
396 /// *DO NOT USE*.
397 void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
398 bool isEH) {
399 if (isEH) {
400 EHL2DwarfRegs = Map;
401 EHL2DwarfRegsSize = Size;
402 } else {
403 L2DwarfRegs = Map;
404 L2DwarfRegsSize = Size;
405 }
406 }
407
408 /// Used to initialize Dwarf register to LLVM
409 /// register number mapping. Called by TableGen auto-generated routines.
410 /// *DO NOT USE*.
411 void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size,
412 bool isEH) {
413 if (isEH) {
414 EHDwarf2LRegs = Map;
415 EHDwarf2LRegsSize = Size;
416 } else {
417 Dwarf2LRegs = Map;
418 Dwarf2LRegsSize = Size;
419 }
420 }
421
422 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
423 /// number mapping. By default the SEH register number is just the same
424 /// as the LLVM register number.
425 /// FIXME: TableGen these numbers. Currently this requires target specific
426 /// initialization code.
427 void mapLLVMRegToSEHReg(MCRegister LLVMReg, int SEHReg) {
428 L2SEHRegs[LLVMReg] = SEHReg;
429 }
430
431 void mapLLVMRegToCVReg(MCRegister LLVMReg, int CVReg) {
432 L2CVRegs[LLVMReg] = CVReg;
433 }
434
435 /// This method should return the register where the return
436 /// address can be found.
437 MCRegister getRARegister() const {
438 return RAReg;
439 }
440
441 /// Return the register which is the program counter.
442 MCRegister getProgramCounter() const {
443 return PCReg;
444 }
445
446 const MCRegisterDesc &operator[](MCRegister RegNo) const {
447 assert(RegNo < NumRegs &&((void)0)
448 "Attempting to access record for invalid register number!")((void)0);
449 return Desc[RegNo];
450 }
451
452 /// Provide a get method, equivalent to [], but more useful with a
453 /// pointer to this object.
454 const MCRegisterDesc &get(MCRegister RegNo) const {
455 return operator[](RegNo);
456 }
457
458 /// Returns the physical register number of sub-register "Index"
459 /// for physical register RegNo. Return zero if the sub-register does not
460 /// exist.
461 MCRegister getSubReg(MCRegister Reg, unsigned Idx) const;
462
463 /// Return a super-register of the specified register
464 /// Reg so its sub-register of index SubIdx is Reg.
465 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,
466 const MCRegisterClass *RC) const;
467
468 /// For a given register pair, return the sub-register index
469 /// if the second register is a sub-register of the first. Return zero
470 /// otherwise.
471 unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const;
472
473 /// Get the size of the bit range covered by a sub-register index.
474 /// If the index isn't continuous, return the sum of the sizes of its parts.
475 /// If the index is used to access subregisters of different sizes, return -1.
476 unsigned getSubRegIdxSize(unsigned Idx) const;
477
478 /// Get the offset of the bit range covered by a sub-register index.
479 /// If an Offset doesn't make sense (the index isn't continuous, or is used to
480 /// access sub-registers at different offsets), return -1.
481 unsigned getSubRegIdxOffset(unsigned Idx) const;
482
483 /// Return the human-readable symbolic target-specific name for the
484 /// specified physical register.
485 const char *getName(MCRegister RegNo) const {
486 return RegStrings + get(RegNo).Name;
487 }
488
489 /// Return the number of registers this target has (useful for
490 /// sizing arrays holding per register information)
491 unsigned getNumRegs() const {
492 return NumRegs;
493 }
494
495 /// Return the number of sub-register indices
496 /// understood by the target. Index 0 is reserved for the no-op sub-register,
497 /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
498 unsigned getNumSubRegIndices() const {
499 return NumSubRegIndices;
500 }
501
502 /// Return the number of (native) register units in the
503 /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
504 /// can be accessed through MCRegUnitIterator defined below.
505 unsigned getNumRegUnits() const {
506 return NumRegUnits;
507 }
508
509 /// Map a target register to an equivalent dwarf register
510 /// number. Returns -1 if there is no equivalent value. The second
511 /// parameter allows targets to use different numberings for EH info and
512 /// debugging info.
513 int getDwarfRegNum(MCRegister RegNum, bool isEH) const;
514
515 /// Map a dwarf register back to a target register. Returns None is there is
516 /// no mapping.
517 Optional<unsigned> getLLVMRegNum(unsigned RegNum, bool isEH) const;
518
519 /// Map a target EH register number to an equivalent DWARF register
520 /// number.
521 int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const;
522
523 /// Map a target register to an equivalent SEH register
524 /// number. Returns LLVM register number if there is no equivalent value.
525 int getSEHRegNum(MCRegister RegNum) const;
526
527 /// Map a target register to an equivalent CodeView register
528 /// number.
529 int getCodeViewRegNum(MCRegister RegNum) const;
530
531 regclass_iterator regclass_begin() const { return Classes; }
532 regclass_iterator regclass_end() const { return Classes+NumClasses; }
533 iterator_range<regclass_iterator> regclasses() const {
534 return make_range(regclass_begin(), regclass_end());
535 }
536
537 unsigned getNumRegClasses() const {
538 return (unsigned)(regclass_end()-regclass_begin());
539 }
540
541 /// Returns the register class associated with the enumeration
542 /// value. See class MCOperandInfo.
543 const MCRegisterClass& getRegClass(unsigned i) const {
544 assert(i < getNumRegClasses() && "Register Class ID out of range")((void)0);
545 return Classes[i];
546 }
547
548 const char *getRegClassName(const MCRegisterClass *Class) const {
549 return RegClassStrings + Class->NameIdx;
550 }
551
552 /// Returns the encoding for RegNo
553 uint16_t getEncodingValue(MCRegister RegNo) const {
554 assert(RegNo < NumRegs &&((void)0)
555 "Attempting to get encoding for invalid register number!")((void)0);
556 return RegEncodingTable[RegNo];
557 }
558
559 /// Returns true if RegB is a sub-register of RegA.
560 bool isSubRegister(MCRegister RegA, MCRegister RegB) const {
561 return isSuperRegister(RegB, RegA);
562 }
563
564 /// Returns true if RegB is a super-register of RegA.
565 bool isSuperRegister(MCRegister RegA, MCRegister RegB) const;
566
567 /// Returns true if RegB is a sub-register of RegA or if RegB == RegA.
568 bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const {
569 return isSuperRegisterEq(RegB, RegA);
570 }
571
572 /// Returns true if RegB is a super-register of RegA or if
573 /// RegB == RegA.
574 bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const {
575 return RegA == RegB || isSuperRegister(RegA, RegB);
576 }
577
578 /// Returns true if RegB is a super-register or sub-register of RegA
579 /// or if RegB == RegA.
580 bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const {
581 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB);
582 }
583};
584
585//===----------------------------------------------------------------------===//
586// Register List Iterators
587//===----------------------------------------------------------------------===//
588
589// MCRegisterInfo provides lists of super-registers, sub-registers, and
590// aliasing registers. Use these iterator classes to traverse the lists.
591
592/// MCSubRegIterator enumerates all sub-registers of Reg.
593/// If IncludeSelf is set, Reg itself is included in the list.
594class MCSubRegIterator : public MCRegisterInfo::DiffListIterator {
595public:
596 MCSubRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI,
597 bool IncludeSelf = false) {
598 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
599 // Initially, the iterator points to Reg itself.
600 if (!IncludeSelf)
601 ++*this;
602 }
603};
604
605/// Iterator that enumerates the sub-registers of a Reg and the associated
606/// sub-register indices.
607class MCSubRegIndexIterator {
608 MCSubRegIterator SRIter;
609 const uint16_t *SRIndex;
610
611public:
612 /// Constructs an iterator that traverses subregisters and their
613 /// associated subregister indices.
614 MCSubRegIndexIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
615 : SRIter(Reg, MCRI) {
616 SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices;
617 }
618
619 /// Returns current sub-register.
620 MCRegister getSubReg() const {
621 return *SRIter;
622 }
623
624 /// Returns sub-register index of the current sub-register.
625 unsigned getSubRegIndex() const {
626 return *SRIndex;
627 }
628
629 /// Returns true if this iterator is not yet at the end.
630 bool isValid() const { return SRIter.isValid(); }
631
632 /// Moves to the next position.
633 void operator++() {
634 ++SRIter;
635 ++SRIndex;
636 }
637};
638
639/// MCSuperRegIterator enumerates all super-registers of Reg.
640/// If IncludeSelf is set, Reg itself is included in the list.
641class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator {
642public:
643 MCSuperRegIterator() = default;
644
645 MCSuperRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI,
646 bool IncludeSelf = false) {
647 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
648 // Initially, the iterator points to Reg itself.
649 if (!IncludeSelf
36.1
'IncludeSelf' is false
36.1
'IncludeSelf' is false
)
37
←
Taking true branch
→
650 ++*this;
38
←
Calling 'DiffListIterator::operator++'
→
651 }
652};
653
654// Definition for isSuperRegister. Put it down here since it needs the
655// iterator defined above in addition to the MCRegisterInfo class itself.
656inline bool MCRegisterInfo::isSuperRegister(MCRegister RegA, MCRegister RegB) const{
657 for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I)
658 if (*I == RegB)
659 return true;
660 return false;
661}
662
663//===----------------------------------------------------------------------===//
664// Register Units
665//===----------------------------------------------------------------------===//
666
667// Register units are used to compute register aliasing. Every register has at
668// least one register unit, but it can have more. Two registers overlap if and
669// only if they have a common register unit.
670//
671// A target with a complicated sub-register structure will typically have many
672// fewer register units than actual registers. MCRI::getNumRegUnits() returns
673// the number of register units in the target.
674
675// MCRegUnitIterator enumerates a list of register units for Reg. The list is
676// in ascending numerical order.
677class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator {
678public:
679 /// MCRegUnitIterator - Create an iterator that traverses the register units
680 /// in Reg.
681 MCRegUnitIterator() = default;
682
683 MCRegUnitIterator(MCRegister Reg, const MCRegisterInfo *MCRI) {
684 assert(Reg && "Null register has no regunits")((void)0);
685 assert(MCRegister::isPhysicalRegister(Reg.id()))((void)0);
686 // Decode the RegUnits MCRegisterDesc field.
687 unsigned RU = MCRI->get(Reg).RegUnits;
688 unsigned Scale = RU & 15;
689 unsigned Offset = RU >> 4;
690
691 // Initialize the iterator to Reg * Scale, and the List pointer to
692 // DiffLists + Offset.
693 init(Reg * Scale, MCRI->DiffLists + Offset);
694
695 // That may not be a valid unit, we need to advance by one to get the real
696 // unit number. The first differential can be 0 which would normally
697 // terminate the list, but since we know every register has at least one
698 // unit, we can allow a 0 differential here.
699 advance();
700 }
701};
702
703/// MCRegUnitMaskIterator enumerates a list of register units and their
704/// associated lane masks for Reg. The register units are in ascending
705/// numerical order.
706class MCRegUnitMaskIterator {
707 MCRegUnitIterator RUIter;
708 const LaneBitmask *MaskListIter;
709
710public:
711 MCRegUnitMaskIterator() = default;
712
713 /// Constructs an iterator that traverses the register units and their
714 /// associated LaneMasks in Reg.
715 MCRegUnitMaskIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
716 : RUIter(Reg, MCRI) {
717 uint16_t Idx = MCRI->get(Reg).RegUnitLaneMasks;
718 MaskListIter = &MCRI->RegUnitMaskSequences[Idx];
719 }
720
721 /// Returns a (RegUnit, LaneMask) pair.
722 std::pair<unsigned,LaneBitmask> operator*() const {
723 return std::make_pair(*RUIter, *MaskListIter);
724 }
725
726 /// Returns true if this iterator is not yet at the end.
727 bool isValid() const { return RUIter.isValid(); }
728
729 /// Moves to the next position.
730 void operator++() {
731 ++MaskListIter;
732 ++RUIter;
733 }
734};
735
736// Each register unit has one or two root registers. The complete set of
737// registers containing a register unit is the union of the roots and their
738// super-registers. All registers aliasing Unit can be visited like this:
739//
740// for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
741// for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI)
742// visit(*SI);
743// }
744
745/// MCRegUnitRootIterator enumerates the root registers of a register unit.
746class MCRegUnitRootIterator {
747 uint16_t Reg0 = 0;
748 uint16_t Reg1 = 0;
749
750public:
751 MCRegUnitRootIterator() = default;
752
753 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
754 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit")((void)0);
755 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
756 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
757 }
758
759 /// Dereference to get the current root register.
760 unsigned operator*() const {
761 return Reg0;
762 }
763
764 /// Check if the iterator is at the end of the list.
765 bool isValid() const {
766 return Reg0;
767 }
768
769 /// Preincrement to move to the next root register.
770 void operator++() {
771 assert(isValid() && "Cannot move off the end of the list.")((void)0);
772 Reg0 = Reg1;
773 Reg1 = 0;
774 }
775};
776
777/// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSelf is
778/// set, Reg itself is included in the list. This iterator does not guarantee
779/// any ordering or that entries are unique.
780class MCRegAliasIterator {
781private:
782 MCRegister Reg;
783 const MCRegisterInfo *MCRI;
784 bool IncludeSelf;
785
786 MCRegUnitIterator RI;
787 MCRegUnitRootIterator RRI;
788 MCSuperRegIterator SI;
789
790public:
791 MCRegAliasIterator(MCRegister Reg, const MCRegisterInfo *MCRI,
792 bool IncludeSelf)
793 : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) {
794 // Initialize the iterators.
795 for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) {
796 for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) {
797 for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) {
798 if (!(!IncludeSelf && Reg == *SI))
799 return;
800 }
801 }
802 }
803 }
804
805 bool isValid() const { return RI.isValid(); }
806
807 MCRegister operator*() const {
808 assert(SI.isValid() && "Cannot dereference an invalid iterator.")((void)0);
809 return *SI;
810 }
811
812 void advance() {
813 // Assuming SI is valid.
814 ++SI;
815 if (SI.isValid()) return;
816
817 ++RRI;
818 if (RRI.isValid()) {
819 SI = MCSuperRegIterator(*RRI, MCRI, true);
820 return;
821 }
822
823 ++RI;
824 if (RI.isValid()) {
825 RRI = MCRegUnitRootIterator(*RI, MCRI);
826 SI = MCSuperRegIterator(*RRI, MCRI, true);
827 }
828 }
829
830 void operator++() {
831 assert(isValid() && "Cannot move off the end of the list.")((void)0);
832 do advance();
833 while (!IncludeSelf && isValid() && *SI == Reg);
834 }
835};
836
837} // end namespace llvm
838
839#endif // LLVM_MC_MCREGISTERINFO_H